WO2009153262A1

WO2009153262A1 - Control system

Info

Publication number: WO2009153262A1
Application number: PCT/EP2009/057475
Authority: WO
Inventors: Horst Flock
Original assignee: Afl Stribel Production Gmbh
Priority date: 2008-06-20
Filing date: 2009-06-16
Publication date: 2009-12-23
Also published as: DE102008030628B4; DE102008030628A1

Abstract

In order to improve upon a control system comprising a microcontroller and an EEPROM for storing data for the microcontroller in such a way that access by the microcontroller to the EEPROM can proceed without interference, it is proposed that a switch be provided between a power supply and a supply connection of the EEPROM, said switch able to be controlled by way of a control connection of the microcontroller, and that a system reset routine be provided in the microcontroller for issuing an interruption signal when a flow occurs at the control connection, wherein the switch opens for an interruption time duration and resets the EEPROM.

Description

CONTROL SYSTEM

The invention relates to a control system comprising a microcontroller and an EEPROM for storing data for the microcontroller.

Such control systems, in which a microcontroller cooperates with an EEPROM to store data of the microcontroller and make it available for the microcontroller, are known from the prior art. In these, there is the problem that in case of malfunction of the microcontroller in the data communication between the microcontroller and the EEPROM undefined states may occur and undefined data sets may be present, so that the EEPROM in this case either stores incorrect data or incorrect data to the microcontroller represents.

The invention is therefore an object of the invention to improve a control system of the type mentioned in such a way that the access of the microcontroller to the EEPROM can be done trouble-free.

This object is achieved in a control system of the type mentioned in the present invention that between a power supply and a supply terminal of the EEPROM, a switch is provided, which is controllable by a control terminal of the microcontroller, and that in the microcontroller, a system reset routine is provided which at a Pass on the control terminal outputs an interrupt signal which opens the switch for an interruption period and resets the EEPROM. The advantage of the solution according to the invention is to be seen in the fact that thus can be ensured by the system reset routine in the microcontroller, which is automatically started after a malfunction of the microcontroller in this, that also a reset of the EEPROM takes place, so that in particular at its inputs fitting information or control commands are deleted and do not falsify the data to be transmitted in a later access of the microcontroller to the EEPROM.

This can ensure that after each malfunction of the microcontroller again a reliable transmission of data between the microcontroller and EEPROM is possible without the malfunctioning signals or data are not deleted.

Since, in the solution according to the invention, the system reset routine outputs the interrupt signal without taking into account the state of the microcontroller and the EEPROM in which the malfunction occurred, it is preferably provided that the system reset routine output the interrupt signal after a defined waiting time from the start of the system reset routine.

This solution has the advantage that it creates the possibility of operating the EEPROM after the start of the system reset routine of the microcontroller for so long that it can complete processes that have already begun.

A particularly expedient solution provides that the defined waiting time corresponds at least to the writing time duration of the EEPROM. This can be ensured that in the event that, then, when occurring the malfunction has already started the EEPROM to write the transmitted data into its memory, the EEPROM has the ability to terminate this writing without being reset by the interrupt signal, so that the already completely transmitted data can be reliably stored in the EEPROM ,

Preferably, it is provided that the defined waiting time is at least 10 ms even better 20 ms.

With regard to the communication between the microcontroller and the EEPROM so far no further details have been made.

Thus, it is preferably provided that the microcontroller exchanges data with the EEPROM via an interface.

Such an interface is, for example, a common interface used for EEPROMs.

For example, the interface is an SPI interface.

In order to prevent signals or data still being present through the interface which have not been deleted after the malfunction of the microcontroller has occurred, it is preferably provided that the system reset routine effects a reset of the interface before the interruption signal is triggered. This deletes existing data and commands in the interface that were not executed due to the function control of the microcontroller.

Furthermore, it is preferably provided that the interrupt signal is terminated before an initialization of the interface by the system reset routine.

This means that the EEPROM is also completely reset by the interruption signal and any data that has not yet been saved by the malfunction or that has not been executed is deleted from the EEPROM before the interface is again initialized by the microcontroller.

Further features and advantages of the invention are the subject of the following description and the drawings of an embodiment.

In the drawing shows:

Fig. 1 is a schematic representation of an inventive

Control system with a microcontroller and an EEPROM.

An embodiment of a control system according to the invention, shown in FIG. 1, comprises a microcontroller designated as a whole by 10, which is connected to a supply voltage on the one hand to a supply voltage UV and on the other hand to ground for operation. The microcontroller 10 includes a plurality of terminals 12, which may be either outputs for control signals or inputs for signals.

Furthermore, the microcontroller 10 comprises connections 14 of an SPI interface unit 16, via which data is communicated with an SPI interface unit 18 of an EEPROM designated as a whole by 20, for example an EEPROM of the type 25AA256 or 25LC256 with SPI interface from Microchip Technology Inc. , which in turn has the terminals 14 of the microcontroller 10 corresponding terminals 22 which are interconnected by a wiring harness 23.

To operate the EEPROM 20, a supply terminal 24 thereof is connected to the supply voltage UV and a ground terminal 26 thereof with the mass M.

Furthermore, the EEPROM still has a hold connection 28, which could be controlled separately, but in the described embodiment is not separately driven and is therefore connected via a tap 32 to the supply terminal 24.

Further, between the tap 32 and the mass M is still a capacitor 34, which serves to filter the taps 32 occurring interference by the EEPROM. The capacitance of the capacitor 34 is for example in the range of 10 nF to 100 nF. Between the tap 32 and the supply voltage UV is a switch 40, which is designed as a transistor, wherein a base 42 of this transistor 40 is connected via a voltage divider 44 to the ground M and a center tap 46 of the voltage divider 44 to a control terminal 48 of the microcontroller 10th is connected so that via the control terminal 48 of the microcontroller 10, the switch 40 is controllable.

In normal operation, no signal is present at the control connection 48, so that the switch 40 is closed, that is to say the transistor is turned on, and consequently the EEPROM 20 with its supply connection 24 and the home connection 28 is connected directly to the supply voltage UV.

For writing or reading data, the commands which are usual in the SPI interface 16, 18 are exchanged via the connections 14 of the microcontroller and the connections 22.

For example, a data transfer via the terminals SI and SO of the EEPROM 20, while a write command via the terminal CS of the EEPROM 20 takes place, the write command via the terminal CS by the microcontroller 10 is only given if already data on the port SI the EEPROM 20 are transmitted. At the conclusion of the transmission of the data, the command for writing the data into the EEPROM 20 then takes place via the connection CS.

However, if the function of the microcontroller 10 malfunctions, for example due to a voltage fluctuation or the like, during the transfer of data from the microcontroller 10 to the EEPROM 20, the data transfer is not completed or the signal to Writing the data in the EEPROM 20 is not given, so there is a system failure, since there is an undefined state at the terminals 22 of the EEPROM 20.

After such a malfunction of the microcontroller 10, a system reset routine 50 is usually started therein, which, however, likewise is not able to recognize the state in which the access to the EEPROM 20 has stopped.

For this reason, a reset step 52 is provided in the system reset routine 50 of the microcontroller 10, which results in an interrupt signal US being output at the control connection 48, for example by the signal "High", which in the range of, for example, 50 ms to 200 ms, the base 42 of the transistor 40 is controlled so that the switch 40 breaks the connection between the tap 32 and the power UV and thereby turns off the EEPROM 20 and turns on again after the interruption period, all undefined states are deleted at the terminals 22.

This makes it possible to delete all undefined states at the terminals 22 of the EEPROM and thus again to restart the communication between the microcontroller 10 and the EEPROM 20 with a clearly defined state.

The system reset routine 50 preferably executes the reset step 52 only after a defined waiting time from the start 54 of the system reset routine 50 in order, if appropriate, to give the EEPROM 20 the possibility of a to complete already started writing process, so that the waiting time at least equal to the write time of the EEPROM 20.

Further, in the system reset routine 50, after the start 54 and before the reset step 52, a reset step 56 for the SPI interface 16 follows and the initialization of the SPI interface 16 follows in an initialization step 58 following the reset step 52 so that at times of the initialization step For the SPI interface, the EEPROM 20 is fully functional again.

According to the invention, the interruption signal US has an interruption time duration which reliably leads to a reset of the EEPROM 20, in particular a time duration which is greater than the time constant of the capacitor 34 and parasitic capacitances, so that the voltage at the supply terminal 24 and the hold signal Terminal 28 drops to a level which results in erasing the data at all terminals 22 of EEPROM 20.

This can be in a malfunction of the microcontroller 10, for example, the following conditions dominate.

If, for example, in a first case, the malfunction of the function of the microcontroller 10 in a state in which data is still transmitted via the SPI interface 16, 18 of the terminals 14 of the microcontroller 10 to the terminals 22 of the EEPROM 20, so gives the microcontroller 10, for example, at the port CS not the command to write the data in the EEPROM 20, since the function of the microcontroller 10 is disturbed. If the system reset routine 50 were to be started, and cause a system reset of the microcontroller 10, there would be no longer defined states and signals at the terminals 22 of the EEPROM 20.

Incidentally, the EEPROM 20 would still wait for the completion of the data transfer and at the port CS for the signal for writing the data.

For this reason, the reset routine 52 is provided in the system reset routine 50 which, after a wait time after the start 54 of the system reset routine 50 at the output 48 outputs the interrupt signal US, which causes the switch 40, the center tap 32 and thus also the Ver supply terminal 24 and the hold terminal 28 from the supply voltage UV for the interruption period separates, so that a complete reset of the EEPROM 20 takes place while deleting the signals applied to the terminals 22.

Thus, all undefined states at the terminals 22 of the EEPROM 20 are deleted.

Thus, the system reset routine 50, which has already triggered a reset of the SPI interface 16, 18 and thus deleted in the SPI interface 16, 18 incompletely transmitted information after the reset 54 in the reset step 56 after the reset step 52, the initialization step 58 for the SPI -Interface and transmit after completion of the system reset routine 50 in a known manner via the SPI interface data. If, for example, in a second case, a fault of the microcontroller 10 occurs at a time when data has already been transmitted to the EEPROM 20 via the SPI interface 16, 18 and the write command has also been given via the connection CS of the EEPROM 20, then takes EEPROM 20 does not perceive any change in the signals at terminals 22 during the amount of time it takes to write the data in the memory of EEPROM 20.

A malfunction of the function of the microcontroller 10 during the time required for writing is thus irrelevant to the function and the writing process of the EEPROM 20.

However, it must be ensured that, even if the function of the microcontroller 10 is interrupted and thus the system reset routine 50 is started, no interruption of the power supply of the EEPROM 20 takes place during the time period for writing.

For this reason, in the system reset routine 50, the waiting time between the start 54 and the execution of the reset step 52 is at least as long as the time duration of the EEPROM 20 for writing, for example, greater than 20 ms, more preferably greater than 50 ms, so that after outputting the Write command on the part of the microcontroller 10, the EEPROM 20 in any case has the ability to write the received data into its memory before interrupting the connection between the supply voltage UV and the tap 32 and thus the supply terminal 24 and the hold terminal 28 of the EEPROM 20 , Thus, the EEPROM 20 has the ability, unmolested by the failure of the microcontroller 10 and the start of the system reset routine 50 in the microcontroller 10 to end the writing process for the data and only then, triggered by the reset step 52, the output of the interrupt signal 48, although is not necessarily required in this case, but due to the reset step 52 provided in the system reset routine 50, always takes place at the expiration of the system reset routine 50, at a time when the writing operation for the data in the EEPROM 20 is completed, and thus at a time, to which it can be reset by interrupting the connection between the power supply UV and the tap 32 by the switch 40 without impairing the function of the EEPROM 20.

Thus, the SPI interface can also be fully initialized again by the subsequent initialization step 58 and the communication between the microcontroller 10 and the EEPROM 20 can be recorded.

Claims

A control system comprising a microcontroller (10) and an EEPROM (20) for storing data for the microcontroller (10), characterized in that between a voltage supply (U _v ) and a supply connection (24) of the EEPROM (20 ) a switch (40) is provided, which is controllable by a control connection (48) of the microcontroller (10) and in the microcontroller (10) a system reset routine (50) is provided, which in one pass at the control terminal (48) Interrupt signal (US) which opens the switch (40) for an interruption period and resets the EEPROM (20).

2. Control system according to claim 1, characterized in that the system reset routine (50) triggers the interrupt signal (US) after a defined waiting time from the start (54) of the system reset routine (50).

3. Control system according to claim 2, characterized in that the defined waiting time corresponds to at least the writing period of the EEPROM (20).

4. Control system according to claim 2 or 3, characterized in that the defined waiting time is at least 10 ms.

5. Control system according to one of the preceding claims, characterized in that the microcontroller (10) with the EEPROM (20) exchanges data via an interface (16, 18).

6. A control system according to claim 5, characterized in that the system reset routine (50) before triggering the interrupt signal (US) causes a reset of the interface (16, 18).

7. Control system according to claim 5 or 6, characterized in that the interrupt signal (US) is terminated before an initialization of the interface (16, 18) by the system reset routine (50).