WO2008045824A3 - Monitor mode integrity verification - Google Patents
Monitor mode integrity verification Download PDFInfo
- Publication number
- WO2008045824A3 WO2008045824A3 PCT/US2007/080697 US2007080697W WO2008045824A3 WO 2008045824 A3 WO2008045824 A3 WO 2008045824A3 US 2007080697 W US2007080697 W US 2007080697W WO 2008045824 A3 WO2008045824 A3 WO 2008045824A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processing logic
- logic
- security level
- integrity verification
- monitor mode
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
- G06F21/53—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine
Abstract
A system (100) comprising a processing logic adapted to activate multiple security levels for the system and a storage coupled to the processing logic via a bus (11), the bus adapted to transfer information between the storage and the processing logic. The system also comprises a monitoring logic coupled to the processing logic and comprising a range of addresses associated with a predetermined security level of the system. The monitoring logic obtains an address associated with the information. If a current security level matches the predetermined security level and if the address does not correspond to the range of addresses, the monitoring logic restricts usage of the system.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06291584A EP1912149A1 (en) | 2006-10-09 | 2006-10-09 | Monitor mode integrity verification |
EP06291584.8 | 2006-10-09 | ||
US11/617,411 | 2006-12-28 | ||
US11/617,411 US20080086769A1 (en) | 2006-10-09 | 2006-12-28 | Monitor mode integrity verification |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008045824A2 WO2008045824A2 (en) | 2008-04-17 |
WO2008045824A3 true WO2008045824A3 (en) | 2008-08-14 |
Family
ID=39283545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/080697 WO2008045824A2 (en) | 2006-10-09 | 2007-10-08 | Monitor mode integrity verification |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2008045824A2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5684948A (en) * | 1995-09-01 | 1997-11-04 | National Semiconductor Corporation | Memory management circuit which provides simulated privilege levels |
US20030140245A1 (en) * | 2002-01-16 | 2003-07-24 | Franck Dahan | Secure mode for processors supporting MMU and interrupts |
US20060015749A1 (en) * | 2000-06-30 | 2006-01-19 | Millind Mittal | Method and apparatus for secure execution using a secure memory partition |
-
2007
- 2007-10-08 WO PCT/US2007/080697 patent/WO2008045824A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5684948A (en) * | 1995-09-01 | 1997-11-04 | National Semiconductor Corporation | Memory management circuit which provides simulated privilege levels |
US20060015749A1 (en) * | 2000-06-30 | 2006-01-19 | Millind Mittal | Method and apparatus for secure execution using a secure memory partition |
US20030140245A1 (en) * | 2002-01-16 | 2003-07-24 | Franck Dahan | Secure mode for processors supporting MMU and interrupts |
Also Published As
Publication number | Publication date |
---|---|
WO2008045824A2 (en) | 2008-04-17 |
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