WO2008045824A3 - Monitor mode integrity verification - Google Patents

Monitor mode integrity verification Download PDF

Info

Publication number
WO2008045824A3
WO2008045824A3 PCT/US2007/080697 US2007080697W WO2008045824A3 WO 2008045824 A3 WO2008045824 A3 WO 2008045824A3 US 2007080697 W US2007080697 W US 2007080697W WO 2008045824 A3 WO2008045824 A3 WO 2008045824A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing logic
logic
security level
integrity verification
monitor mode
Prior art date
Application number
PCT/US2007/080697
Other languages
French (fr)
Other versions
WO2008045824A2 (en
Inventor
Gregory R Conti
Original Assignee
Texas Instruments Inc
Gregory R Conti
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP06291584A external-priority patent/EP1912149A1/en
Application filed by Texas Instruments Inc, Gregory R Conti filed Critical Texas Instruments Inc
Publication of WO2008045824A2 publication Critical patent/WO2008045824A2/en
Publication of WO2008045824A3 publication Critical patent/WO2008045824A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G06F21/53Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine

Abstract

A system (100) comprising a processing logic adapted to activate multiple security levels for the system and a storage coupled to the processing logic via a bus (11), the bus adapted to transfer information between the storage and the processing logic. The system also comprises a monitoring logic coupled to the processing logic and comprising a range of addresses associated with a predetermined security level of the system. The monitoring logic obtains an address associated with the information. If a current security level matches the predetermined security level and if the address does not correspond to the range of addresses, the monitoring logic restricts usage of the system.
PCT/US2007/080697 2006-10-09 2007-10-08 Monitor mode integrity verification WO2008045824A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP06291584A EP1912149A1 (en) 2006-10-09 2006-10-09 Monitor mode integrity verification
EP06291584.8 2006-10-09
US11/617,411 2006-12-28
US11/617,411 US20080086769A1 (en) 2006-10-09 2006-12-28 Monitor mode integrity verification

Publications (2)

Publication Number Publication Date
WO2008045824A2 WO2008045824A2 (en) 2008-04-17
WO2008045824A3 true WO2008045824A3 (en) 2008-08-14

Family

ID=39283545

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/080697 WO2008045824A2 (en) 2006-10-09 2007-10-08 Monitor mode integrity verification

Country Status (1)

Country Link
WO (1) WO2008045824A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684948A (en) * 1995-09-01 1997-11-04 National Semiconductor Corporation Memory management circuit which provides simulated privilege levels
US20030140245A1 (en) * 2002-01-16 2003-07-24 Franck Dahan Secure mode for processors supporting MMU and interrupts
US20060015749A1 (en) * 2000-06-30 2006-01-19 Millind Mittal Method and apparatus for secure execution using a secure memory partition

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684948A (en) * 1995-09-01 1997-11-04 National Semiconductor Corporation Memory management circuit which provides simulated privilege levels
US20060015749A1 (en) * 2000-06-30 2006-01-19 Millind Mittal Method and apparatus for secure execution using a secure memory partition
US20030140245A1 (en) * 2002-01-16 2003-07-24 Franck Dahan Secure mode for processors supporting MMU and interrupts

Also Published As

Publication number Publication date
WO2008045824A2 (en) 2008-04-17

Similar Documents

Publication Publication Date Title
WO2006130763A3 (en) Partial page scheme for memory technologies
WO2008021101A3 (en) Fuel cartridge authentication
MXPA05007150A (en) Policy engine and methods and systems for protecting data.
WO2008042784A9 (en) Comparing taxonomies
WO2008058152A3 (en) Multiple stakeholder secure memory partitioning and access control
WO2007026263A3 (en) Routing configuration validation apparatus and methods
WO2008024762A3 (en) Probabilistic technique for consistency checking cache entries
TW200632651A (en) A virtual address cache and method for sharing data stored in a virtual address cache
WO2007009009A3 (en) Systems and methods for identifying sources of malware
TWI350968B (en) Mass storage memory system and method for accessing the same
WO2007035714A3 (en) Method and system for preventing unsecure memory accesses
WO2011005763A3 (en) Data transfer management
WO2008005126A3 (en) Method and system for providing signatures for machines
WO2009154787A3 (en) Parking locator system including vehicle and user identifiers
JP2012104049A5 (en)
WO2006069158A3 (en) Self-adaptive multimodal biometric authentication system and method
EP1479008A4 (en) Methods and systems for resolving addressing conflicts based on tunnel information
WO2008004149A3 (en) Flash memory device having a flash cache portion and a method for using the same
WO2008008623A3 (en) Systems and techniques for datapath security in a system-on-a-chip device
WO2007124307A3 (en) Virtually-tagged instruction cache with physically-tagged behavior
FI20060637A0 (en) Access to a network using a portable memory device
WO2008155188A3 (en) Firewall control using remote system information
WO2008129765A1 (en) Monitoring unit control system
WO2008155805A1 (en) Cache memory device, arithmetic processing unit, and its control method
WO2010006134A3 (en) Distributed data storage and access systems

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07843970

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07843970

Country of ref document: EP

Kind code of ref document: A2