WO2007008961A3 - Method and apparatus for parameter adjustment, testing, and configuration - Google Patents

Method and apparatus for parameter adjustment, testing, and configuration Download PDF

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Publication number
WO2007008961A3
WO2007008961A3 PCT/US2006/027014 US2006027014W WO2007008961A3 WO 2007008961 A3 WO2007008961 A3 WO 2007008961A3 US 2006027014 W US2006027014 W US 2006027014W WO 2007008961 A3 WO2007008961 A3 WO 2007008961A3
Authority
WO
WIPO (PCT)
Prior art keywords
testing
configuration
parameter adjustment
components
monitoring
Prior art date
Application number
PCT/US2006/027014
Other languages
French (fr)
Other versions
WO2007008961A2 (en
Inventor
Stanley Hronik
Original Assignee
Integrated Device Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Device Tech filed Critical Integrated Device Tech
Priority to CN2006800334877A priority Critical patent/CN101553737B/en
Priority to EP06786989A priority patent/EP1913409A4/en
Publication of WO2007008961A2 publication Critical patent/WO2007008961A2/en
Publication of WO2007008961A3 publication Critical patent/WO2007008961A3/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31718Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3172Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

A method and apparatus for parameter adjustment, testing and configuration pertaining to the testing of devices is disclosed. The method and apparatus allows tuning the interaction of components in a system for best performance, modifying the operation of components in a system, and monitoring changes in parameters which may predict degradation or failure. The method and apparatus may operate at the device, interface or system level. Through serial data chains, systems may be made to perform under selected or imposed operating conditions to allow configuration, testing, measuring or monitoring.
PCT/US2006/027014 2005-07-12 2006-07-12 Method and apparatus for parameter adjustment, testing, and configuration WO2007008961A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800334877A CN101553737B (en) 2005-07-12 2006-07-12 Method and apparatus for parameter adjustment, testing, and configuration
EP06786989A EP1913409A4 (en) 2005-07-12 2006-07-12 Method and apparatus for parameter adjustment, testing, and configuration

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US69832005P 2005-07-12 2005-07-12
US60/698,320 2005-07-12
US11/395,602 US20070016835A1 (en) 2005-07-12 2006-03-31 Method and apparatus for parameter adjustment, testing, and configuration
US11/395,602 2006-03-31

Publications (2)

Publication Number Publication Date
WO2007008961A2 WO2007008961A2 (en) 2007-01-18
WO2007008961A3 true WO2007008961A3 (en) 2009-04-16

Family

ID=37637925

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/027014 WO2007008961A2 (en) 2005-07-12 2006-07-12 Method and apparatus for parameter adjustment, testing, and configuration

Country Status (4)

Country Link
US (2) US20070016835A1 (en)
EP (1) EP1913409A4 (en)
CN (1) CN101553737B (en)
WO (1) WO2007008961A2 (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7647467B1 (en) * 2006-05-25 2010-01-12 Nvidia Corporation Tuning DRAM I/O parameters on the fly
US8186891B2 (en) * 2006-08-04 2012-05-29 Emcore Corporation Embedded parametric monitoring of optoelectronic modules
US20080031576A1 (en) * 2006-08-04 2008-02-07 Hudgins Clay E Embedded parametric monitoring of optoelectronic modules
US7949907B2 (en) * 2006-10-03 2011-05-24 Wipro Limited Method and device for data communication
US7671602B1 (en) * 2007-01-24 2010-03-02 Integrated Device Technology, Inc. Method and apparatus for cross-point detection
US20090140774A1 (en) * 2007-12-03 2009-06-04 Jeff Kotowski System and method for communicating data among chained circuits
US7760008B2 (en) * 2008-10-28 2010-07-20 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Digital trimming in a microelectronic device
US9461930B2 (en) 2009-04-27 2016-10-04 Intel Corporation Modifying data streams without reordering in a multi-thread, multi-flow network processor
US8683221B2 (en) * 2010-05-18 2014-03-25 Lsi Corporation Configurable memory encryption with constant pipeline delay in a multi-core processor
US8405402B2 (en) * 2009-05-20 2013-03-26 Apple Inc. Systems and methods for adjusting signaling properties based on cable attributes
US8566495B2 (en) * 2009-11-06 2013-10-22 Qualcomm Incorporated Systems, methods and apparatus for data communication
US8578222B2 (en) * 2011-02-17 2013-11-05 Qualcomm Incorporated SerDes power throttling as a function of detected error rate
US8417114B1 (en) * 2011-11-18 2013-04-09 Level 3 Communications, Llc Apparatus, system and method for network monitoring
US11012153B2 (en) * 2011-11-18 2021-05-18 Level 3 Communications, Llc Optical test device and systems
US9092573B2 (en) * 2012-07-06 2015-07-28 Nvidia Corporation System, method, and computer program product for testing device parameters
US8704566B2 (en) * 2012-09-10 2014-04-22 International Business Machines Corporation Hybrid phase-locked loop architectures
US20140229644A1 (en) * 2013-02-12 2014-08-14 Haran Thanigasalam Method, apparatus, system for including interrupt functionality in sensor interconnects
CN103631723B (en) * 2013-11-29 2017-02-01 中国电子科技集团公司第四十七研究所 adjusting circuit and circuit adjusting method
US20150276839A1 (en) * 2014-04-01 2015-10-01 Qualcomm Incorporated Worst case jitter prediction method using step response
US9407574B2 (en) * 2014-04-17 2016-08-02 Adva Optical Networking Se Using SerDes loopbacks for low latency functional modes with full monitoring capability
US9281810B2 (en) 2014-05-13 2016-03-08 Qualcomm Incorporated Current mode logic circuit with multiple frequency modes
US9536031B2 (en) * 2014-07-14 2017-01-03 Mediatek Inc. Replacement method for scan cell of integrated circuit, skewable scan cell and integrated circuit
US10097313B2 (en) * 2016-08-02 2018-10-09 Avago Technologies General Ip (Singapore) Pte. Ltd. Backchannel protocol for link training and adaptation
US10169140B2 (en) 2016-10-18 2019-01-01 International Business Machines Corporation Loading a phase-locked loop (PLL) configuration using flash memory
US10419005B2 (en) * 2016-12-14 2019-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Phase-locked-loop architecture
CN109239514B (en) * 2018-08-03 2021-02-09 重庆川仪自动化股份有限公司 Short circuit and open circuit detection circuit of liquid level meter sensor
CN111489050A (en) * 2020-03-04 2020-08-04 广州明珞汽车装备有限公司 Maintenance task allocation method, system, device and storage medium
CN113049943A (en) * 2021-03-09 2021-06-29 普冉半导体(上海)股份有限公司 Test method for adjusting chip parameters
CN114594342B (en) * 2022-03-21 2023-03-28 国网安徽省电力有限公司电力科学研究院 Power distribution network ground fault judgment input waveform consistency processing method
CN115932373B (en) * 2022-11-22 2023-10-20 南方电网数字电网研究院有限公司 Voltage measuring probe, single-phase line and three-phase line voltage measuring method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US6393081B1 (en) * 1998-11-25 2002-05-21 Texas Instruments Incorporated Plural circuit selection using role reversing control inputs

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646299A (en) 1983-08-01 1987-02-24 Fairchild Semiconductor Corporation Method and apparatus for applying and monitoring programmed test signals during automated testing of electronic circuits
US4868552A (en) 1986-08-25 1989-09-19 Rohde & Schwartz-Polarad Apparatus and method for monochrome/multicolor display of superimposed images
US4868522A (en) * 1988-12-13 1989-09-19 Gazelle Microcircuits, Inc. Clock signal distribution device
US5319680A (en) * 1991-09-03 1994-06-07 The Whitaker Corporation Phase locked loop synchronization system for use in data communications
US5230013A (en) * 1992-04-06 1993-07-20 Motorola, Inc. PLL-based precision phase shifting at CMOS levels
US5487093A (en) * 1994-05-26 1996-01-23 Texas Instruments Incorporated Autoranging digital analog phase locked loop
US5696468A (en) * 1996-02-29 1997-12-09 Qualcomm Incorporated Method and apparatus for autocalibrating the center frequency of a voltage controlled oscillator of a phase locked loop
US5757240A (en) * 1996-07-01 1998-05-26 International Business Machines Corporation Low gain voltage-controlled oscillator
US5918194A (en) * 1996-08-01 1999-06-29 Keithley Instruments, Inc. Integrated modular measurement system having configurable firmware architecture and modular mechanical parts
US5793778A (en) * 1997-04-11 1998-08-11 National Semiconductor Corporation Method and apparatus for testing analog and digital circuitry within a larger circuit
US6043717A (en) * 1998-09-22 2000-03-28 Intel Corporation Signal synchronization and frequency synthesis system configurable as PLL or DLL
AU1330200A (en) * 1998-10-30 2000-05-22 Broadcom Corporation Internet gigabit ethernet transmitter architecture
JP2000174616A (en) * 1998-12-04 2000-06-23 Fujitsu Ltd Semiconductor integrated circuit
JP2000357951A (en) * 1999-06-15 2000-12-26 Mitsubishi Electric Corp Delay circuit, clock generation circuit and phase locked loop
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
KR100350481B1 (en) * 1999-12-30 2002-08-28 삼성전자 주식회사 apparatus and method for implementing hand-off from asynchronous mobile communication system to synchronous mobile communication system
US6823031B1 (en) * 2000-01-20 2004-11-23 Wavtrace, Inc. Automated frequency compensation for remote synchronization
US6314034B1 (en) * 2000-04-14 2001-11-06 Advantest Corp. Application specific event based semiconductor memory test system
US6993095B2 (en) * 2001-03-15 2006-01-31 Texas Instruments Incorporated Phase-locked loop initialization via curve-fitting
US6424229B1 (en) * 2001-06-04 2002-07-23 Ericsson Inc. Tunable voltage controlled oscillator circuit having aided acquisition and methods for operating the same
US6856203B2 (en) * 2002-01-31 2005-02-15 Stmicroelectronics Pvt. Ltd. Phase lock loop with controllable lock time
US7123046B2 (en) 2002-02-13 2006-10-17 Micron Technology, Inc Apparatus for adaptively adjusting a data receiver
US6825785B1 (en) * 2002-02-28 2004-11-30 Silicon Laboratories, Inc. Digital expander apparatus and method for generating multiple analog control signals particularly useful for controlling a sub-varactor array of a voltage controlled oscillator
JP2003318732A (en) * 2002-04-26 2003-11-07 Hitachi Ltd Semiconductor integrated circuit for communication, and radio communication system
US6812691B2 (en) * 2002-07-12 2004-11-02 Formfactor, Inc. Compensation for test signal degradation due to DUT fault
US20050134336A1 (en) * 2002-10-31 2005-06-23 Goldblatt Jeremy M. Adjustable-bias VCO
JP2004173177A (en) * 2002-11-22 2004-06-17 Nec Corp Pll circuit
GB0301956D0 (en) * 2003-01-28 2003-02-26 Analog Devices Inc Scan controller and integrated circuit including such a controller
US7233183B1 (en) * 2003-02-27 2007-06-19 Cypress Semiconductor Corporation Wide frequency range DLL with dynamically determined VCDL/VCO operational states
FR2859329A1 (en) * 2003-09-02 2005-03-04 St Microelectronics Sa Method for processing frequency shift of carrier frequency, involves correcting carrier frequency by phase lock loop initiated by frequency shift estimation value, with frequency locking range of loop lower than that of frequency estimator
US7424348B2 (en) * 2004-06-28 2008-09-09 Micrel, Incorporated System and method for monitoring serially-connected devices
US7148758B1 (en) * 2004-08-13 2006-12-12 Xilinx, Inc. Integrated circuit with digitally controlled phase-locked loop
US6985096B1 (en) * 2004-08-17 2006-01-10 Xilinx, Inc. Bimodal serial to parallel converter with bitslip controller
US7681063B2 (en) * 2005-03-30 2010-03-16 Infineon Technologies Ag Clock data recovery circuit with circuit loop disablement
US7265634B2 (en) * 2005-06-17 2007-09-04 Kabushiki Kaisha Toshiba System and method for phase-locked loop initialization
US7388442B2 (en) * 2005-06-18 2008-06-17 Agere Systems Inc. Digitally controlled oscillator for reduced power over process variations

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation
US6393081B1 (en) * 1998-11-25 2002-05-21 Texas Instruments Incorporated Plural circuit selection using role reversing control inputs

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1913409A4 *

Also Published As

Publication number Publication date
EP1913409A2 (en) 2008-04-23
US8265219B1 (en) 2012-09-11
WO2007008961A2 (en) 2007-01-18
US20070016835A1 (en) 2007-01-18
CN101553737A (en) 2009-10-07
EP1913409A4 (en) 2010-11-17
CN101553737B (en) 2012-05-23

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