WO2006050534A1 - Timer offsetting mechanism in a virtual machine environment - Google Patents
Timer offsetting mechanism in a virtual machine environment Download PDFInfo
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- WO2006050534A1 WO2006050534A1 PCT/US2005/040450 US2005040450W WO2006050534A1 WO 2006050534 A1 WO2006050534 A1 WO 2006050534A1 US 2005040450 W US2005040450 W US 2005040450W WO 2006050534 A1 WO2006050534 A1 WO 2006050534A1
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- timer
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- offset
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
Definitions
- Embodiments of the invention relate generally to virtual machines, and more specifically to a timer offsetting mechanism in a virtual machine environment.
- Timers are typically used by operating systems and application software to schedule activities.
- an operating system kernel may use a timer to allow a plurality of user-level applications to time-share the resources of the system (e.g., the central processing unit (CPU)).
- An example of a timer used on a personal computer (PC) platform is the 8254 Programmable Interval Timer. This timer may be configured to issue interrupts after a specified interval or periodically.
- TSC timestamp counter
- ISA instruction set architecture
- Intel ® Pentium ® 4 referred to herein as the IA-32 ISA
- the TSC is a 64-bit counter that is set to 0 following the hardware reset of the processor, and then incremented every processor clock cycle, even when the processor is halted by the HLT instruction.
- the TSC cannot be used to generate interrupts. It is a time reference only, useful to measure time intervals.
- the IA-32 ISA provides an instruction (RDTSC) to read the value of the TSC and an instruction (WRMSR) to write the TSC.
- RTSC instruction
- WRMSR instruction
- the TSC is used to properly synchronize processors and schedule processes appropriately.
- the values of the TSC on all processors are synchronized and most operating systems assume that the TSC then count at the same rate. If the TSC values drift between processors (e.g., if one processor counts at a different rate that the others), scheduling of processes by the operating system may be confused.
- Figure 1 illustrates one embodiment of a virtual-machine environment, in which the present invention may operate
- Figure 2 is a flow diagram of one embodiment of a process for controlling access of VMs to a timer
- Figure 3 is a flow diagram of one embodiment of a process for configuring fields associated timer offsetting; and [0009] Figures 4 and 5 are flow diagrams of two alternative embodiments of a process for calculating a timer offset value for a VM. Description of Embodiments
- the present invention may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process according to the present invention.
- processes of the present invention might be performed by specific hardware components that contain hardwired logic for performing the processes, or by any combination of programmed computer components and custom hardware components.
- a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD- ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, a transmission over the Internet, electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.) or the like.
- a machine e.g., a computer
- ROMs Read-Only Memory
- RAM Random Access Memory
- EPROM Erasable Programmable Read-Only Memory
- EEPROM Electrically Erasable Programmable Read-Only Memory
- a design may go through various stages, from creation to simulation to fabrication.
- Data representing a design may represent the design in a number of manners.
- the hardware may be represented using a hardware description language or another functional description language.
- a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.
- most designs, at some stage reach a level of data representing the physical placement of various devices in the hardware model.
- data representing a hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit.
- the data may be stored in any form of a machine- readable medium.
- FIG. 1 illustrates one embodiment of a virtual-machine environment 100, in which the present invention may operate.
- bare platform hardware 116 comprises a computing platform, which may be capable, for example, of executing a standard operating system (OS) or a virtual-machine monitor (VMM), such as a VMM 112.
- OS operating system
- VMM virtual-machine monitor
- the VMM 112 though typically implemented in software, may emulate and export a bare machine interface to higher level software.
- higher level software may comprise a standard or real-time OS, may be a highly stripped down operating environment with limited operating system functionality, may not include traditional OS facilities, etc.
- the VMM 112 may be run within, or on top of, another VMM.
- VMMs may be implemented, for example, in hardware, software, firmware or by a combination of various techniques.
- the platform hardware 116 can be of a personal computer (PC), mainframe, handheld device, portable computer, set-top box, or any other computing system.
- the platform hardware 116 includes a processor 118 and memory 120.
- Processor 118 can be any type of processor capable of executing software, such as a microprocessor, digital signal processor, microcontroller, or the like.
- the processor 118 may include microcode, programmable logic or hardcoded logic for performing the execution of method embodiments of the present invention. Although Figure 1 shows only one such processor 118, there may be one or more processors in the system.
- Memory 120 can be a hard disk, a floppy disk, random access memory (RAM), read only memory (ROM), flash memory, any combination of the above devices, or any other type of machine medium readable by processor 118.
- Memory 120 may store instructions and/or data for performing the execution of method embodiments of the present invention.
- the VMM 112 presents to other software (i.e., "guest” software) the abstraction of one or more virtual machines (VMs), which may provide the same or different abstractions to the various guests.
- Figure 1 shows two VMs, 102 and 114.
- the guest software running on each VM may include a guest OS such as a guest OS 104 or 106 and various guest software applications 108 and 110.
- Each of the guest OSs 104 and 106 expects to access physical resources (e.g., processor registers, memory and I/O devices) within the VMs 102 and 114 on which the guest OS 104 or 106 is running and to perform other functions.
- physical resources e.g., processor registers, memory and I/O devices
- the guest OS 104 and 106 expects to have access to all registers, caches, structures, I/O devices, memory and the like, according to the architecture of the processor and platform presented in the VMs 102 and 114.
- the resources that can be accessed by the guest software may either be classified as "privileged" or "non-privileged.”
- the VMM 112 facilitates functionality desired by guest software while retaining ultimate control over these privileged resources.
- Non-privileged resources do not need to be controlled by the VMM 112 and can be accessed by guest software.
- each guest OS expects to handle various fault events such as exceptions (e.g., page faults, general protection faults, etc.), interrupts (e.g., hardware interrupts, software interrupts), and platform events (e.g., initialization (INIT) and system management interrupts (SMIs)).
- exceptions e.g., page faults, general protection faults, etc.
- interrupts e.g., hardware interrupts, software interrupts
- platform events e.g., initialization (INIT) and system management interrupts (SMIs)
- IIT initialization
- SMIs system management interrupts
- control may be transferred to the VMM 112.
- the transfer of control from guest software to the VMM 112 is referred to herein as a VM exit.
- the VMM 112 may return control to guest software.
- the transfer of control from the VMM 112 to guest software is referred to as a VM entry.
- the processor 118 controls the operation of the VMs 102 and 114 in accordance with data stored in a virtual machine control structure (VMCS) 124.
- the VMCS 124 is a structure that may contain state of guest software, state of the VMM 112, execution control information indicating how the VMM 112 wishes to control operation of guest software, information controlling transitions between the VMM 112 and a VM, etc.
- the processor 118 reads information from the VMCS 124 to determine the execution environment of the VM and to constrain its behavior.
- the VMCS is stored in memory 120. In some embodiments, multiple VMCS structures are used to support multiple VMs.
- the VMM 112 may need to use a timer to schedule resources, provide quality of service, assure security, and perform other functions. For example, in the instruction set architecture (ISA) of the Intel ® Pentium ® 4 (referred to herein as the IA-32 ISA), the VMM 112 may use the timestamp counter (TSC) to perform these functions. Each of the VMs 102 and 114 may also need to use the timer to calibrate timing loops and do performance optimization. Because the VMs 102 and 114 have no knowledge of each other or the VMM 112, the timer's values provided to the VM 102 or 114 may need to be adjusted to present the illusion that the guest OS 104 or 106 is running on a dedicated hardware platform, not a virtual platform.
- TSC timestamp counter
- a timer offsetting mechanism is provided to properly virtualize the timer and thus preserve the illusion for the guest OSes 104 and 106.
- the timer offsetting mechanism includes a timer offset configuration module 126 and timer access logic 122.
- the timer offset configuration module 126 is responsible for providing values for fields associated with timer offsetting prior to requesting a transition of control to the VM 102 or 114. In one embodiment, these values may include an offset value specifying an offset to be used by the processor 118 when providing timer values to the VM 102 or 114 and a timer offsetting indicator specifying whether timer offsetting is enabled for the VM 102 or 114.
- the timer offset value is a signed value, allowing the VMM 112 to present a timer value to guest software that is less than or greater than the actual hardware timer value.
- the timer offset value is added to the timer value before returning the value to the VM 102 or 114.
- the fields associated with timer offsetting also include a timer access control indicator specifying whether VM requests to access the timer are associated with a transition of control to the VMM (e.g., whether VM requests to access the timer should cause VM exits).
- the offset value for the VM 102 or 114 accounts for the aggregation of time intervals during which this VM was not running due to the execution of the VMM 112 and the other VM. For example, suppose that, when the timer's value is 1000 ticks, the VM 102 expects the value of the timer to be 1000. Then, at 1500 ticks, the VM 102 may be interrupted by a VM exit, following by the execution of the VMM 112 for 100 ticks (timer value of 1600 ticks), after which the VMM 112 may request to enter the VM 114.
- the VM 114 may then execute for 600 ticks (timer value of 2200 ticks) until a VM exit, resulting in the execution of the VMM 112 for 200 ticks (timer value 2400), which may then request to re-enter the VM 102.
- timer value 2400 timer value 2400
- the VM 102 expects the timer to have the value of 1500 ticks. Instead, the actual timer value at this time is 2400 ticks.
- the offset value provided by the VMM 112 for the VM 102 will be 900 ticks, which is the aggregation of time intervals during which the VM 112 was not running due to the execution of the VM 114 and the VMM 112.
- the VMM 112 would store the offset value of 900 to the timer offset field so that when the VM 102 attempts to read the timer, the value provided to the VM 102 will be computed by reducing the current timer value by 900.
- the offset value may also be calculated by computing the difference between the actual timer value and the timer value expected by the VM 102.
- the value provided to the VM 102 when it attempts to read the timer is computed by adding the current timer value to the offset value configured by the VMM 112.
- the offset value stored by the VMM is a negative number. In the example described above, the value stored is -900.
- the offset value is determined by the VMM 112.
- the offset value is determined by the processor 118, and the fields and controls associated with timer offsetting may include a timer offsetting indicator, an adjust offset indicator, a guest timer field, a save timer indicator, and a timer offset field.
- the three indicator values may be combined in a variety of ways.
- the adjust offset indicator and the save timer indicator may be the same control (i.e., enabling the adjustment of the timer offset implicitly enables the saving of the timer), as will be described in more detail below. In some embodiments, some of the above indicators may not be present.
- the timer offsetting indicator may not be present, and timer offsetting is assumed to be always enabled, as will be discussed in greater detail below.
- the fields and controls associated with timer offsetting are stored in the VMCS 124.
- the fields and controls associated with timer offsetting may reside in the processor 118, a combination of the memory 120 and the processor 118, or in any other storage location or locations.
- separate fields and controls associated with timer offsetting are maintained for each of the VMs 102 and 114.
- the same fields and controls associated with timer offsetting are maintained for both VMs 102 and 144 and are updated by the VMM 112 before each VM entry.
- each of the multiple logical processors is associated with separate fields and controls associated with timer offsetting, and the VMM 112 configures the fields and controls associated with timer offsetting for each of the multiple logical processors.
- the processor 118 includes timer access logic 122 that is responsible for virtualizing accesses of the VM 102 and 114 to the timer based on the timer offsetting values. In particular, if the timer access logic 122 determines that timer offsetting is enabled, it provides an adjusted timer value to the VM 102 or 114. In one embodiment, the timer access logic 122 determines if timer offsetting is enabled by examining a timer offsetting indicator value.
- the timer access logic 122 when the timer access logic 122 receives a request for a current value of the timer from the VM 102 or 114, it reads the current value of the timer, adds the offset value to the current value of the timer, and returns the resulting value to the VM 102 or 114, thus presenting the VM 102 or 114 with the illusion that it is running on a dedicated hardware platform.
- the offset value is a signed value.
- the offset values may be determined for the VM 102 and 114 by the VMM 112 (e.g., by the timer offset configuration module 126).
- the offset values are determined by the processor 118 (e.g., by the timer access logic 122).
- One embodiment of a process for determining an offset value by the processor 118 will be discussed in more detail below in conjunction with Figure 5.
- FIG. 2 is a flow diagram of one embodiment of a process 200 for controlling access of VMs to a timer.
- the process may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as that run on a general purpose computer system or a dedicated machine), or a combination of both.
- process 200 is performed by timer access logic 122 of Figure 1.
- process 200 begins with processing logic receiving a request to transition control to a VM from a VMM (i.e., the request for VM entry) (processing block 202).
- the VM entry request is received via a VM entry instruction executed by the VMM.
- processing logic determines whether timer offsetting is enabled (processing block 204). In one embodiment, processing logic makes this determination as part of the transition to the VM (e.g., when checking and loading VM state and execution control information stored in the VMCS). In one embodiment, the determination is based on the current value of a timer offsetting indicator stored in the VMCS for the VM being entered.
- processing logic uses a timer offset value when responding to the requests of the VM for a current timer value.
- the timer offset value is determined by the VMM prior to issuing the request to transition control to this VM.
- the offset value is automatically determined by the processor when transitioning control to this VM.
- One embodiment of a process for determining the offset value by the processor will be discussed in more detail below in conjunction with Figure
- processing logic if timer offsetting is enabled, processing logic loads an offset register with the timer offset value stored in the VMCS (processing block 206). Alternatively, if timer offsetting is disabled, processing logic loads the offset register with 0 (processing block 206). Next, processing logic begins the execution in the VM (processing block 210).
- processing logic may receive the VM's requests for a current value of the timer.
- the VM may issue a request for a current value of the TSC by executing the RDMSR instruction or a RDTSC instruction to read the TSC.
- processing logic determines whether the VM requests a current value of the timer. If so, then in one embodiment, processing logic determines whether this request is associated with a transition of control to the VMM (processing box 214).
- a timer access control indicator may be set to an "exit" value to cause a VM exit on each request of the VM to access the timer.
- the timer access control indicator is a single bit, which if set to 1 indicates that requests of a VM to access the timer cause VM exits. In one embodiment, this indicator may be stored in the VMCS. If the request is not associated with a transition of control to the VMM, processing logic proceeds to processing block 216.
- processing logic transitions control to the VMM, indicating to the VMM that the VM exit was caused by an attempt to access the timer (processing block 220).
- processing logic loads the offset register with 0 (processing block 218) to allow the VMM to obtain the actual value of the timer.
- a timer access control indicator is not used, and processing logic does not check for a transition of control to the VMM in response to VM requests for a current value of the timer. Instead, processing logic skips processing block 214 and proceeds directly to processing block 216.
- processing logic reads the current value of the timer, adds the offset value to the current value of the timer, and returns the result to the VM.
- the timer offset value is a signed value that is combined with the content of the timer using signed addition.
- processing logic if processing logic detects an event associated with a VM exit (processing box 222), processing logic loads the offset register with 0 (processing block 218) and transitions control to the VMM, indicating the cause of the VM exit detected in processing block 222 (processing block 220). If processing logic does not detect any events associated with a VM exit, processing logic returns to processing box 212.
- FIG. 3 is a flow diagram of one embodiment of a process 300 for configuring fields associated with timer offsetting.
- the process may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as that run on a general purpose computer system or a dedicated machine), or a combination of both.
- process 300 is performed by a timer offset configuration module 126 of Figure 1.
- process 300 begins with processing logic deciding that a transition of control to a VM is needed. Prior to issuing a request to transition control to the VM, processing logic determines a timer offset value for the VM
- processing block 302 and stores the timer offset value in the VMCS (processing block 304).
- the timer offset value is the aggregation of time intervals during which the VM being entered was not running due to the execution of the VMM and the other VMs.
- processing logic sets a timer offset indicator to an enabling value (processing block 306) and issues a request to transition control to the VM (e.g., a VM entry request) (processing logic 308).
- FIG. 3 is a flow diagram of one embodiment of a process 400 for calculating a timer offset value for a VM (as referenced in processing block 302 of Figure 3 for example).
- process 400 may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as that run on a general purpose computer system or a dedicated machine), or a combination of both.
- processing logic may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as that run on a general purpose computer system or a dedicated machine), or a combination of both.
- process 400 is performed by a timer offset configuration module 126 of Figure 1.
- process 400 begins with processing logic calculating the time spent in this VM since the last VM entry (processing block 402). In one embodiment, this time is calculated by determining a VM-entry time (i.e., the timer value just prior to issuing a request to enter the VM) and a VM-exit time (e.g., the timer value at the time of receiving control returned from the VM), and subtracting the VM-entry time from the VM-exit time.
- a VM-entry time i.e., the timer value just prior to issuing a request to enter the VM
- a VM-exit time e.g., the timer value at the time of receiving control returned from the VM
- processing logic calculates the cumulative time spent in the VM by adding the time spent in the VM during the last entry to the previously calculated cumulative time. In one embodiment, processing logic calculates the cumulative time spent in the VM when receiving control returned from the VM. Alternatively, processing logic calculates the cumulative time spent in the VM when issuing a request to return control to this VM.
- processing logic When processing logic decides to return control to the VM, it reads the current value of the timer (processing block 406), and calculates the timer offset value as a difference between the cumulative time spent in the VM and the current value of the timer (processing block 408).
- the timer offset value is a signed value.
- FIG. 5 is a flow diagram of an alternative embodiment of a process for calculating a timer offset value for a VM.
- the process may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as that run on a general purpose computer system or a dedicated machine), or a combination of both.
- process 500 is performed by timer offset logic 122 of Figure 1.
- process 500 begins with processing logic detecting an event associated with a transition of control from VMl to the VMM (processing block 502).
- processing logic determines whether a save timer indicator is enabled.
- the save timer indicator is configured by the VMM and stored in the VMCS.
- processing logic saves a current timer value as a VMl timer value to a guest timer field (processing block 506) and proceeds to processing block 508.
- the guest timer field is stored in the VMCS.
- processing logic If the save timer indicator is disabled, processing logic skips processing block 506 and proceeds directly to processing block 508. [0057] At processing block 508, processing logic transitions control to the VMM. [0058] Subsequently, at processing block 510, processing logic receives a request to return control to VMl. In response, processing logic determines whether an adjust offset indicator is enabled (processing block 512). In one embodiment, the adjust offset indicator is configured by the VMM and stored in the VMCS. In another embodiment, the save timer indicator and the adjust offset indicator are represented by the same indicator which is checked both at processing blocks 504 and 512. In another embodiment, a timer offsetting indicator may be evaluated to determine if timer offsetting should be used.
- the timer offsetting indicator is configured by the VMM and stored in the VMCS.
- processing logic reads the current timer value (processing block 514), and determines the difference between the current timer value and the VMl timer value saved at processing block 506 by subtracting the saved VMl timer value from the current timer value (processing block 516). Further, processing logic calculates the adjusted timer offset value by subtracting this difference from the timer offset value in the timer offset field (processing block 518). In one embodiment, this adjusted timer offset value is stored to the timer offset field. Next, processing logic transitions control to VMl (processing block 520).
- processing logic skips processing blocks 514 through 518 and proceeds directly to processing block 520.
- processing logic retrieves the value of timer offset field for use as the adjusted timer offset value and then proceeds to processing block 520.
- a virtual guest timer value is calculated (by computing the sum of the current timer offset value and the current value of the timer) and stored to a virtual guest timer field.
- the virtual guest timer field is stored in the VMCS.
- the offset value is computed by subtracting the timer value at the time of the VM entry from the virtual guest timer value. While the VM executes, attempts to read the timer will return the current value of the timer adjusted by the offset value.
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JP2007539377A JP4584315B2 (en) | 2004-10-29 | 2005-10-31 | Timer offset mechanism in virtual machine environment |
DE112005002347T DE112005002347T5 (en) | 2004-10-29 | 2005-10-31 | Timer offset mechanism in the environment of a virtual machine |
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US10/976,970 US8146078B2 (en) | 2004-10-29 | 2004-10-29 | Timer offsetting mechanism in a virtual machine environment |
US10/976,970 | 2004-10-29 |
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- 2005-10-31 WO PCT/US2005/040450 patent/WO2006050534A1/en active Application Filing
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Also Published As
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DE112005002347T5 (en) | 2007-09-20 |
CN101044458A (en) | 2007-09-26 |
CN100481010C (en) | 2009-04-22 |
JP2008518367A (en) | 2008-05-29 |
US20060130059A1 (en) | 2006-06-15 |
US8146078B2 (en) | 2012-03-27 |
JP4584315B2 (en) | 2010-11-17 |
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