WO2004003711A2 - Sleep attack protection - Google Patents

Sleep attack protection Download PDF

Info

Publication number
WO2004003711A2
WO2004003711A2 PCT/US2003/019597 US0319597W WO2004003711A2 WO 2004003711 A2 WO2004003711 A2 WO 2004003711A2 US 0319597 W US0319597 W US 0319597W WO 2004003711 A2 WO2004003711 A2 WO 2004003711A2
Authority
WO
WIPO (PCT)
Prior art keywords
sleep
response
memory
secrets
monitor
Prior art date
Application number
PCT/US2003/019597
Other languages
French (fr)
Other versions
WO2004003711A3 (en
Inventor
David Grawcock
David Poisner
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to KR1020047020945A priority Critical patent/KR100692348B1/en
Priority to JP2004517729A priority patent/JP4660188B2/en
Priority to AU2003247595A priority patent/AU2003247595A1/en
Priority to EP03761974A priority patent/EP1516239A2/en
Publication of WO2004003711A2 publication Critical patent/WO2004003711A2/en
Publication of WO2004003711A3 publication Critical patent/WO2004003711A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories

Definitions

  • SE security enhanced
  • An SE environment may employ various techniques to prevent different kinds of attacks or unauthorized access to protected data or secrets (e.g. social security number, account numbers, bank balances, lo passwords, authorization keys, etc.).
  • One type of attack that an SE environment may attempt to prevent is a sleep attack.
  • many computing devices support a suspend-to-memory sleep state such as, for example, the S3 sleep state described in the Advanced Configuration and Power Interface (ACPI) Specification, revision 2.0, 27 July
  • ACPI Advanced Configuration and Power Interface
  • the computing device Upon entering the suspend-to-memory sleep state, the computing device removes power from various components and/or subcomponents of the computing device but continues to power the system memory to retain the contents of the system memory. As a result of removing power, the computing device may remove power from circuitry used to protect secrets stored in the
  • the computing device may return power to the circuitry used to protect secrets stored in system memory.
  • the protection circuitry may be in a reset state and may not actually protect secrets in system memory. An attacker may successfully gain access to stored secrets prior to re-establishing the protections provided by
  • FIG. 1 illustrates an embodiment of a computing device.
  • FIG. 2 illustrates an embodiment of a security enhanced (SE) environment that may be established by the computing device of FIG. 1.
  • SE security enhanced
  • FIG. 3 illustrates an embodiment of a sleep method of the computing device of FIG. 1.
  • FIG. 4 illustrates an embodiment of a wake method of the computing
  • references herein to "symmetric" cryptography, keys, encryption or decryption, refer to cryptographic techniques in which the same key is used for encryption and decryption.
  • DES Data Encryption Standard
  • So called "public key” cryptographic techniques including the well- known Rivest-Shamir-Adleman (RSA) technique, are examples of asymmetric cryptography.
  • One of the two related keys of an asymmetric cryptographic system is referred to herein as a private key (because it is generally kept secret), and the other key as a public key (because it is generally made freely available).
  • RSA Rivest-Shamir-Adleman
  • either the private or public key may be used for encryption and the other key used for the associated decryption.
  • object is intended to be a broad term encompassing any grouping of one or more bits regardless of structure, format, or representation. Further, the verb “hash” and related forms are used herein to refer
  • the hash operation generates a digest value from which it is computationally infeasible to find a message with that hash and from which one cannot determine any usable information about a message with that hash. Further, the hash operation ideally generates the hash such that determining two messages which produce the same hash is computationally impossible. While the hash operation ideally has the above properties, in practice one way functions such as, for example, the Message Digest 5 function (MD5) and the Secure Hashing Algorithm 1 (SHA-1 ) generate hash values from which deducing the message are difficult, computationally intensive, and/or practically infeasible.
  • MD5 Message Digest 5 function
  • SHA-1 Secure Hashing Algorithm 1
  • Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors.
  • a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device).
  • a machine- readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others.
  • FIG. 1 An example embodiment of a computing device 100 is shown in FIG. 1.
  • the computing device 100 may comprise one or more processors 102 coupled to a chipset 104 via a processor bus 106.
  • the chipset 104 may comprise one or more integrated circuit packages or chips that couple the processors 102 to system memory 108, a token 110, firmware 112, non-volatile storage 114 (e.g. hard disk, floppy disk, optical disk, flash, programmable read only memory, etc.) and/or other devices 116 (e.g. a mouse, keyboard, video controller, etc.).
  • the processors 102 may support execution of a secure enter
  • SENTER SEXIT instruction to initiate creation of a SE environment such as, for example, the example SE environment of FIG. 2.
  • the processors 102 may further support a secure exit (SEXIT) instruction to initiate dismantling of a SE environment.
  • SEXIT secure exit
  • the processor 102 may issue bus messages on processor bus 106 in association with execution of the SENTER, SEXIT, and other instructions.
  • the processors 102 may further comprise a key 118 such as, for
  • the processor 102 may use the processor key 118 to authentic an authentic code (AC) module prior to executing the AC module.
  • the processor key 118 comprises an asymmetric private key to which only the processor 102 has access.
  • the processors 102 may support one or more operating modes such as, for example, a real mode, a protected mode, a virtual real mode, and a virtual machine mode (VMX mode). Further, the processors 102 may support one or more privilege levels or rings in each of the supported operating modes. In general, the operating modes and privilege levels of a processor 102 define the
  • a processor 102 may be permitted to execute certain privileged instructions only if the processor 102 is in an appropriate mode and/or privilege level.
  • the chipset 104 may comprise one or more chips or integrated circuits
  • the chipset 104 comprises a memory controller 120.
  • the processors 102 may comprise all or a portion of the memory controller 120.
  • the memory controller 120 provides an interface for components of the computing device 100 to access the system memory 108. Further, the memory controller 120 of the chipset 104 and/or processors 102 may define certain regions of the memory 108 as security enhanced (SE) memory 122. In one embodiment, the processors 102 may only access SE memory 122 when in an
  • the chipset 104 may comprise a key 124 that may be used to authentic an AC module prior to execution. Similar to the processor key 118, the chipset key 124 may comprise a symmetric cryptographic key, an asymmetric cryptographic key, or some other type of key. In one embodiment, the chipset key 5 124 comprises an asymmetric private key to which only the chipset 104 has access. In another embodiment, the chipset 104 comprises a hash of an asymmetric chipset key 124 stored in another component of the computing device 100. The chipset 104 may retrieve the chipset key 124 and authenticate the key 124 using the hash.
  • the chipset 104 may further comprise a secrets store 126 to indicate whether the system memory 108 might contain unencrypted secrets.
  • the secrets store 126 may comprise a flag that may be set to indicate that the system memory 108 might contain unencrypted secrets, and that may be cleared to indicate that the system memory 108 does not contain
  • the secrets store 126 may be located elsewhere such as, for example, the token 110, the processors 102, or other components of the computing device 100.
  • the secrets store 126 is implemented as a single volatile memory bit having backup power supplied by a battery.
  • the backup power supplied by a battery.
  • the chipset 104 may further comprise battery detection circuitry (not shown) to detect an interruption in power supplied by the battery.
  • the circuitry may further update the secrets store 126 to indicate that the system
  • the secrets store 126 may contain secrets in response to detecting a power interruption.
  • the secrets store 126 is implemented as a non-volatile memory bit such as a flash memory bit that does not require battery backup to retain its contents across a power removal/loss event.
  • the secrets store 126 is implemented with a single memory bit that may be set or
  • chipset 104 may further protect the secrets store 126 from unauthorized updates.
  • chipset 104 comprises a processor interface 128 to decode transactions of the processor bus 106 and/or receive messages from the processors 102.
  • the processors 102 may generate bus 5 transactions and/or messages in response to executing one or more privileged instructions that request the chipset 104 to update the secrets store 126.
  • the processor interface 128 may receive the bus transaction and/or messages and may update the secrets store 126 based upon the decoded bus transaction and/or messages.
  • valid execution of the privileged instructions is
  • the chipset 104 may further allow unprivileged updates of the secrets
  • processors 102 in response to executing one or more privileged instructions may generate bus transactions and/or messages that the request the chipset 104 to allow unprivileged updates of the secrets store 126. Further, the processors 102 in response to executing one/or more unprivileged or privileged instructions may generate bus transactions and/or
  • the processors 102 in response to executing one or more unprivileged instructions may generate bus transactions and/or messages that request the chipset 104 to update the secrets store 126.
  • the processor interface 128 may receive the bus transactions and/or messages and may allow
  • valid execution of the privileged instructions to request unprivileged updates is restricted to software executing at a particular processor privilege level. For example, in one embodiment valid execution of these privileged instructions is
  • the chipset 104 may further comprise a sleep controller 130, a sleep type store 132, and a sleep enable store 134.
  • the sleep controller 130 in one embodiment selectively powers components and/or subcomponents based upon the sleep type store 132 and the sleep enable store 134.
  • a 5 value may be stored in the sleep type store 132 to indicate into which sleep state (e.g. ACPI sleep states S1 , S2, S3, S4) the sleep controller 130 is to place the computing device 100.
  • the sleep enable store 134 may be updated to invoke entry into the sleep state indicated by the sleep state store 132.
  • the sleep enable store 134 may comprise a flag that in response to being set causes lo the sleep controller 130 to place the computing device 100 in the requested sleep state.
  • the chipset 104 may further comprise sleep attack detection logic 136 that detects probable sleep attacks.
  • a sleep method updates the secrets store 126 to indicate that the the system memory 108 contains no
  • the sleep attack detection logic 136 determines that a sleep attack is probable in response to (i) the secrets store 126 indicating that the system memory 108 might contain unencrypted secrets and (ii) the sleep enable store 134 requesting that the sleep
  • the sleep attack detection logic 136 initiates a sleep attack response such as, for example, generating a system reset event, a system halt event, a system shutdown event, a system power off event, or some other response to protect the secrets stored in system memory 108.
  • the sleep attack detection logic 136 further determines based upon the sleep state to be entered whether to invoke a sleep attack response. For example, circuitry used to protect secrets stored in the SE memory 122 may remain effective during a given sleep state. Accordingly, the sleep attack detection logic 136 may either decide that no sleep attack is
  • the sleep type store 132 indicates a sleep state in which SE memory protections remain effective.
  • the chipset 104 may also support standard I/O operations on I/O buses such as peripheral component interconnect (PCI), accelerated graphics port 5 (AGP), universal serial bus (USB), low pin count (LPC) bus, or any other kind of I/O bus (not shown).
  • the chipset 104 may comprise a token interface 138 to connect chipset 104 with a token 110 that comprises one or more platform configuration registers (PCR) 140.
  • token interface 138 may comprise an LPC bus interface (LPC Interface Specification, Intel Corporation,
  • the token 110 may record metrics in a security enhanced manner, may quote metrics in a security enhanced manner, may seal secrets to a particular environment (current or future), and may unseal secrets to the environment to which they were sealed.
  • the token 110 may comprise one or more
  • the token 110 may further comprise one or more platform configuration registers (PCR registers) 140 to record and report metrics in a security enhanced manner.
  • PCR registers platform configuration registers
  • the token 110 supports a PCR extend operation that records
  • the token 110 may also support a PCR quote operation that returns a quote or contents of an identified PCR register 140.
  • the token 110 may further support a seal operation and an unseal operation. In response to a seal operation,
  • the token 110 generates a sealed object comprising an object sealed to the token 110 and a specified device environment. Conversely, the token 110 may return an object of a sealed object in response to an unseal operation only if the object was sealed with a key of the token 110 and the current device environment satisfies environment criteria specified for the sealed object.
  • the token 110 may return an object of a sealed object in response to an unseal operation only if the object was sealed with a key of the token 110 and the current device environment satisfies environment criteria specified for the sealed object.
  • TPM Trusted Platform Module
  • TCPA Trusted Computing Platform Alliance
  • the firmware 112 comprises Basic Input/Output
  • BIOS System routines
  • the BIOS 144 may comprise AC modules, sleep 5 code, wake code, system start-up code and/or structures.
  • BIOS 144 may comprise ACPI structures and ACPI Source Language (ASL) code which may be accessed and/or executed during sleep event processing, wake event processing, and/or computing device initialization.
  • ASL ACPI Source Language
  • the SE lo environment 200 may be initiated in response to various events such as, for example, system startup, an application request, an operating system request, etc.
  • the SE environment 200 may comprise a trusted virtual machine kernel or monitor 202, one or more standard virtual machines (standard VMs) 204, and one or more trusted virtual machines (trusted VMs) 206.
  • 15 the monitor 202 of the SE environment 200 executes in the protected mode at the most privileged processor ring (e.g. OP) to manage security and provide barriers between the virtual machines 204, 206.
  • the most privileged processor ring e.g. OP
  • the standard VM 204 may comprise an operating system 208 that executes at the most privileged processor ring of the VMX mode (e.g. 0D), and
  • the operating system 208 does not have unfettered control of the computing device 100 but instead is subject to the control and restraints of the
  • the monitor 202 may prevent the operating system 208 and its applications 210 from directly accessing the SE memory 122 and the token 110.
  • the monitor 202 may further comprise sleep logic 212 and one or more monitor keys 214 to encrypt and/or otherwise protect information.
  • the sleep logic 212 comprises code to perform one or more sleep operations such as, for example, encrypting and attesting to memory contents.
  • the monitor keys 214 may comprise symmetric cryptographic keys, asymmetric cryptographic keys, or other keys to which the monitor 202 has exclusive control.
  • the monitor 5 keys 214 may comprise a symmetric root key and one or more asymmetric keys that are encrypted with the symmetric root key.
  • the monitor 202 may perform one or more measurements of the trusted kernel 216 such as a hash of the kernel code to obtain one or more metrics, may cause the token 110 to extend a PCR register 140 with the metrics of the kernel lo 216, and may record the metrics in an associated PCR log stored in SE memory 122.
  • the monitor 202 may further establish the trusted VM 206 in SE memory 122 and launch the trusted kernel 216 in the established trusted VM 206.
  • the trusted kernel 216 may take one or more measurements of an applet or application 218 such as a hash of the applet code to obtain one or
  • the trusted kernel 216 via the monitor 202 may then cause the physical token 110 to extend a PCR register 140 with the metrics of the applet 218.
  • the trusted kernel 216 may further record the metrics in an associated PCR log stored in SE memory 122. Further, the trusted kernel 216 may launch the trusted applet 218 in the established trusted VM 206 of the SE memory 122.
  • the computing device 100 further records metrics of the monitor 202 and hardware components of the computing device 100 in one or more PCR registers 140 of the token 110.
  • the processor 102 may obtain hardware identifiers such as, for example, processor family, processor version, processor microcode
  • the processor 102 may then record the obtained hardware identifiers in one or more PCR registers 140.
  • the computing device 100 may perform the method in response to a sleep event.
  • a sleep event may be generated in response to a device and/or an operating system detecting that a device has remained idle for a predetermined length of time.
  • the operating system 208 may determine in block 300 whether an SE environment 5 200 is currently established.
  • the computing device 100 in block 302 may invoke a sleep entry process (described in more detail below) to place the computing device 100 into a requested sleep state.
  • the monitor 202 in block 304 may encrypt and attest to the contents of the SE memory 122.
  • the monitor 202 encrypts the pages of the SE memory 122 using one of the monitor keys 214 and replaces the pages with encrypted pages.
  • the monitor 202 may leave portions of the SE memory 122 that contain the monitor 202 or the portions of the SE memory 122 that contain the 15 sleep logic 212 of the monitor 202 unencrypted so that processors 102 may continue to execute the sleep logic 212.
  • the monitor 202 in block 304 may further attest to the contents of the
  • the monitor 202 may generate a contents attestation by hashing the encrypted contents of the SE memory 122 to obtain a
  • the monitor 202 may generate the contents attestation by hashing only the pages that will remain in the SE memory 122 after the wake process. For example, the wake process may reload the monitor 202 and/or other code from non-volatile storage 114. Since these portions of the SE memory 122 are reloaded, the computing device 100 may erase these portions of the SE memory 122.
  • the monitor 202 may attest to the contents of the SE memory 122 by embedding a content attestation such as, for example, a watermark, signature, and/or other information in the attested contents of the SE memory 122.
  • the monitor 202 may generate and attest to a data structure (e.g. a page table, page list, segment list, region list, etc.) that identifies pages/segments/regions of system memory 122 encrypted in block 304.
  • the monitor 202 may generate a data structure attestation by 5 hashing the data structure to obtain a data structure hash.
  • the monitor 202 may attest to the data structure by embedding a data structure attestation such as, for example, a watermark, signature, and/or other information in the attested data structure.
  • the monitor 202 in block 308 may seal the content attestation, the data
  • the monitor 202 seals the content attestation, the data structure attestation, and the monitor keys 214 via one or more seal operations of the token 110 to obtain one or more sealed resume objects.
  • the seal operations use a PCR register 140 15 containing a metric of the monitor 202 to effectively prevent another monitor such as, for example, a rogue monitor from accessing and/or altering the unencrypted contents of the sealed resume objects.
  • the monitor 202 dismantles the SE environment 200.
  • the monitor 202 may perform various operations as part of the dismantling process.
  • the monitor 202 updates the secrets store 126 to indicate that the system memory 108 does not contain unencrypted secrets. For example, the monitor 202 may clear a flag of the secrets store 126 to indicate the system memory 108 does not contain unencrypted secrets. Further, the monitor 202 may shutdown the trusted virtual machines 206 and may exit the VMX processor
  • the monitor 202 may further erase regions of the system memory 108 that will be reloaded from non-volatile storage 114 during the wake process.
  • the computing device 100 may cease execution of the monitor 202 and return to execution of the operating system 208.
  • the monitor 202 may cease execution of the monitor 202 and return to execution of the operating system 208.
  • the monitor 202 may cease execution of the monitor 202 and return to execution of the operating system 208.
  • the computing device 100 may utilize other mechanisms to enable the operating system 208 to retrieve the monitor 202 and sealed resume objects during the 5 wake process.
  • the monitor 202 and/or sealed resume objects may be stored at predetermined locations or at locations set by the BIOS 144.
  • the operating system 208 in block 314 may save the resume information so that it may be retrieved as part of the wake process.
  • the operating system 208 may store the SE environment resume information at predetermined
  • the monitor 202 in block 312 stores the information at the appropriate locations, thus relieving the operating system 208 of saving the information in block 314.
  • the operating system 208 and/or the BIOS 144 in block 302 may
  • the operating system 208 and/or the BIOS 144 may write a sleep type identifier to the sleep type store 132 to indicate which sleep state the computing device 100 is entering and may update the sleep enable store 134 to invoke entry into the sleep state.
  • the operating system 208 and/or BIOS 144 may cause the
  • the operating system 208 and/or BIOS 144 may elect to change the sleep state for various reasons such as, for example, one or more components of the computing device 100 not supporting the requested sleep state.
  • the sleep type store 132 and sleep enable stores 134 In response to updating the sleep type store 132 and sleep enable stores 134, the sleep
  • controller 130 may cause the computing device 100 to enter the sleep state and may complete the sleep process.
  • the sleep controller 130 may remove power from components and/or subcomponents of the computing devices 100, may request components and/or subcomponents to enter a low power mode of operation, and/or may cause the contents of system memory 108 to be written
  • the computing device 100 may perform the wake method in response to a wake event.
  • a wake event may be generated in response various stimuli such as, for example, a modem detecting a ring event, a network controller detecting
  • the sleep controller 130 in block 400 may perform one or more wake operations such as, for example, waking the processors 102 and transferring saved state information from the non-volatile storage 114 to the system memory 108.
  • the sleep controller 130 in one embodiment may perform lo one or more of the wake operations in response to executing ASL and/or other code of the BIOS 144.
  • the sleep controller 130 may transfer control to the operating system 208.
  • the sleep logic 212 invokes execution of the operating system 208 from a location identified by a wake vector.
  • the operating system 208 in block 402 may perform one or more wake operations, such as, waking network controllers, modems, and/or other devices of the computing device 100.
  • the operating system 208 determines whether to restore an SE environment 200 based upon stored resume information and/or the lack of stored resume information. In response to determining to
  • the operating system 208 performs various operations. For example, the operating system 208 may load, authenticate, and initiate execution of AC modules that configure the computing device 100 and/or verify the configuration of the computing device 100. Further, the operating system 208 in block 406 may load and invoke execution of the monitor 202
  • the monitor 202 may unseal the sealed resume objects to obtain the contents attestation, the data structure attestation, and the monitor keys 214 via one or more unseal operations of the token 110.
  • the monitor 202 in block 412 invokes
  • the monitor 202 invokes the sleep attack response by writing to a reset register of the chipset 104 to invoke a system reset.
  • the monitor 202 may respond in other ways such as, for example, halting the processors 102, erasing system memory 108, invoking a system shutdown, removing power from the computing device 100, and/or other actions that protect the secrets from unauthorized access 5 and/or alteration.
  • the monitor 202 verifies the authenticity of the data structure base upon the data structure attestation.
  • the monitor 202 hashes the data structure to obtain a computed data structure attestation.
  • the monitor 202 further compares the computed data structure
  • the monitor 202 in block 412 invokes a sleep
  • the monitor 202 in block 416 may decrypt portions of system memory
  • the monitor 202 may decrypt the portions of the system memory 108 identified by the data structure using one or more unsealed monitor keys 214. In block 418, the monitor 202 may
  • the monitor 202 may hash the decrypted contents added to the SE memory 122 to obtain a computed contents attestation. In another embodiment, the monitor 202 may hash the encrypted contents to be added to the SE memory 122 to obtain a computed contents attestation. The monitor 202 may further
  • the monitor 202 in block 412 may invoke an attack
  • the monitor 202 completes the wake process by invoking execution of the operating system 208.
  • the sleep and wake methods help protect secrets from attack.
  • an attacker may attempt to circumvent the sleeping 5 method of FIG. 3 to place the computing device 100 in a sleep state in which unencrypted secrets reside in system memory 108 and/or non-volatile storage 114 unprotected.
  • the sleep attack detection logic 136 may invoke a system reset event or another attack response in response to detecting a probable sleep attack.
  • the sleep attack detection logic 136 may invoke a system reset event or another attack response in response to detecting a probable sleep attack.
  • the monitor 202 updates the secrets store 126 to indicate that the system memory 108 contains no unencrypted secrets prior to updating the sleep enable store 134 to initiate the sleep entry process. Accordingly, the sleep attack detection logic 136 may invoke a sleep attack response in response to the sleep enable store 134 being updated if the secrets store 420 indicates that the
  • system memory 108 might contain unencrypted secrets.
  • the monitor 202 encrypts the SE memory 122 and updates the secrets store 126 to indicate that the system memory 108 contains no unencrypted secrets only if the requested sleep state would result in the SE memory 122 being unprotected. Accordingly,
  • sleep attack detection logic 136 may invoke a sleep attack response in response to the sleep enable store 134 being updated if the secrets store 420 indicates that the system memory 108 might contain unencrypted secrets and the sleep type store 132 indicates a sleep state in which the SE memory 122 map be unprotected.

Abstract

Methods, apparatus and machine-readable medium are described that attempt to protect secrets from sleep attacks. In some embodiments, the secrets are encrypted and a security enhanced environment dismantled prior to entering a sleep state. Some embodiments further re-establish a security enhanced environment and decrypt the secrets in response to a wake event.

Description

SLEEP PROTECTION
BACKGROUND
[0001] Financial and personal transactions are being performed on computing devices at an increasing rate. However, the continual growth of such financial and 5 personal transactions is dependent in part upon the establishment of security enhanced (SE) environments that attempt to prevent loss of privacy, corruption of data, abuse of data, etc. An SE environment may employ various techniques to prevent different kinds of attacks or unauthorized access to protected data or secrets (e.g. social security number, account numbers, bank balances, lo passwords, authorization keys, etc.). One type of attack that an SE environment may attempt to prevent is a sleep attack.
[0002] For example, many computing devices support a suspend-to-memory sleep state such as, for example, the S3 sleep state described in the Advanced Configuration and Power Interface (ACPI) Specification, revision 2.0, 27 July
15 2000. Upon entering the suspend-to-memory sleep state, the computing device removes power from various components and/or subcomponents of the computing device but continues to power the system memory to retain the contents of the system memory. As a result of removing power, the computing device may remove power from circuitry used to protect secrets stored in the
20 system memory. Upon waking from the sleep state, the computing device may return power to the circuitry used to protect secrets stored in system memory. However, after returning power, the protection circuitry may be in a reset state and may not actually protect secrets in system memory. An attacker may successfully gain access to stored secrets prior to re-establishing the protections provided by
25 the protection circuitry. BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The invention described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. 5 For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.
[0004] FIG. 1 illustrates an embodiment of a computing device.
P005] FIG. 2 illustrates an embodiment of a security enhanced (SE) environment that may be established by the computing device of FIG. 1.
[0006] FIG. 3 illustrates an embodiment of a sleep method of the computing device of FIG. 1.
[0007] FIG. 4 illustrates an embodiment of a wake method of the computing
15 device of FIG. 1.
DETAILED DESCRIPTION
[0008] The following description describes techniques for protecting secrets from sleep attacks. In the following description, numerous specific details such as logic implementations, opcodes, means to specify operands, resource
20 partitioning/sharing/duplication implementations, types and interrelationships of system components, and logic partitioning/integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level
25 circuits and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.
[0009] References in the specification to "one embodiment", "an embodiment",
"an example embodiment", etc., indicate that the embodiment described may
5 include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of to one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0010] References herein to "symmetric" cryptography, keys, encryption or decryption, refer to cryptographic techniques in which the same key is used for encryption and decryption. The well known Data Encryption Standard (DES)
15 published in 1993 as Federal Information Publishing Standard FIPS PUB 46-2, and Advanced Encryption Standard (AES), published in 2001 as FIPS PUB 197, are examples of symmetric cryptography. Reference herein to "asymmetric" cryptography, keys, encryption or decryption, refer to cryptographic techniques in which different but related keys are used for encryption and decryption,
20 respectively. So called "public key" cryptographic techniques, including the well- known Rivest-Shamir-Adleman (RSA) technique, are examples of asymmetric cryptography. One of the two related keys of an asymmetric cryptographic system is referred to herein as a private key (because it is generally kept secret), and the other key as a public key (because it is generally made freely available). In some
25 embodiments either the private or public key may be used for encryption and the other key used for the associated decryption.
[0011] As used herein, the term "object" is intended to be a broad term encompassing any grouping of one or more bits regardless of structure, format, or representation. Further, the verb "hash" and related forms are used herein to refer
30 to performing an operation upon an operand or message to produce a digest value or a "hash". Ideally, the hash operation generates a digest value from which it is computationally infeasible to find a message with that hash and from which one cannot determine any usable information about a message with that hash. Further, the hash operation ideally generates the hash such that determining two messages which produce the same hash is computationally impossible. While the hash operation ideally has the above properties, in practice one way functions such as, for example, the Message Digest 5 function (MD5) and the Secure Hashing Algorithm 1 (SHA-1 ) generate hash values from which deducing the message are difficult, computationally intensive, and/or practically infeasible.
] Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine- readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others.
] An example embodiment of a computing device 100 is shown in FIG. 1.
The computing device 100 may comprise one or more processors 102 coupled to a chipset 104 via a processor bus 106. The chipset 104 may comprise one or more integrated circuit packages or chips that couple the processors 102 to system memory 108, a token 110, firmware 112, non-volatile storage 114 (e.g. hard disk, floppy disk, optical disk, flash, programmable read only memory, etc.) and/or other devices 116 (e.g. a mouse, keyboard, video controller, etc.).
] The processors 102 may support execution of a secure enter
(SENTER) instruction to initiate creation of a SE environment such as, for example, the example SE environment of FIG. 2. The processors 102 may further support a secure exit (SEXIT) instruction to initiate dismantling of a SE environment. In one embodiment, the processor 102 may issue bus messages on processor bus 106 in association with execution of the SENTER, SEXIT, and other instructions.
[0015] The processors 102 may further comprise a key 118 such as, for
5 example, a symmetric cryptographic key, an asymmetric cryptographic key, or some other type of key. The processor 102 may use the processor key 118 to authentic an authentic code (AC) module prior to executing the AC module. In one embodiment, the processor key 118 comprises an asymmetric private key to which only the processor 102 has access.
016] The processors 102 may support one or more operating modes such as, for example, a real mode, a protected mode, a virtual real mode, and a virtual machine mode (VMX mode). Further, the processors 102 may support one or more privilege levels or rings in each of the supported operating modes. In general, the operating modes and privilege levels of a processor 102 define the
15 instructions available for execution and the effect of executing such instructions. More specifically, a processor 102 may be permitted to execute certain privileged instructions only if the processor 102 is in an appropriate mode and/or privilege level.
[0017] The chipset 104 may comprise one or more chips or integrated circuits
20 packages that interface the processors 102 to components of the computing device 100 such as, for example, system memory 108, the token 110, non-volatile storage 114, and the other devices 116. In one embodiment, the chipset 104 comprises a memory controller 120. However, in other embodiments, the processors 102 may comprise all or a portion of the memory controller 120. In
25 general, the memory controller 120 provides an interface for components of the computing device 100 to access the system memory 108. Further, the memory controller 120 of the chipset 104 and/or processors 102 may define certain regions of the memory 108 as security enhanced (SE) memory 122. In one embodiment, the processors 102 may only access SE memory 122 when in an
30 appropriate operating mode (e.g. protected mode) and privilege level (e.g. OP). [0018] Further, the chipset 104 may comprise a key 124 that may be used to authentic an AC module prior to execution. Similar to the processor key 118, the chipset key 124 may comprise a symmetric cryptographic key, an asymmetric cryptographic key, or some other type of key. In one embodiment, the chipset key 5 124 comprises an asymmetric private key to which only the chipset 104 has access. In another embodiment, the chipset 104 comprises a hash of an asymmetric chipset key 124 stored in another component of the computing device 100. The chipset 104 may retrieve the chipset key 124 and authenticate the key 124 using the hash.
019] The chipset 104 may further comprise a secrets store 126 to indicate whether the system memory 108 might contain unencrypted secrets. In one embodiment, the secrets store 126 may comprise a flag that may be set to indicate that the system memory 108 might contain unencrypted secrets, and that may be cleared to indicate that the system memory 108 does not contain
15 unencrypted secrets. In other embodiments, the secrets store 126 may be located elsewhere such as, for example, the token 110, the processors 102, or other components of the computing device 100.
[0020] In one embodiment, the secrets store 126 is implemented as a single volatile memory bit having backup power supplied by a battery. The backup power
20 supplied by the battery maintains the contents of the secrets store 126 across a system reset, a sleep event, a system shutdown, a system power down, or other power removal/loss event. The chipset 104 may further comprise battery detection circuitry (not shown) to detect an interruption in power supplied by the battery. The circuitry may further update the secrets store 126 to indicate that the system
25 memory 108 may contain secrets in response to detecting a power interruption. In another embodiment, the secrets store 126 is implemented as a non-volatile memory bit such as a flash memory bit that does not require battery backup to retain its contents across a power removal/loss event. In one embodiment, the secrets store 126 is implemented with a single memory bit that may be set or
30 cleared. However, other embodiments may comprise a secrets store 126 having a different storage capacity and/or utilizing a different status encoding. [0021 ] The chipset 104 may further protect the secrets store 126 from unauthorized updates. In one embodiment, chipset 104 comprises a processor interface 128 to decode transactions of the processor bus 106 and/or receive messages from the processors 102. The processors 102 may generate bus 5 transactions and/or messages in response to executing one or more privileged instructions that request the chipset 104 to update the secrets store 126. The processor interface 128 may receive the bus transaction and/or messages and may update the secrets store 126 based upon the decoded bus transaction and/or messages. In one embodiment, valid execution of the privileged instructions is
10 restricted to software executing at a particular processor privilege level. For example, in one embodiment valid execution of the privileged instructions is restricted to a monitor executing at the most privileged processor level. (See, FIG. 2).
[0022] The chipset 104 may further allow unprivileged updates of the secrets
15 store 126. In one embodiment, the processors 102 in response to executing one or more privileged instructions may generate bus transactions and/or messages that the request the chipset 104 to allow unprivileged updates of the secrets store 126. Further, the processors 102 in response to executing one/or more unprivileged or privileged instructions may generate bus transactions and/or
20 messages that request the chipset 104 to deny unprivileged updates of the secrets store 126. The processors 102 in response to executing one or more unprivileged instructions may generate bus transactions and/or messages that request the chipset 104 to update the secrets store 126. The processor interface 128 may receive the bus transactions and/or messages and may allow
25 unprivileged updates, deny unprivileged updates, and/or update the secrets store 126 based upon the decoded bus transactions and/or messages. In one embodiment, valid execution of the privileged instructions to request unprivileged updates is restricted to software executing at a particular processor privilege level. For example, in one embodiment valid execution of these privileged instructions is
30 restricted to a monitor executing at the most privileged processor level, thus allowing the monitor to grant selected non-privileged code (e.g. an AC module) write access to the secrets store 126. [0023] The chipset 104 may further comprise a sleep controller 130, a sleep type store 132, and a sleep enable store 134. The sleep controller 130 in one embodiment selectively powers components and/or subcomponents based upon the sleep type store 132 and the sleep enable store 134. In one embodiment, a 5 value may be stored in the sleep type store 132 to indicate into which sleep state (e.g. ACPI sleep states S1 , S2, S3, S4) the sleep controller 130 is to place the computing device 100. The sleep enable store 134 may be updated to invoke entry into the sleep state indicated by the sleep state store 132. For example, the sleep enable store 134 may comprise a flag that in response to being set causes lo the sleep controller 130 to place the computing device 100 in the requested sleep state.
[0024] The chipset 104 may further comprise sleep attack detection logic 136 that detects probable sleep attacks. In one embodiment, a sleep method updates the secrets store 126 to indicate that the the system memory 108 contains no
15 unencrypted secrets prior to updating the sleep enable store 134 to initiate the sleep entry process. Therefore, the sleep attack detection logic 136 in one embodiment determines that a sleep attack is probable in response to (i) the secrets store 126 indicating that the system memory 108 might contain unencrypted secrets and (ii) the sleep enable store 134 requesting that the sleep
20 entry process be invoked. In response to detecting a probable sleep attack, the sleep attack detection logic 136 initiates a sleep attack response such as, for example, generating a system reset event, a system halt event, a system shutdown event, a system power off event, or some other response to protect the secrets stored in system memory 108.
[8025] In another embodiment, the sleep attack detection logic 136 further determines based upon the sleep state to be entered whether to invoke a sleep attack response. For example, circuitry used to protect secrets stored in the SE memory 122 may remain effective during a given sleep state. Accordingly, the sleep attack detection logic 136 may either decide that no sleep attack is
30 occurring or may decide not to invoke a sleep attack response if the sleep type store 132 indicates a sleep state in which SE memory protections remain effective.
[0026] The chipset 104 may also support standard I/O operations on I/O buses such as peripheral component interconnect (PCI), accelerated graphics port 5 (AGP), universal serial bus (USB), low pin count (LPC) bus, or any other kind of I/O bus (not shown). In particular, the chipset 104 may comprise a token interface 138 to connect chipset 104 with a token 110 that comprises one or more platform configuration registers (PCR) 140. In one embodiment, token interface 138 may comprise an LPC bus interface (LPC Interface Specification, Intel Corporation,
10 rev. 1.0, 29 December 1997).
[0027] In general, the token 110 may record metrics in a security enhanced manner, may quote metrics in a security enhanced manner, may seal secrets to a particular environment (current or future), and may unseal secrets to the environment to which they were sealed. The token 110 may comprise one or more
15 keys 142 that may be used to support the above operations. The token keys 142 may include symmetric keys, asymmetric keys, and/or some other type of key. The token 110 may further comprise one or more platform configuration registers (PCR registers) 140 to record and report metrics in a security enhanced manner. In one embodiment, the token 110 supports a PCR extend operation that records
20 a received metric in an identified PCR register 140 in a security enhanced manner.
[0028] The token 110 may also support a PCR quote operation that returns a quote or contents of an identified PCR register 140. The token 110 may further support a seal operation and an unseal operation. In response to a seal operation,
25 the token 110 generates a sealed object comprising an object sealed to the token 110 and a specified device environment. Conversely, the token 110 may return an object of a sealed object in response to an unseal operation only if the object was sealed with a key of the token 110 and the current device environment satisfies environment criteria specified for the sealed object. In one embodiment, the token
30 110 may comprise a Trusted Platform Module (TPM) as described in the Trusted Computing Platform Alliance (TCPA) Main Specification, Version 1.1a, 1 December 2001 or a variant thereof.
[0029] In an embodiment, the firmware 112 comprises Basic Input/Output
System routines (BIOS) 144. The BIOS 144 may comprise AC modules, sleep 5 code, wake code, system start-up code and/or structures. For example, the BIOS 144 may comprise ACPI structures and ACPI Source Language (ASL) code which may be accessed and/or executed during sleep event processing, wake event processing, and/or computing device initialization.
[0030] One embodiment of an SE environment 200 is shown in FIG. 2. The SE lo environment 200 may be initiated in response to various events such as, for example, system startup, an application request, an operating system request, etc. As shown, the SE environment 200 may comprise a trusted virtual machine kernel or monitor 202, one or more standard virtual machines (standard VMs) 204, and one or more trusted virtual machines (trusted VMs) 206. In one embodiment, 15 the monitor 202 of the SE environment 200 executes in the protected mode at the most privileged processor ring (e.g. OP) to manage security and provide barriers between the virtual machines 204, 206.
[0031] The standard VM 204 may comprise an operating system 208 that executes at the most privileged processor ring of the VMX mode (e.g. 0D), and
20 one or more applications 210 that execute at a lower privileged processor ring of the VMX mode (e.g. 3D). Since the processor ring in which the monitor 202 executes is more privileged than the processor ring in which the operating system 208 executes, the operating system 208 does not have unfettered control of the computing device 100 but instead is subject to the control and restraints of the
25 monitor 202. In particular, the monitor 202 may prevent the operating system 208 and its applications 210 from directly accessing the SE memory 122 and the token 110.
[0032] The monitor 202 may further comprise sleep logic 212 and one or more monitor keys 214 to encrypt and/or otherwise protect information. The sleep logic 212 comprises code to perform one or more sleep operations such as, for example, encrypting and attesting to memory contents. The monitor keys 214 may comprise symmetric cryptographic keys, asymmetric cryptographic keys, or other keys to which the monitor 202 has exclusive control. For example, the monitor 5 keys 214 may comprise a symmetric root key and one or more asymmetric keys that are encrypted with the symmetric root key.
[0033] The monitor 202 may perform one or more measurements of the trusted kernel 216 such as a hash of the kernel code to obtain one or more metrics, may cause the token 110 to extend a PCR register 140 with the metrics of the kernel lo 216, and may record the metrics in an associated PCR log stored in SE memory 122. The monitor 202 may further establish the trusted VM 206 in SE memory 122 and launch the trusted kernel 216 in the established trusted VM 206.
[0034] Similarly, the trusted kernel 216 may take one or more measurements of an applet or application 218 such as a hash of the applet code to obtain one or
15 more metrics. The trusted kernel 216 via the monitor 202 may then cause the physical token 110 to extend a PCR register 140 with the metrics of the applet 218. The trusted kernel 216 may further record the metrics in an associated PCR log stored in SE memory 122. Further, the trusted kernel 216 may launch the trusted applet 218 in the established trusted VM 206 of the SE memory 122.
035] In response to initiating the SE environment 200 of FIG. 2, the computing device 100 further records metrics of the monitor 202 and hardware components of the computing device 100 in one or more PCR registers 140 of the token 110. For example, the processor 102 may obtain hardware identifiers such as, for example, processor family, processor version, processor microcode
25 version, chipset version, and physical token version of the processors 102, chipset 104, and physical token 110. The processor 102 may then record the obtained hardware identifiers in one or more PCR registers 140.
[0036] Referring now to FIG. 3, an embodiment of a method to enter a sleep state is illustrated. The computing device 100 may perform the method in response to a sleep event. For example, a sleep event may be generated in response to a device and/or an operating system detecting that a device has remained idle for a predetermined length of time. In response to the sleep event, the operating system 208 may determine in block 300 whether an SE environment 5 200 is currently established. In response to determining that no SE environment 200 is established, the computing device 100 in block 302 may invoke a sleep entry process (described in more detail below) to place the computing device 100 into a requested sleep state.
[0037] In response to determining that an SE environment 200 is established,
10 the request, the monitor 202 in block 304 may encrypt and attest to the contents of the SE memory 122. In one embodiment, the monitor 202 encrypts the pages of the SE memory 122 using one of the monitor keys 214 and replaces the pages with encrypted pages. The monitor 202 may leave portions of the SE memory 122 that contain the monitor 202 or the portions of the SE memory 122 that contain the 15 sleep logic 212 of the monitor 202 unencrypted so that processors 102 may continue to execute the sleep logic 212.
[0038] The monitor 202 in block 304 may further attest to the contents of the
SE memory 122. In one embodiment, the monitor 202 may generate a contents attestation by hashing the encrypted contents of the SE memory 122 to obtain a
20 memory hash. In another embodiment, the monitor 202 may generate the contents attestation by hashing only the pages that will remain in the SE memory 122 after the wake process. For example, the wake process may reload the monitor 202 and/or other code from non-volatile storage 114. Since these portions of the SE memory 122 are reloaded, the computing device 100 may erase these
25 portions from system memory 108 and/or may not save them to non-volatile storage 114 prior to entering the sleep state. In another embodiment, the monitor 202 may attest to the contents of the SE memory 122 by embedding a content attestation such as, for example, a watermark, signature, and/or other information in the attested contents of the SE memory 122. [0039] In block 306, the monitor 202 may generate and attest to a data structure (e.g. a page table, page list, segment list, region list, etc.) that identifies pages/segments/regions of system memory 122 encrypted in block 304. In one embodiment, the monitor 202 may generate a data structure attestation by 5 hashing the data structure to obtain a data structure hash. In another embodiment, the monitor 202 may attest to the data structure by embedding a data structure attestation such as, for example, a watermark, signature, and/or other information in the attested data structure.
[0040] The monitor 202 in block 308 may seal the content attestation, the data
10 structure attestation, and/or the monitor keys 214 to protect them from unauthorized access and/or alteration. In one embodiment, the monitor 202 seals the content attestation, the data structure attestation, and the monitor keys 214 via one or more seal operations of the token 110 to obtain one or more sealed resume objects. In one embodiment, the seal operations use a PCR register 140 15 containing a metric of the monitor 202 to effectively prevent another monitor such as, for example, a rogue monitor from accessing and/or altering the unencrypted contents of the sealed resume objects.
[0041] In block 310, the monitor 202 dismantles the SE environment 200. The monitor 202 may perform various operations as part of the dismantling process. In
20 one embodiment, the monitor 202 updates the secrets store 126 to indicate that the system memory 108 does not contain unencrypted secrets. For example, the monitor 202 may clear a flag of the secrets store 126 to indicate the system memory 108 does not contain unencrypted secrets. Further, the monitor 202 may shutdown the trusted virtual machines 206 and may exit the VMX processor
25 mode. The monitor 202 may further erase regions of the system memory 108 that will be reloaded from non-volatile storage 114 during the wake process.
[0042] In block 312, the computing device 100 may cease execution of the monitor 202 and return to execution of the operating system 208. In one embodiment, as a result of returning to the operating system 208, the monitor 202
30 provides the operating system 208 with SE environment resume information that identifies the location and size of the monitor 202 to be executed in response to waking and the location and size of the sealed resume objects. However, the computing device 100 may utilize other mechanisms to enable the operating system 208 to retrieve the monitor 202 and sealed resume objects during the 5 wake process. For example, the monitor 202 and/or sealed resume objects may be stored at predetermined locations or at locations set by the BIOS 144.
[0043] The operating system 208 in block 314 may save the resume information so that it may be retrieved as part of the wake process. The operating system 208 may store the SE environment resume information at predetermined
10 locations of the system memory 108, at locations set by the BIOS 144, nonvolatile registers of the chipset 104, and/or other locations. In one embodiment, the monitor 202 in block 312 stores the information at the appropriate locations, thus relieving the operating system 208 of saving the information in block 314.
[0044] The operating system 208 and/or the BIOS 144 in block 302 may
15 complete the sleep entry process. For example, the operating system 208 and/or the BIOS 144 may write a sleep type identifier to the sleep type store 132 to indicate which sleep state the computing device 100 is entering and may update the sleep enable store 134 to invoke entry into the sleep state. In one embodiment, the operating system 208 and/or BIOS 144 may cause the
20 computing device 100 to enter a sleep state that is different than the sleep state requested. The operating system 208 and/or BIOS 144 may elect to change the sleep state for various reasons such as, for example, one or more components of the computing device 100 not supporting the requested sleep state. In response to updating the sleep type store 132 and sleep enable stores 134, the sleep
25 controller 130 may cause the computing device 100 to enter the sleep state and may complete the sleep process. For example, the sleep controller 130 may remove power from components and/or subcomponents of the computing devices 100, may request components and/or subcomponents to enter a low power mode of operation, and/or may cause the contents of system memory 108 to be written
30 to non-volatile storage 114. [0045] Referring now to FIG. 4, a method of waking from a sleep state is illustrated. The computing device 100 may perform the wake method in response to a wake event. A wake event may be generated in response various stimuli such as, for example, a modem detecting a ring event, a network controller detecting
5 network activity, a keyboard controller detecting a key press, etc. In response to the wake event, the sleep controller 130 in block 400 may perform one or more wake operations such as, for example, waking the processors 102 and transferring saved state information from the non-volatile storage 114 to the system memory 108. The sleep controller 130 in one embodiment may perform lo one or more of the wake operations in response to executing ASL and/or other code of the BIOS 144. After performing the wake operations, the sleep controller 130 may transfer control to the operating system 208. In one embodiment, the sleep logic 212 invokes execution of the operating system 208 from a location identified by a wake vector.
046] The operating system 208 in block 402 may perform one or more wake operations, such as, waking network controllers, modems, and/or other devices of the computing device 100. In block 404, the operating system 208 determines whether to restore an SE environment 200 based upon stored resume information and/or the lack of stored resume information. In response to determining to
20 restore the SE environment 200, the operating system 208 performs various operations. For example, the operating system 208 may load, authenticate, and initiate execution of AC modules that configure the computing device 100 and/or verify the configuration of the computing device 100. Further, the operating system 208 in block 406 may load and invoke execution of the monitor 202
25 identified by the resume information.
[0047] In block 408, the monitor 202 may unseal the sealed resume objects to obtain the contents attestation, the data structure attestation, and the monitor keys 214 via one or more unseal operations of the token 110. In response to detecting that the unseal operation failed (block 410), the monitor 202 in block 412 invokes
30 a sleep attack response to address a probable sleep attack. In one embodiment, the monitor 202 invokes the sleep attack response by writing to a reset register of the chipset 104 to invoke a system reset. However, the monitor 202 may respond in other ways such as, for example, halting the processors 102, erasing system memory 108, invoking a system shutdown, removing power from the computing device 100, and/or other actions that protect the secrets from unauthorized access 5 and/or alteration.
[0048] In block 414, the monitor 202 verifies the authenticity of the data structure base upon the data structure attestation. In one embodiment, the monitor 202 hashes the data structure to obtain a computed data structure attestation. The monitor 202 further compares the computed data structure
10 attestation to the data structure attestation obtained from the sealed resume objects and determines that the data structure is authentic in response to the computed attestation having a predetermined relationship (e.g. equal) to the unsealed attestation. In response to determining that the data structure may not be authentic and by be altered, the monitor 202 in block 412 invokes a sleep
15 attack response to address the probable sleep attack.
[0049] The monitor 202 in block 416 may decrypt portions of system memory
108 and store the decrypted portions in SE memory 122. The monitor 202 may decrypt the portions of the system memory 108 identified by the data structure using one or more unsealed monitor keys 214. In block 418, the monitor 202 may
20 verify the authenticity of the encrypted or decrypted SE memory contents. In one embodiment, the monitor 202 may hash the decrypted contents added to the SE memory 122 to obtain a computed contents attestation. In another embodiment, the monitor 202 may hash the encrypted contents to be added to the SE memory 122 to obtain a computed contents attestation. The monitor 202 may further
25 compare the computed contents attestation to the unsealed contents attestation and may determine that the contents are authentic (e.g. unaltered) in response to the computed attestation having a predetermined relationship (e.g. equal) to the unsealed attestation. In response to determining that the contents are not authentic (e.g. altered), the monitor 202 in block 412 may invoke an attack
30 response to the probable sleep attack. Conversely, in response to determining that the contents are authentic, the monitor 202 completes the wake process by invoking execution of the operating system 208.
[0050] The above embodiments of the sleep and wake methods help protect secrets from attack. However, an attacker may attempt to circumvent the sleeping 5 method of FIG. 3 to place the computing device 100 in a sleep state in which unencrypted secrets reside in system memory 108 and/or non-volatile storage 114 unprotected. To protect against such circumvention, the sleep attack detection logic 136 may invoke a system reset event or another attack response in response to detecting a probable sleep attack. In one embodiment of the sleep
10 method of FIG. 3, the monitor 202 updates the secrets store 126 to indicate that the system memory 108 contains no unencrypted secrets prior to updating the sleep enable store 134 to initiate the sleep entry process. Accordingly, the sleep attack detection logic 136 may invoke a sleep attack response in response to the sleep enable store 134 being updated if the secrets store 420 indicates that the
15 system memory 108 might contain unencrypted secrets.
[0051] In another embodiment of the sleep method of FIG. 3, the monitor 202 encrypts the SE memory 122 and updates the secrets store 126 to indicate that the system memory 108 contains no unencrypted secrets only if the requested sleep state would result in the SE memory 122 being unprotected. Accordingly,
20 sleep attack detection logic 136 may invoke a sleep attack response in response to the sleep enable store 134 being updated if the secrets store 420 indicates that the system memory 108 might contain unencrypted secrets and the sleep type store 132 indicates a sleep state in which the SE memory 122 map be unprotected.
[8052] While certain features of the invention have been described with reference to example embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the example embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit
30 and scope of the invention.

Claims

What is claimed is:
1. A method comprising
detecting a probable sleep attack, and
invoking a sleep attack response that protects secrets from the probable sleep attack.
2. The method of claim 1 further comprising
determining whether a memory might contain secrets; and
invoking the sleep attack response in response to determining that the memory might contain secrets.
3. The method of claim 1 further comprising
determining whether a memory might contain secrets in response to a sleep event; and
invoking the sleep attack response in response to determining that the memory might contain secrets.
4. The method of claim 1 further comprising
encrypting one or more portions of a memory in response to a sleep event.
5. The method of claim 4 further comprising
generating a contents attestation that attests to the one or more portions of the memory.
6. The method of claim 4 further comprising generating a structure that identifies the one or more portions of the memory; and
generating one or more attestations that attest to the structure and the one or more portions of the memory.
7. The method of claim 6 further comprising
sealing the structure and the one or more attestations to a monitor of a computing device.
8. The method of claim 1 further comprising
generating a system reset in response to invoking the sleep attack response.
9. A chipset comprising
sleep attack detection logic to detect a sleep attack and to invoke an attack response in response to a detected sleep attack.
10. The chipset of claim 9 further comprising a secrets store to indicate whether a memory might contain secrets,
the sleep attack detection logic to detect a sleep attack based upon the secrets store.
11. The chipset of claim 10 further comprising a sleep enable store to invoke a sleep entry,
the sleep attack detection logic to detect a sleep attack based further upon the sleep enable store.
12. The chipset of claim 11 further comprising a sleep type store to indicate a requested sleep state, the sleep attack detection logic to detect a sleep attack based further upon the sleep type store.
13. The chipset of claim 11 further comprising an interface that prevents untrusted modification of the secrets store.
14. The chipset of claim 11 further comprising an interface that requires receipt of one or more messages prior to allowing updates to the secrets store.
15. A system comprising an operating system and a more privileged monitor,
the operating system to receive a sleep event and to transfer processing of the sleep event to the monitor, and
the monitor, in response to the sleep request, to encrypt one or more pages of a memory and to indicate that the memory contains no unencrypted secrets.
16. The system of claim 15, wherein the monitor is to further update a secrets store to indicate that the memory contains no unencrypted secrets.
17. The system of claim 15, wherein
the monitor is to return processing of the sleep event to the operating system, and
the operating system is to write encrypted and non-encrypted pages of memory to non-volatile storage.
18. The system of claim 15, wherein
the monitor is to return processing of the sleep event to the operating system, and
the operating system is to cause the system to enter a sleep state.
19. The system of claim 18, wherein the operating system is to update a sleep type store to indicate the sleep state to be entered, and is to update a sleep enable store to invoke entry into the sleep state.
20. The system of claim 15, wherein the monitor is to further generate a contents attestation that attests to the encrypted pages of the memory.
21. The system of claim 20, wherein the monitor is to further generate a structure that identifies the encrypted pages, and is to generate a structure attestation that attests to the structure.
22. The system of claim 21 , wherein the monitor is to further seal to the monitor the contents attestation, the structure attestation, and a monitor key to decrypt the encrypted pages.
23. A system comprising
volatile memory comprising security enhanced regions,
a secrets store to indicate whether the volatile memory might contain unencrypted secrets,
a sleep enable store to invoke entry into a sleep state,
a processor to encrypt the security enhanced regions in response to a sleep event and to update the secrets store to indicate that the volatile memory contains no unencrypted secrets in response to encrypting the security enhanced regions, and
sleep attack detection logic to invoke a sleep attack response in response to the sleep enable store being updated to invoke entry into sleep state and the secrets store indicating that the volatile memory might contain unencrypted secrets.
24. The system of claim 23, wherein the processor is to further generate a contents attestation that attests to the security enhanced regions and is to invoke a sleep attack response in response to a wake event if the contents attestation indicates that the security enhanced regions are not authentic.
25. The system of claim 24, wherein the processor is to further seal the contents attestation and a key to decrypt the security enhanced regions to the system.
26. The system of claim 25, wherein the processor is to further invoke a sleep attack response in response to a wake event if unsealing the contents attestation and the key fails.
27. A machine-readable medium comprising a plurality of instructions that in response to being executed, result in a system
encrypting contents of a memory in response to a sleep event, and
generating a contents attestation that attests to the contents of the memory.
28. The machine-readable medium of claim 27 wherein the plurality of instructions in response to being executed further result in the system
using the contents attestation to verify the authenticity of the contents in response to a wake event, and
invoking a sleep attack response in response to determining that the contents of the memory are not authentic.
29. The machine-readable medium of claim 28 wherein the plurality of instructions in response to being executed further result in the system
sealing the contents attestation and a key to decrypt the contents of the memory to the system in response to a sleep event,
unsealing the contents attestation and the key in response to a wake event, and invoking a sleep attack response in response to a failure in unsealing the contents attestation and the key.
PCT/US2003/019597 2002-06-26 2003-06-20 Sleep attack protection WO2004003711A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020047020945A KR100692348B1 (en) 2002-06-26 2003-06-20 Sleep protection
JP2004517729A JP4660188B2 (en) 2002-06-26 2003-06-20 Protection from attacks in sleep
AU2003247595A AU2003247595A1 (en) 2002-06-26 2003-06-20 Sleep attack protection
EP03761974A EP1516239A2 (en) 2002-06-26 2003-06-20 Sleep protection

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/185,887 US7392415B2 (en) 2002-06-26 2002-06-26 Sleep protection
US10/185,887 2002-06-26

Publications (2)

Publication Number Publication Date
WO2004003711A2 true WO2004003711A2 (en) 2004-01-08
WO2004003711A3 WO2004003711A3 (en) 2004-03-25

Family

ID=29779758

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/019597 WO2004003711A2 (en) 2002-06-26 2003-06-20 Sleep attack protection

Country Status (8)

Country Link
US (1) US7392415B2 (en)
EP (1) EP1516239A2 (en)
JP (1) JP4660188B2 (en)
KR (3) KR20070011623A (en)
CN (1) CN100449558C (en)
AU (1) AU2003247595A1 (en)
TW (1) TWI245182B (en)
WO (1) WO2004003711A2 (en)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7174457B1 (en) * 1999-03-10 2007-02-06 Microsoft Corporation System and method for authenticating an operating system to a central processing unit, providing the CPU/OS with secure storage, and authenticating the CPU/OS to a third party
US7194092B1 (en) * 1998-10-26 2007-03-20 Microsoft Corporation Key-based secure storage
US7476925B2 (en) * 2001-08-30 2009-01-13 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
JP2003218724A (en) * 2002-01-18 2003-07-31 Nec Compound Semiconductor Devices Ltd Semiconductor device
US7890771B2 (en) * 2002-04-17 2011-02-15 Microsoft Corporation Saving and retrieving data based on public key encryption
US7487365B2 (en) * 2002-04-17 2009-02-03 Microsoft Corporation Saving and retrieving data based on symmetric key encryption
US7171663B2 (en) * 2002-12-09 2007-01-30 International Business Machines Corporation External event interrupt for server-side programs
US20050044408A1 (en) * 2003-08-18 2005-02-24 Bajikar Sundeep M. Low pin count docking architecture for a trusted platform
US7210009B2 (en) * 2003-09-04 2007-04-24 Advanced Micro Devices, Inc. Computer system employing a trusted execution environment including a memory controller configured to clear memory
US20050204155A1 (en) * 2004-03-09 2005-09-15 Nec Laboratories America, Inc Tamper resistant secure architecture
EP1870814B1 (en) * 2006-06-19 2014-08-13 Texas Instruments France Method and apparatus for secure demand paging for processor devices
US8639946B2 (en) * 2005-06-24 2014-01-28 Sigmatel, Inc. System and method of using a protected non-volatile memory
US8959339B2 (en) 2005-12-23 2015-02-17 Texas Instruments Incorporated Method and system for preventing unauthorized processor mode switches
GB2446658B (en) * 2007-02-19 2011-06-08 Advanced Risc Mach Ltd Hibernating a processing apparatus for processing secure data
US7945786B2 (en) * 2007-03-30 2011-05-17 Intel Corporation Method and apparatus to re-create trust model after sleep state
US7991932B1 (en) 2007-04-13 2011-08-02 Hewlett-Packard Development Company, L.P. Firmware and/or a chipset determination of state of computer system to set chipset mode
US8429085B2 (en) * 2007-06-22 2013-04-23 Visa U.S.A. Inc. Financial transaction token with onboard power source
US9324071B2 (en) 2008-03-20 2016-04-26 Visa U.S.A. Inc. Powering financial transaction token with onboard power source
US8117642B2 (en) * 2008-03-21 2012-02-14 Freescale Semiconductor, Inc. Computing device with entry authentication into trusted execution environment and method therefor
CN101562871B (en) * 2008-04-18 2011-09-28 鸿富锦精密工业(深圳)有限公司 Mobile station and method for preventing attack
US8291415B2 (en) * 2008-12-31 2012-10-16 Intel Corporation Paging instruction for a virtualization engine to local storage
WO2010110780A1 (en) * 2009-03-23 2010-09-30 Hewlett-Packard Development Company, L.P. System and method for securely storing data in an electronic device
JP5493951B2 (en) * 2009-04-17 2014-05-14 株式会社リコー Information processing apparatus, validity verification method, and program
GB2482811B (en) * 2009-12-16 2017-07-05 Intel Corp Providing integrity verification and attestation in a hidden execution environment
US8510569B2 (en) * 2009-12-16 2013-08-13 Intel Corporation Providing integrity verification and attestation in a hidden execution environment
WO2011119169A1 (en) 2010-03-26 2011-09-29 Hewlett-Packard Development Company, L.P. Storage device access authentication upon resuming from a standby mode of a computing device
US8943329B2 (en) * 2010-03-29 2015-01-27 Lenovo (Singapore) Pte. Ltd. Method and apparatus for sharing an integrity security module in a dual-environment computing device
US20130166869A1 (en) * 2010-09-10 2013-06-27 Hewlett-Packard Development Company, L.P. Unlock a storage device
US8503674B2 (en) 2011-04-28 2013-08-06 Microsoft Corporation Cryptographic key attack mitigation
KR101414932B1 (en) * 2011-12-30 2014-07-04 에스케이씨앤씨 주식회사 System and method for controlling access to applet
WO2013100636A1 (en) 2011-12-30 2013-07-04 에스케이씨앤씨 주식회사 Master tsm
US10013041B2 (en) 2012-02-20 2018-07-03 Intel Corporation Directed wakeup into a secured system environment
DE112012006454T5 (en) 2012-05-29 2015-02-26 Hewlett-Packard Development Company, L.P. Hibernation based on page source code
US9811475B2 (en) * 2012-06-29 2017-11-07 Intel Corporation Methods and apparatus for a secure sleep state
JP6026666B2 (en) 2012-09-14 2016-11-16 インテル・コーポレーション Method, apparatus, program, and computer-readable storage medium
JP6095330B2 (en) * 2012-11-13 2017-03-15 キヤノン株式会社 Information processing apparatus, control method therefor, and program
US9378342B2 (en) 2013-11-08 2016-06-28 Dell Products L.P. Context analysis at an information handling system to manage authentication cycles
US9235729B2 (en) * 2013-11-08 2016-01-12 Dell Products L.P. Context analysis at an information handling system to manage authentication cycles
KR101442539B1 (en) * 2013-12-31 2014-09-26 권용구 Storage system having security storage device and managing method thereof
KR101416547B1 (en) * 2014-02-20 2014-07-09 (주)지란지교소프트 Method for automatic encryption and decryption of important file
US10032029B2 (en) * 2014-07-14 2018-07-24 Lenovo (Singapore) Pte. Ltd. Verifying integrity of backup file in a multiple operating system environment
US9430407B2 (en) 2014-10-31 2016-08-30 Qualcomm Incorporated Method and system for secure storage and retrieval of machine state
US9910475B2 (en) * 2014-12-23 2018-03-06 Intel Corporation Processor core power event tracing
CN105847221B (en) * 2015-01-14 2019-10-11 宇龙计算机通信科技(深圳)有限公司 A kind of management method of security information, device and terminal
US10198274B2 (en) * 2015-03-27 2019-02-05 Intel Corporation Technologies for improved hybrid sleep power management
US10152599B2 (en) * 2015-12-18 2018-12-11 Intel IP Corporation Security mechanisms for extreme deep sleep state
WO2017155516A1 (en) * 2016-03-08 2017-09-14 Hewlett-Packard Development Company, L.P. Securing data
JP6316370B2 (en) * 2016-10-12 2018-04-25 インテル・コーポレーション Apparatus, method, integrated circuit, program, and tangible computer-readable storage medium
GB201700367D0 (en) * 2017-01-10 2017-02-22 Trustonic Ltd A system for recording and attesting device lifecycle
US10810297B2 (en) 2017-05-02 2020-10-20 Dell Products L.P. Information handling system multi-touch security system
US10586029B2 (en) 2017-05-02 2020-03-10 Dell Products L.P. Information handling system multi-security system management
CN111066374B (en) * 2017-07-18 2023-08-15 惠普发展公司,有限责任合伙企业 System and method for device management
US10503898B2 (en) * 2017-10-03 2019-12-10 Grand Mate Co., Ltd. Method for defending against malware
JP6494143B2 (en) * 2018-03-27 2019-04-03 インテル・コーポレーション Apparatus, method, integrated circuit, program, and tangible computer-readable storage medium
TWI783410B (en) * 2021-03-16 2022-11-11 瑞昱半導體股份有限公司 Electronic device and hibernation recovery method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0965902A2 (en) * 1994-06-28 1999-12-22 National Semiconductor Corporation Secure data processor with cryptography and tamper detection
US6188257B1 (en) * 1999-02-01 2001-02-13 Vlsi Technology, Inc. Power-on-reset logic with secure power down capability
EP1085396A1 (en) * 1999-09-17 2001-03-21 Hewlett-Packard Company Operation of trusted state in computing platform
US6275933B1 (en) * 1999-04-30 2001-08-14 3Com Corporation Security system for a computerized apparatus
WO2001063994A2 (en) * 2000-02-23 2001-08-30 Iridian Technologies, Inc. Tamper proof case for electronic devices having memories with sensitive information
EP1271277A2 (en) * 2001-06-26 2003-01-02 Redstrike B.V. Security system and software to prevent unauthorized use of a computing device

Family Cites Families (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699532A (en) 1970-04-21 1972-10-17 Singer Co Multiprogramming control for a data handling system
US3996449A (en) 1975-08-25 1976-12-07 International Business Machines Corporation Operating system authenticator
US4162536A (en) 1976-01-02 1979-07-24 Gould Inc., Modicon Div. Digital input/output system and method
US4037214A (en) 1976-04-30 1977-07-19 International Business Machines Corporation Key register controlled accessing system
US4247905A (en) 1977-08-26 1981-01-27 Sharp Kabushiki Kaisha Memory clear system
US4278837A (en) 1977-10-31 1981-07-14 Best Robert M Crypto microprocessor for executing enciphered programs
US4276594A (en) 1978-01-27 1981-06-30 Gould Inc. Modicon Division Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same
US4207609A (en) 1978-05-08 1980-06-10 International Business Machines Corporation Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system
JPS5823570B2 (en) 1978-11-30 1983-05-16 国産電機株式会社 Liquid level detection device
JPS5576447A (en) 1978-12-01 1980-06-09 Fujitsu Ltd Address control system for software simulation
US4307447A (en) 1979-06-19 1981-12-22 Gould Inc. Programmable controller
US4307214A (en) * 1979-12-12 1981-12-22 Phillips Petroleum Company SC2 activation of supported chromium oxide catalysts
US4319323A (en) 1980-04-04 1982-03-09 Digital Equipment Corporation Communications device for data processing system
US4419724A (en) 1980-04-14 1983-12-06 Sperry Corporation Main bus interface package
US4366537A (en) 1980-05-23 1982-12-28 International Business Machines Corp. Authorization mechanism for transfer of program control or data between different address spaces having different storage protect keys
US4403283A (en) 1980-07-28 1983-09-06 Ncr Corporation Extended memory system and method
DE3034581A1 (en) 1980-09-13 1982-04-22 Robert Bosch Gmbh, 7000 Stuttgart READ-OUT LOCK FOR ONE-CHIP MICROPROCESSORS
US4521852A (en) 1982-06-30 1985-06-04 Texas Instruments Incorporated Data processing device formed on a single semiconductor substrate having secure memory
JPS59111561A (en) 1982-12-17 1984-06-27 Hitachi Ltd Access controlling system of composite processor system
US4759064A (en) 1985-10-07 1988-07-19 Chaum David L Blind unanticipated signature systems
US4975836A (en) 1984-12-19 1990-12-04 Hitachi, Ltd. Virtual computer system
JPS61206057A (en) 1985-03-11 1986-09-12 Hitachi Ltd Address converting device
FR2601525B1 (en) 1986-07-11 1988-10-21 Bull Cp8 SECURITY DEVICE PROHIBITING THE OPERATION OF AN ELECTRONIC ASSEMBLY AFTER A FIRST SHUTDOWN OF ITS POWER SUPPLY
US5007082A (en) 1988-08-03 1991-04-09 Kelly Services, Inc. Computer software encryption apparatus
US5079737A (en) 1988-10-25 1992-01-07 United Technologies Corporation Memory management unit for the MIL-STD 1750 bus
JPH02171934A (en) 1988-12-26 1990-07-03 Hitachi Ltd Virtual machine system
JPH02208740A (en) 1989-02-09 1990-08-20 Fujitsu Ltd Virtual computer control system
JP2590267B2 (en) 1989-06-30 1997-03-12 株式会社日立製作所 Display control method in virtual machine
US5022077A (en) 1989-08-25 1991-06-04 International Business Machines Corp. Apparatus and method for preventing unauthorized access to BIOS in a personal computer system
JP2825550B2 (en) 1989-09-21 1998-11-18 株式会社日立製作所 Multiple virtual space address control method and computer system
CA2010591C (en) 1989-10-20 1999-01-26 Phillip M. Adams Kernels, description tables and device drivers
CA2027799A1 (en) 1989-11-03 1991-05-04 David A. Miller Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
US5075842A (en) 1989-12-22 1991-12-24 Intel Corporation Disabling tag bit recognition and allowing privileged operations to occur in an object-oriented memory protection mechanism
US5108590A (en) 1990-09-12 1992-04-28 Disanto Dennis Water dispenser
US5230069A (en) 1990-10-02 1993-07-20 International Business Machines Corporation Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system
US5317705A (en) 1990-10-24 1994-05-31 International Business Machines Corporation Apparatus and method for TLB purge reduction in a multi-level machine system
US5287363A (en) 1991-07-01 1994-02-15 Disk Technician Corporation System for locating and anticipating data storage media failures
US5437033A (en) 1990-11-16 1995-07-25 Hitachi, Ltd. System for recovery from a virtual machine monitor failure with a continuous guest dispatched to a nonguest mode
US5255379A (en) 1990-12-28 1993-10-19 Sun Microsystems, Inc. Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 80486 processor
US5319760A (en) 1991-06-28 1994-06-07 Digital Equipment Corporation Translation buffer for virtual machines with address space match
US5522075A (en) 1991-06-28 1996-05-28 Digital Equipment Corporation Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces
US5455909A (en) 1991-07-05 1995-10-03 Chips And Technologies Inc. Microprocessor with operation capture facility
JPH06236284A (en) 1991-10-21 1994-08-23 Intel Corp Method for preservation and restoration of computer-system processing state and computer system
US5627987A (en) 1991-11-29 1997-05-06 Kabushiki Kaisha Toshiba Memory management and protection system for virtual memory in computer system
US5574936A (en) 1992-01-02 1996-11-12 Amdahl Corporation Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system
US5421006A (en) 1992-05-07 1995-05-30 Compaq Computer Corp. Method and apparatus for assessing integrity of computer system software
US5237616A (en) 1992-09-21 1993-08-17 International Business Machines Corporation Secure computer system having privileged and unprivileged memories
US5293424A (en) 1992-10-14 1994-03-08 Bull Hn Information Systems Inc. Secure memory card
JP2765411B2 (en) 1992-11-30 1998-06-18 株式会社日立製作所 Virtual computer system
US5668971A (en) 1992-12-01 1997-09-16 Compaq Computer Corporation Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer
JPH06187178A (en) 1992-12-18 1994-07-08 Hitachi Ltd Input and output interruption control method for virtual computer system
US5483656A (en) 1993-01-14 1996-01-09 Apple Computer, Inc. System for managing power consumption of devices coupled to a common bus
US5469557A (en) 1993-03-05 1995-11-21 Microchip Technology Incorporated Code protection in microcontroller with EEPROM fuses
FR2703800B1 (en) 1993-04-06 1995-05-24 Bull Cp8 Method for signing a computer file, and device for implementing it.
JPH06348867A (en) 1993-06-04 1994-12-22 Hitachi Ltd Microcomputer
US5555385A (en) 1993-10-27 1996-09-10 International Business Machines Corporation Allocation of address spaces within virtual machine compute system
US5825880A (en) 1994-01-13 1998-10-20 Sudia; Frank W. Multi-step digital signature method and system
US5459869A (en) 1994-02-17 1995-10-17 Spilo; Michael L. Method for providing protected mode services for device drivers and other resident software
US5604805A (en) 1994-02-28 1997-02-18 Brands; Stefanus A. Privacy-protected transfer of electronic information
US5684881A (en) 1994-05-23 1997-11-04 Matsushita Electric Industrial Co., Ltd. Sound field and sound image control apparatus and method
US5473692A (en) 1994-09-07 1995-12-05 Intel Corporation Roving software license for a hardware agent
US5539828A (en) 1994-05-31 1996-07-23 Intel Corporation Apparatus and method for providing secured communications
US5978481A (en) 1994-08-16 1999-11-02 Intel Corporation Modem compatible method and apparatus for encrypting data that is transparent to software applications
JPH0883211A (en) 1994-09-12 1996-03-26 Mitsubishi Electric Corp Data processor
DE69534757T2 (en) 1994-09-15 2006-08-31 International Business Machines Corp. System and method for secure storage and distribution of data using digital signatures
US6058478A (en) 1994-09-30 2000-05-02 Intel Corporation Apparatus and method for a vetted field upgrade
US5606617A (en) 1994-10-14 1997-02-25 Brands; Stefanus A. Secret-key certificates
US5564040A (en) 1994-11-08 1996-10-08 International Business Machines Corporation Method and apparatus for providing a server function in a logically partitioned hardware machine
US5560013A (en) 1994-12-06 1996-09-24 International Business Machines Corporation Method of using a target processor to execute programs of a source architecture that uses multiple address spaces
US5555414A (en) 1994-12-14 1996-09-10 International Business Machines Corporation Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals
US5615263A (en) 1995-01-06 1997-03-25 Vlsi Technology, Inc. Dual purpose security architecture with protected internal operating system
US5764969A (en) 1995-02-10 1998-06-09 International Business Machines Corporation Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization
US5717903A (en) 1995-05-15 1998-02-10 Compaq Computer Corporation Method and appartus for emulating a peripheral device to allow device driver development before availability of the peripheral device
JP3451595B2 (en) 1995-06-07 2003-09-29 インターナショナル・ビジネス・マシーンズ・コーポレーション Microprocessor with architectural mode control capable of supporting extension to two distinct instruction set architectures
US5684948A (en) 1995-09-01 1997-11-04 National Semiconductor Corporation Memory management circuit which provides simulated privilege levels
US5633929A (en) 1995-09-15 1997-05-27 Rsa Data Security, Inc Cryptographic key escrow system having reduced vulnerability to harvesting attacks
US5737760A (en) 1995-10-06 1998-04-07 Motorola Inc. Microcontroller with security logic circuit which prevents reading of internal memory by external program
JP3693721B2 (en) 1995-11-10 2005-09-07 Necエレクトロニクス株式会社 Microcomputer with built-in flash memory and test method thereof
JPH09204360A (en) * 1996-01-24 1997-08-05 Toshiba Corp Method for protecting confidential data
US5657445A (en) 1996-01-26 1997-08-12 Dell Usa, L.P. Apparatus and method for limiting access to mass storage devices in a computer system
US5835594A (en) 1996-02-09 1998-11-10 Intel Corporation Methods and apparatus for preventing unauthorized write access to a protected non-volatile storage
US5809546A (en) 1996-05-23 1998-09-15 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for controlling accesses to the buffers
US5729760A (en) 1996-06-21 1998-03-17 Intel Corporation System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode
KR200144911Y1 (en) * 1996-06-28 1999-06-15 양재신 Simulated Collision Testing Device
US5740178A (en) 1996-08-29 1998-04-14 Lucent Technologies Inc. Software for controlling a reliable backup memory
US6055637A (en) 1996-09-27 2000-04-25 Electronic Data Systems Corporation System and method for accessing enterprise-wide resources by presenting to the resource a temporary credential
US5937063A (en) 1996-09-30 1999-08-10 Intel Corporation Secure boot
US5844986A (en) 1996-09-30 1998-12-01 Intel Corporation Secure BIOS
US5935242A (en) 1996-10-28 1999-08-10 Sun Microsystems, Inc. Method and apparatus for initializing a device
JPH10134008A (en) * 1996-11-05 1998-05-22 Mitsubishi Electric Corp Semiconductor device and computer system
US5852717A (en) 1996-11-20 1998-12-22 Shiva Corporation Performance optimizations for computer networks utilizing HTTP
US5901225A (en) 1996-12-05 1999-05-04 Advanced Micro Devices, Inc. System and method for performing software patches in embedded systems
US5757919A (en) 1996-12-12 1998-05-26 Intel Corporation Cryptographically protected paging subsystem
US5953502A (en) 1997-02-13 1999-09-14 Helbig, Sr.; Walter A Method and apparatus for enhancing computer system security
US6044478A (en) 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US5987557A (en) 1997-06-19 1999-11-16 Sun Microsystems, Inc. Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU)
US6035374A (en) 1997-06-25 2000-03-07 Sun Microsystems, Inc. Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US6014745A (en) 1997-07-17 2000-01-11 Silicon Systems Design Ltd. Protection for customer programs (EPROM)
US5978475A (en) 1997-07-18 1999-11-02 Counterpane Internet Security, Inc. Event auditing system
US5919257A (en) 1997-08-08 1999-07-06 Novell, Inc. Networked workstation intrusion detection system
US6233685B1 (en) * 1997-08-29 2001-05-15 Sean William Smith Establishing and employing the provable untampered state of a device
US5935247A (en) 1997-09-18 1999-08-10 Geneticware Co., Ltd. Computer system having a genetic code that cannot be directly accessed and a method of maintaining the same
US5970147A (en) 1997-09-30 1999-10-19 Intel Corporation System and method for configuring and registering a cryptographic device
JP2001202167A (en) * 2000-01-20 2001-07-27 Toyo Commun Equip Co Ltd Computer and its control method
US6983374B2 (en) * 2000-02-14 2006-01-03 Kabushiki Kaisha Toshiba Tamper resistant microprocessor
US20020120843A1 (en) * 2001-02-21 2002-08-29 Goodman Steven Dale Method and system for preventing reset of a cryptographic subsystem when entering or recovering from a powered-off sleep state

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0965902A2 (en) * 1994-06-28 1999-12-22 National Semiconductor Corporation Secure data processor with cryptography and tamper detection
US6188257B1 (en) * 1999-02-01 2001-02-13 Vlsi Technology, Inc. Power-on-reset logic with secure power down capability
US6275933B1 (en) * 1999-04-30 2001-08-14 3Com Corporation Security system for a computerized apparatus
EP1085396A1 (en) * 1999-09-17 2001-03-21 Hewlett-Packard Company Operation of trusted state in computing platform
WO2001063994A2 (en) * 2000-02-23 2001-08-30 Iridian Technologies, Inc. Tamper proof case for electronic devices having memories with sensitive information
EP1271277A2 (en) * 2001-06-26 2003-01-02 Redstrike B.V. Security system and software to prevent unauthorized use of a computing device

Also Published As

Publication number Publication date
CN100449558C (en) 2009-01-07
KR20050008847A (en) 2005-01-21
KR100823374B1 (en) 2008-04-17
AU2003247595A1 (en) 2004-01-19
JP2005531086A (en) 2005-10-13
US20040003273A1 (en) 2004-01-01
US7392415B2 (en) 2008-06-24
KR100692348B1 (en) 2007-03-09
AU2003247595A8 (en) 2004-01-19
CN1662869A (en) 2005-08-31
TW200405963A (en) 2004-04-16
KR20070011623A (en) 2007-01-24
WO2004003711A3 (en) 2004-03-25
KR20070014208A (en) 2007-01-31
EP1516239A2 (en) 2005-03-23
JP4660188B2 (en) 2011-03-30
TWI245182B (en) 2005-12-11

Similar Documents

Publication Publication Date Title
US7392415B2 (en) Sleep protection
KR101735023B1 (en) Method and apparatus including architecture for protecting sensitive code and data
US6581162B1 (en) Method for securely creating, storing and using encryption keys in a computer system
JP4982825B2 (en) Computer and shared password management methods
US8332635B2 (en) Updateable secure kernel extensions
JP5249399B2 (en) Method and apparatus for secure execution using secure memory partition
JP4498735B2 (en) Secure machine platform that interfaces with operating system and customized control programs
JP4822646B2 (en) Generating a key hierarchy for use in an isolated execution environment
US7313705B2 (en) Implementation of a secure computing environment by using a secure bootloader, shadow memory, and protected memory
TWI471754B (en) Support for secure objects in a computer system
KR100871181B1 (en) Protection against memory attacks following reset
Blass et al. TRESOR-HUNT: attacking CPU-bound encryption
KR101081118B1 (en) System and method for securely restoring a program context from a shared memory
KR101054981B1 (en) Computer-implemented methods, information processing systems, and computer-readable recording media for securely storing the context of a program
WO2016073411A2 (en) System and method for a renewable secure boot
KR20040094724A (en) Multi-token seal and unseal
WO1998015086A1 (en) Secure boot
US9015454B2 (en) Binding data to computers using cryptographic co-processor and machine-specific and platform-specific keys
JP5316592B2 (en) Secure processor program
KR20080090253A (en) Wireless telephone apparatus and method for protecting system resources
JP5365664B2 (en) Secure processor
JP2004272816A (en) System and method for performing multitask
Lie et al. Using hypervisors to secure commodity operating systems
Bove Secure Services for Standard RISC-V Architectures
JP2009301566A (en) Secure processor and program for the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003761974

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020047020945

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2004517729

Country of ref document: JP

Ref document number: 20038148323

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 1020047020945

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2003761974

Country of ref document: EP