WO2001020453A1 - Method and apparatus for modifying microinstructions in a static memory device - Google Patents
Method and apparatus for modifying microinstructions in a static memory device Download PDFInfo
- Publication number
- WO2001020453A1 WO2001020453A1 PCT/US2000/025474 US0025474W WO0120453A1 WO 2001020453 A1 WO2001020453 A1 WO 2001020453A1 US 0025474 W US0025474 W US 0025474W WO 0120453 A1 WO0120453 A1 WO 0120453A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory device
- jump point
- address
- microinstructions
- microinstruction
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/66—Updates of program code stored in read-only memory [ROM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
Definitions
- the present invention relates to the field of control stores for microprocessors. More particularly, the invention relates to the modification of a control store apparatus that utilizes both a Read-Only Memory (ROM) and a Random Access Memory (RAM).
- ROM Read-Only Memory
- RAM Random Access Memory
- Control stores contain executable microinstructions that control the data path of a microprocessor.
- the control store consists of RAM, in others, the control store is ROM.
- the contents of a RAM can easily be rewritten with new information.
- RAM is volatile, i.e., the contents of RAM are retained only during the time period when power is supplied to the circuit.
- the contents of a ROM are inserted at the time of the ROM's manufacture and cannot be changed or erased, even when powered off.
- ROM is much cheaper than RAM when produced in large volumes. Due to cost considerations of RAM and ROM, microcode programmers generally design new circuitry with RAM so that programming mistakes can be easily corrected, but substitute RAM with ROM in the final design stage to minimize production costs. However, even the most rigorous design review can miss programming errors that will then be permanently embedded in the static ROM. When programming mistakes are discovered in the microinstruction set stored in ROM, programmers create patches to correct the mistakes. "Patch" is a term of art that refers to new code introduced to fix prior code or to add functionality. Microinstructions as a whole are referred to as "code” and designed in a modular manner, wherein the entire code consists of separate subroutines.
- an error in one portion of the code can be isolated and corrected without having to rewrite the entire code.
- a programmer will create a duplicate subroutine, without the errors, which is called by the program flow instead of the faulty subroutine.
- This technique is possible by utilizing system RAM and ROM together for storing the microinstruction set.
- Subroutines are generally stored in ROM, whereas the main program code that calls the subroutines is generally stored in RAM.
- exit points from the main code allow the program flow to execute the microinstructions of the subroutines in ROM.
- the present invention is directed to a method and apparatus for modifying the program flow of microinstructions residing in a ROM in order for programmers to have more direct access and control over the ROM microinstructions. Since the microinstructions in ROM cannot be altered, any changes to the microinstruction set must necessarily be made in RAM.
- the present invention allows a programmer to directly access a programming error within ROM without having to duplicate the entire subroutine in RAM.
- the present invention can also allow a programmer to add functionality to outdated ROM rather than replacing the outdated ROM with a newly designed ROM.
- the exemplary embodiment of the present invention is a method for modifying the program flow in a static memory device, the method comprising the step of generating an interrupt that triggers a jump from the static memory device to a programmable memory device.
- a jump point register is used to hold a jump point address. This jump point address can trigger an interrupt event in the program flow.
- a program counter contains the address of the current microinstruction in the program flow. If the program counter holds an address that equals the jump point address in the jump point register, the interrupt event is generated. This interrupt event initiates an alteration in the program flow from a static memory device to a programmable memory device.
- the interrupt event can be used to repair programming errors in the static memory device.
- a programmer can create a patch for a defective portion of code residing in the static memory device.
- the programmer can then store an exit address in a register or other storage device wherein the exit address corresponds to an address of a predetermined microinstruction within the defective code portion.
- the exit address is compared to all the microinstructions being executed in the program flow.
- the microinstructions in the patch are executed when the predetermined microinstruction occurs in the program flow.
- the interrupt event can produce an alteration in the program flow that adds functionality to the static memory device.
- the alteration can be in the form of additional code stored in a programmable memory device, which can be executed in the midst of the execution of microcode from the static memory device.
- multiple jump point registers can be coupled to an interrupt port along with corresponding comparators, which can enable or disable each individual jump point register.
- Each individual jump point register can be associated with separate interrupt events.
- FIG. 1 is a diagram showing a conventional program flow between RAM and ROM.
- FIG. 2 is a diagram showing the program flow between RAM and ROM in an embodiment of the present invention.
- FIG. 3 is a block diagram of a circuit for implementing program flow between RAM and ROM.
- FIG. 4 is a block diagram of a data processing system.
- FIG. 1 is a block diagram showing a prior art implementation of an error correcting method, i.e., a "debugging" method, for microinstructions in a data processing system such as a computer system or a general purpose microcomputer.
- a data processing system such as a computer system or a general purpose microcomputer.
- ROM read only memory
- RAM random access memory
- FIG. 1 a RAM 100 has been programmed with code that calls subroutines in a ROM 110.
- a program counter (not shown) containing the address of the microinstruction next to be executed proceeds down the RAM stack until the program counter encounters the address of a microinstruction in the ROM stack.
- the program flow exits the microinstruction set in RAM 100 and enters the microinstruction set in ROM 110.
- the program counter proceeds down the ROM 110 until it encounters the address of a microinstruction in RAM 100.
- the program flow exits the microinstruction set in ROM 110 and reenters the microinstruction set in RAM 100 at point 102. This process repeats itself for the various subroutines stored in ROM 110. However, if a programming error needs be corrected in ROM 110, or a different functionality needs to be added, a programmer could reprogram the RAM 100 so that the subroutine stored in ROM 110 can be bypassed.
- the present practice among those skilled in the art is to debug faulty subroutines by duplicating the entire subroutine in RAM 100, absent programming errors, and reprogramming the RAM 100 to carry the program flow to the duplicated subroutine in RAM 100, rather than to the faulty subroutine stored in ROM 110.
- a programming error 106 is discovered in subroutine 105, then the programmer would have to disable the data path 103 from RAM 100 to ROM 110 and create a new data path 104 to a replacement subroutine 107 residing in RAM 100.
- the data path 108 flows back to any designated microinstruction located in RAM 100 after the disabled data path 103.
- FIG. 2 is a block diagram showing the program flow between RAM 200 and ROM 210 in an embodiment of the present invention that allows a programmer to debug a faulty subroutine stored in ROM 210 without having to replicate the entire subroutine in RAM 200.
- a programmer may include additional features and functions within the subroutines stored in ROM 210.
- the program flow exits RAM 200 and enters ROM 210 as in FIG. 1 during an error-free portion of the microcode.
- the program flow of FIG. 2 allows the programmer to create a patch for the bug without sacrificing a large portion of the RAM 200 in order to correct the bug.
- a program counter (not shown) proceeds down the RAM stack until the program counter encounters the address of a microinstruction in the ROM stack.
- the program flow exits the microinstruction set in RAM 200 and enters the microinstruction set in ROM 210.
- the program counter proceeds down the ROM 210 until it encounters the address of a microinstruction in RAM 200.
- the program flow exits the microinstruction set in ROM 210 and reenters the microinstruction set in RAM 200 at point 202. This process repeats itself for the various subroutines stored in ROM.
- FIG. 3 is a block diagram of an interrupt circuit that will allow a programmer to create a program flow as shown in FIG. 2.
- the interrupt circuit of FIG. 3 consists of a plurality of registers, or any other storage device capable of storing a microinstruction address, and are referred to generically as jump point registers.
- a jump point register holds a jump point address that triggers an interrupt event.
- an interrupt causes the temporary suspension of a process when an external event occurs outside of that process.
- An interrupt signal indicates the occurrence of an interrupt event so that the processor suspends the current process and performs the task requested by the interrupt signal.
- interrupt signals are used in a very different way. Rather than using the interrupt to indicate the occurrence of an external event, the interrupt circuit of FIG. 3 uses an interrupt to bypass portions of the microcode residing in ROM.
- the interrupt circuit embodied in FIG. 3 includes three (3) jump point registers 300, 310, 320.
- Each of the three (3) jump point registers is individually coupled to one of three comparators 308, 318, 328, respectively, through lines 303, 313, 323.
- a comparator is a device that compares two input words and is generally composed of EXCLUSIVE-OR gates, but for this or any other embodiment of the invention, any device that can accomplish a comparison function can be used. However, for illustrative purposes, the term "comparator" will be used.
- Each comparator 308, 318, 328 is coupled to the processor 320 through control lines 304, 305.
- Each jump point register 300, 310, 320 is set with an address corresponding to an interrupt event.
- Line 301 loads the addresses into each jump point register from the processor 320.
- Control line 304 carries the contents of the program counter to the comparators 308, 318, 328.
- the program counter is a register that contains the address of the microinstruction to be executed next. In some data processing systems, the program counter is designed to contain the current microinstruction being executed. It would be apparent to one skilled in the art that the contents of the program counter need not be limited to a predictive state or a current state in order to implement any embodiment of the invention.
- Control line 305 carries a control signal from the processor 320 that enables or disables each comparator 308, 318, 328, in order to achieve the desired functionality associated with each jump point register.
- Control line 306 carries a status signal from comparators 308, 318, 328 to status registers (not shown) in the processor 320, indicating which jump point register contained the same address as the program counter. Placement of the status registers in the processor 320 is merely a matter of design choice and does not effect the scope of the invention.
- the program counter could be used to identify which jump point register has the same address as the program counter. If a program counter is used, then all the bits in an address must be checked to identify the jump point register in question. If a status register is used, then only one bit need be checked. The choice of using the program counter or the status registers for the purpose of identifying which jump point register contains the jump point address associated with the current interrupt is merely a matter of design choice.
- the interrupt event is not an external event which calls for an suspension of the program flow, rather, the interrupt event redirects the program counter to a microinstruction stored in RAM.
- the program flow continues in RAM until redirected back to the ROM. Since RAM is dynamic, the RAM can redirect the program counter, hence, the program flow, to any microinstruction stored in ROM.
- a programmer can identify a bug in a portion of the microinstruction subroutine in ROM and store the address of the bug in a jump point register. If the bug is a minor error that can be fixed with just a few lines of code, a patch for the bug can easily be stored in RAM.
- the comparator When the program counter encounters the address of the bug, which has been stored in the jump point register, the comparator allows a signal to be sent to the interrupt controller, whereby an interrupt is generated which redirects the program flow to the patch stored in RAM.
- the RAM microinstruction immediately following the patch can redirect the program flow to the ROM microinstruction following the erroneous section of the subroutine. In this manner, a subroutine containing a small programming error can be corrected without having to duplicate the entire subroutine in RAM.
- a programmer can advantageously utilize the jump point registers to add further subroutines within the structure of already existing ROM subroutines.
- a programmer can insert a microinstruction address into a jump point register wherein the microinstruction is part of a program subroutine residing in ROM.
- the program counter contains the address of this microinstruction
- the program flow will jump to a corresponding set of microinstructions stored in RAM.
- the last instruction of the corresponding set of microinstructions will redirect the program flow back to the subroutine at whichever point the programmer desires.
- a programmer can add a new function to the ROM subroutine without replacing the old, programmed ROM.
- a ROM can be updated without having to be replaced by a reprogrammed ROM.
- the interrupt circuit of Fig. 3 is one embodiment of the invention where three (3) jump points and corresponding comparators are connected through a OR gate 330 to an interrupt request (IRQ) pin in a processor, i.e., the interrupt controller.
- IRQ interrupt request
- multiple interrupt circuits can be used in a data processing system in order to minimize the amount of checking for new code that will occur whenever an interrupt is triggered. When there is a large number of jump point registers within a single interrupt circuit, a large amount of MIPS is consumed to determine which new code corresponds to the interrupt that was just triggered.
- interrupt circuits each with only three or fewer jump point registers, and each connected to an individual IRQ pin, less MIPS are consumed in implementing the code corresponding to the triggered interrupt event.
- the use of multiple interrupt circuits or a single interrupt circuit is a matter of design choice according to the needs of the circuit board designer. However, any variation of the interrupt circuit as described herein falls within the scope of this invention.
- FIG. 4 is a block diagram showing a data processing system. It will be apparent to one skilled in the art that the present invention may be practiced without specific details as to well-known circuits and control logic. In order to avoid obscuring the description, such specific details have been omitted from FIG. 4.
- the block diagram of FIG. 4 is representative of a system wherein the control logic is segregated from the operation core.
- the system may be a digital signal processor or an application specific integrated circuit.
- the present invention can be used in data processing systems with other architectural forms, e.g., where the control logic is combined with the operation core.
- a program flow control device 400 is coupled to the control store RAM 430, the control store ROM 440, an interrupt circuit 450, and an instruction- decoding device 410.
- the interrupt circuit 450 may be the interrupt circuit of FIG. 3.
- the program flow control device 400 generates the contents of the program counter, generates the flags which show whether the current instruction has been executed or canceled, and handles all external events such as direct memory access (DMA) and interrupts.
- the instruction-decoding device 410 may or may not be integrated within the operation core 420 and is connected to the program flow control device 400 through line 405.
- the instruction-decoding device 410 is also connected to the control store RAM 430 and control store ROM 440 through line 404.
- the interrupt circuit 450 is coupled to the program flow control device 400, control store RAM 430, control store ROM 440, and the operation core 420.
- the program flow control device 400 generates the program counter based upon input from control store RAM 430, control store ROM 440 or the interrupt circuit 450.
- Lines RAM_CS 401, ROM_CS 403, and EXEC 412 are used by the program flow control device 400 to enable input from the control store RAM 430, control store ROM 440, or the interrupt circuit 450.
- Line 422 loads jump point addresses into the jump point registers (not shown) in the interrupt circuit 450.
- Line 402 carries the contents of the program counter to the control store RAM 430, control store ROM 440 and the interrupt circuit 450.
- interrupt circuit 450 When interrupt circuit 450 indicates that the current program counter contains an address equal to a jump point address contained in a jump point register (not shown), an interrupt is generated by an interrupt controller (not shown), which may or may not be integrated into the program flow control device 400. When the interrupt circuit 450 generates an interrupt, the program flow control device 400 resets the program counter to hold the address of the next microinstruction specified by the interrupt event.
- the data processing system of FIG. 4 is just one illustrative example of how an embodiment of the present invention may be used. It should be noted that the present invention may be realized using a variety of computer programming languages and hardware, and is not limited to any particular hardware and software configuration. For example, the functions of program flow control device 400, the instruction decoder 410, and the operation core 420 can be achieved through the use of a general-purpose processor, as illustrated in block 490.
- the present invention may be utilized in any embodiment which has code stored in a static storage device such as a ROM, a magnetic tape storage unit, a compact disk or a floppy disk.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001523963A JP2003509769A (en) | 1999-09-14 | 2000-09-14 | Method and apparatus for modifying microinstructions in static storage |
EP00963557A EP1221096A1 (en) | 1999-09-14 | 2000-09-14 | Method and apparatus for modifying microinstructions in a static memory device |
AU74953/00A AU7495300A (en) | 1999-09-14 | 2000-09-14 | Method and apparatus for modifying microinstructions in a static memory device |
KR1020027001886A KR20020029921A (en) | 1999-09-14 | 2000-09-14 | Method and apparatus for modifying microinstructions in a static memory device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39891299A | 1999-09-14 | 1999-09-14 | |
US09/398,912 | 1999-09-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001020453A1 true WO2001020453A1 (en) | 2001-03-22 |
Family
ID=23577324
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/025474 WO2001020453A1 (en) | 1999-09-14 | 2000-09-14 | Method and apparatus for modifying microinstructions in a static memory device |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1221096A1 (en) |
JP (1) | JP2003509769A (en) |
KR (1) | KR20020029921A (en) |
CN (1) | CN1373872A (en) |
AU (1) | AU7495300A (en) |
WO (1) | WO2001020453A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US7464248B2 (en) | 2005-04-25 | 2008-12-09 | Mediatek Incorporation | Microprocessor systems and bus address translation methods |
CN103268237A (en) * | 2013-05-10 | 2013-08-28 | 东信和平科技股份有限公司 | Patching function extension method and device for mask smart card |
CN106484369B (en) * | 2013-10-24 | 2019-11-29 | 华为技术有限公司 | A kind of method and device of online patch activation |
CN104156241B (en) * | 2014-07-31 | 2019-08-13 | 中国船舶重工集团公司第七0九研究所 | The initiated configuration method and system of processor microprogram |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051897A (en) * | 1988-03-11 | 1991-09-24 | Mitsubishi Denki Kabushiki Kaisha | Single-chip microcomputer with memory patching capability |
US5592613A (en) * | 1989-03-28 | 1997-01-07 | Olympus Optical Co., Ltd. | Microcomputer having a program correction function |
US5784537A (en) * | 1994-12-13 | 1998-07-21 | Olympus Optical Co., Ltd. | One-chip microcomputer capable of executing correction program and microcomputer capable of correcting ROM |
US5901225A (en) * | 1996-12-05 | 1999-05-04 | Advanced Micro Devices, Inc. | System and method for performing software patches in embedded systems |
-
2000
- 2000-09-14 WO PCT/US2000/025474 patent/WO2001020453A1/en not_active Application Discontinuation
- 2000-09-14 AU AU74953/00A patent/AU7495300A/en not_active Abandoned
- 2000-09-14 CN CN 00812750 patent/CN1373872A/en active Pending
- 2000-09-14 KR KR1020027001886A patent/KR20020029921A/en not_active Application Discontinuation
- 2000-09-14 JP JP2001523963A patent/JP2003509769A/en active Pending
- 2000-09-14 EP EP00963557A patent/EP1221096A1/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051897A (en) * | 1988-03-11 | 1991-09-24 | Mitsubishi Denki Kabushiki Kaisha | Single-chip microcomputer with memory patching capability |
US5592613A (en) * | 1989-03-28 | 1997-01-07 | Olympus Optical Co., Ltd. | Microcomputer having a program correction function |
US5784537A (en) * | 1994-12-13 | 1998-07-21 | Olympus Optical Co., Ltd. | One-chip microcomputer capable of executing correction program and microcomputer capable of correcting ROM |
US5901225A (en) * | 1996-12-05 | 1999-05-04 | Advanced Micro Devices, Inc. | System and method for performing software patches in embedded systems |
Also Published As
Publication number | Publication date |
---|---|
JP2003509769A (en) | 2003-03-11 |
EP1221096A1 (en) | 2002-07-10 |
CN1373872A (en) | 2002-10-09 |
AU7495300A (en) | 2001-04-17 |
KR20020029921A (en) | 2002-04-20 |
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