WO2001016761A3 - Efficient page allocation - Google Patents

Efficient page allocation Download PDF

Info

Publication number
WO2001016761A3
WO2001016761A3 PCT/US2000/024216 US0024216W WO0116761A3 WO 2001016761 A3 WO2001016761 A3 WO 2001016761A3 US 0024216 W US0024216 W US 0024216W WO 0116761 A3 WO0116761 A3 WO 0116761A3
Authority
WO
WIPO (PCT)
Prior art keywords
page allocation
systems
efficient page
writing
bit
Prior art date
Application number
PCT/US2000/024216
Other languages
French (fr)
Other versions
WO2001016761A2 (en
Inventor
Karlon K West
Chris Miller
Original Assignee
Times N Systems Inc
Karlon K West
Chris Miller
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Times N Systems Inc, Karlon K West, Chris Miller filed Critical Times N Systems Inc
Priority to AU71085/00A priority Critical patent/AU7108500A/en
Publication of WO2001016761A2 publication Critical patent/WO2001016761A2/en
Publication of WO2001016761A3 publication Critical patent/WO2001016761A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526Mutual exclusion algorithms
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284Multiple user address space allocation, e.g. using different base addresses
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0817Cache consistency protocols using directory methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/457Communication
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/544Buffers; Shared memory; Pipes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0837Cache consistency protocols with software control, e.g. non-cacheable data
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/52Indexing scheme relating to G06F9/52
    • G06F2209/523Mode

Abstract

Methods, systems and devices are described for efficient page allocation. A method includes: writing a bit-map representing a freedom state of a plurality of memory pages in a shared memory unit; and scrambling an order of said plurality of memory pages prior to writing said bit-map to reduce contention. The methods, systems and devices provide advantages because the speed and scalability of parallel processor systems is enhanced.
PCT/US2000/024216 1999-08-31 2000-08-31 Efficient page allocation WO2001016761A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU71085/00A AU7108500A (en) 1999-08-31 2000-08-31 Efficient page allocation

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US15215199P 1999-08-31 1999-08-31
US60/152,151 1999-08-31
US22074800P 2000-07-26 2000-07-26
US22097400P 2000-07-26 2000-07-26
US60/220,748 2000-07-26
US60/220,974 2000-07-26

Publications (2)

Publication Number Publication Date
WO2001016761A2 WO2001016761A2 (en) 2001-03-08
WO2001016761A3 true WO2001016761A3 (en) 2001-12-27

Family

ID=27387201

Family Applications (9)

Application Number Title Priority Date Filing Date
PCT/US2000/024039 WO2001016760A1 (en) 1999-08-31 2000-08-31 Switchable shared-memory cluster
PCT/US2000/024216 WO2001016761A2 (en) 1999-08-31 2000-08-31 Efficient page allocation
PCT/US2000/024210 WO2001016740A2 (en) 1999-08-31 2000-08-31 Efficient event waiting
PCT/US2000/024150 WO2001016738A2 (en) 1999-08-31 2000-08-31 Efficient page ownership control
PCT/US2000/024298 WO2001016743A2 (en) 1999-08-31 2000-08-31 Shared memory disk
PCT/US2000/024248 WO2001016742A2 (en) 1999-08-31 2000-08-31 Network shared memory
PCT/US2000/024147 WO2001016737A2 (en) 1999-08-31 2000-08-31 Cache-coherent shared-memory cluster
PCT/US2000/024329 WO2001016750A2 (en) 1999-08-31 2000-08-31 High-availability, shared-memory cluster
PCT/US2000/024217 WO2001016741A2 (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US2000/024039 WO2001016760A1 (en) 1999-08-31 2000-08-31 Switchable shared-memory cluster

Family Applications After (7)

Application Number Title Priority Date Filing Date
PCT/US2000/024210 WO2001016740A2 (en) 1999-08-31 2000-08-31 Efficient event waiting
PCT/US2000/024150 WO2001016738A2 (en) 1999-08-31 2000-08-31 Efficient page ownership control
PCT/US2000/024298 WO2001016743A2 (en) 1999-08-31 2000-08-31 Shared memory disk
PCT/US2000/024248 WO2001016742A2 (en) 1999-08-31 2000-08-31 Network shared memory
PCT/US2000/024147 WO2001016737A2 (en) 1999-08-31 2000-08-31 Cache-coherent shared-memory cluster
PCT/US2000/024329 WO2001016750A2 (en) 1999-08-31 2000-08-31 High-availability, shared-memory cluster
PCT/US2000/024217 WO2001016741A2 (en) 1999-08-31 2000-08-31 Semaphore control of shared-memory

Country Status (4)

Country Link
EP (3) EP1214651A2 (en)
AU (9) AU6949600A (en)
CA (3) CA2382728A1 (en)
WO (9) WO2001016760A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040017301A (en) * 2001-07-13 2004-02-26 코닌클리케 필립스 일렉트로닉스 엔.브이. Method of running a media application and a media system with job control
US6920485B2 (en) 2001-10-04 2005-07-19 Hewlett-Packard Development Company, L.P. Packet processing in shared memory multi-computer systems
US6999998B2 (en) 2001-10-04 2006-02-14 Hewlett-Packard Development Company, L.P. Shared memory coupling of network infrastructure devices
US7254745B2 (en) 2002-10-03 2007-08-07 International Business Machines Corporation Diagnostic probe management in data processing systems
JP2008046969A (en) * 2006-08-18 2008-02-28 Fujitsu Ltd Access monitoring method and device for shared memory
US7685381B2 (en) 2007-03-01 2010-03-23 International Business Machines Corporation Employing a data structure of readily accessible units of memory to facilitate memory access
US7899663B2 (en) 2007-03-30 2011-03-01 International Business Machines Corporation Providing memory consistency in an emulated processing environment
US9442780B2 (en) 2011-07-19 2016-09-13 Qualcomm Incorporated Synchronization of shader operation
US9064437B2 (en) * 2012-12-07 2015-06-23 Intel Corporation Memory based semaphores
WO2014190486A1 (en) 2013-05-28 2014-12-04 华为技术有限公司 Method and system for supporting resource isolation under multi-core architecture

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403283A (en) * 1980-07-28 1983-09-06 Ncr Corporation Extended memory system and method
US4484262A (en) * 1979-01-09 1984-11-20 Sullivan Herbert W Shared memory computer method and apparatus
EP0313787A2 (en) * 1987-10-29 1989-05-03 International Business Machines Corporation A hardware mechanism for the dynamic customization of permutation using bit-matrix multiplication
EP0350713A2 (en) * 1988-07-11 1990-01-17 International Business Machines Corporation Bit map search by competitive processors
US5784699A (en) * 1996-05-24 1998-07-21 Oracle Corporation Dynamic memory allocation in a computer using a bit map index

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668644A (en) * 1970-02-09 1972-06-06 Burroughs Corp Failsafe memory system
US4414624A (en) * 1980-11-19 1983-11-08 The United States Of America As Represented By The Secretary Of The Navy Multiple-microcomputer processing
US4725946A (en) * 1985-06-27 1988-02-16 Honeywell Information Systems Inc. P and V instructions for semaphore architecture in a multiprogramming/multiprocessing environment
US5175839A (en) * 1987-12-24 1992-12-29 Fujitsu Limited Storage control system in a computer system for double-writing
EP0343646B1 (en) * 1988-05-26 1995-12-13 Hitachi, Ltd. Task execution control method for a multiprocessor system with enhanced post/wait procedure
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
DE69124285T2 (en) * 1990-05-18 1997-08-14 Fujitsu Ltd Data processing system with an input / output path separation mechanism and method for controlling the data processing system
US5206952A (en) * 1990-09-12 1993-04-27 Cray Research, Inc. Fault tolerant networking architecture
US5434970A (en) * 1991-02-14 1995-07-18 Cray Research, Inc. System for distributed multiprocessor communication
JPH04271453A (en) * 1991-02-27 1992-09-28 Toshiba Corp Composite electronic computer
EP0528538B1 (en) * 1991-07-18 1998-12-23 Tandem Computers Incorporated Mirrored memory multi processor system
US5315707A (en) * 1992-01-10 1994-05-24 Digital Equipment Corporation Multiprocessor buffer system
US5398331A (en) * 1992-07-08 1995-03-14 International Business Machines Corporation Shared storage controller for dual copy shared data
US5434975A (en) * 1992-09-24 1995-07-18 At&T Corp. System for interconnecting a synchronous path having semaphores and an asynchronous path having message queuing for interprocess communications
DE4238593A1 (en) * 1992-11-16 1994-05-19 Ibm Multiprocessor computer system
JP2963298B2 (en) * 1993-03-26 1999-10-18 富士通株式会社 Recovery method of exclusive control instruction in duplicated shared memory and computer system
US5590308A (en) * 1993-09-01 1996-12-31 International Business Machines Corporation Method and apparatus for reducing false invalidations in distributed systems
US5664089A (en) * 1994-04-26 1997-09-02 Unisys Corporation Multiple power domain power loss detection and interface disable
US5636359A (en) * 1994-06-20 1997-06-03 International Business Machines Corporation Performance enhancement system and method for a hierarchical data cache using a RAID parity scheme
US6587889B1 (en) * 1995-10-17 2003-07-01 International Business Machines Corporation Junction manager program object interconnection and method
US5940870A (en) * 1996-05-21 1999-08-17 Industrial Technology Research Institute Address translation for shared-memory multiprocessor clustering
JPH10142298A (en) * 1996-11-15 1998-05-29 Advantest Corp Testing device for ic device
US5829029A (en) * 1996-12-18 1998-10-27 Bull Hn Information Systems Inc. Private cache miss and access management in a multiprocessor system with shared memory
US5918248A (en) * 1996-12-30 1999-06-29 Northern Telecom Limited Shared memory control algorithm for mutual exclusion and rollback
US6360303B1 (en) * 1997-09-30 2002-03-19 Compaq Computer Corporation Partitioning memory shared by multiple processors of a distributed processing system
DE69715203T2 (en) * 1997-10-10 2003-07-31 Bull Sa A data processing system with cc-NUMA (cache coherent, non-uniform memory access) architecture and cache memory contained in local memory for remote access

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484262A (en) * 1979-01-09 1984-11-20 Sullivan Herbert W Shared memory computer method and apparatus
US4403283A (en) * 1980-07-28 1983-09-06 Ncr Corporation Extended memory system and method
EP0313787A2 (en) * 1987-10-29 1989-05-03 International Business Machines Corporation A hardware mechanism for the dynamic customization of permutation using bit-matrix multiplication
EP0350713A2 (en) * 1988-07-11 1990-01-17 International Business Machines Corporation Bit map search by competitive processors
US5784699A (en) * 1996-05-24 1998-07-21 Oracle Corporation Dynamic memory allocation in a computer using a bit map index

Also Published As

Publication number Publication date
CA2382927A1 (en) 2001-03-08
EP1214652A2 (en) 2002-06-19
WO2001016738A3 (en) 2001-10-04
WO2001016760A1 (en) 2001-03-08
WO2001016742A2 (en) 2001-03-08
AU6949700A (en) 2001-03-26
CA2382929A1 (en) 2001-03-08
CA2382728A1 (en) 2001-03-08
WO2001016740A3 (en) 2001-12-27
WO2001016738A2 (en) 2001-03-08
AU7110000A (en) 2001-03-26
WO2001016761A2 (en) 2001-03-08
AU7108300A (en) 2001-03-26
WO2001016741A3 (en) 2001-09-20
AU6949600A (en) 2001-03-26
WO2001016750A3 (en) 2002-01-17
WO2001016737A3 (en) 2001-11-08
AU7113600A (en) 2001-03-26
AU7100700A (en) 2001-03-26
WO2001016742A3 (en) 2001-09-20
WO2001016738A9 (en) 2002-09-12
AU7112100A (en) 2001-03-26
WO2001016738A8 (en) 2001-05-03
WO2001016740A2 (en) 2001-03-08
AU7108500A (en) 2001-03-26
EP1214651A2 (en) 2002-06-19
WO2001016741A2 (en) 2001-03-08
WO2001016737A2 (en) 2001-03-08
EP1214653A2 (en) 2002-06-19
WO2001016743A2 (en) 2001-03-08
WO2001016743A8 (en) 2001-10-18
WO2001016750A2 (en) 2001-03-08
AU7474200A (en) 2001-03-26
WO2001016743A3 (en) 2001-08-09

Similar Documents

Publication Publication Date Title
GR3035261T3 (en) High performance universal multi-port internally cached dynamic random access memory system, architecture and method
EP1247185A4 (en) Multi-bank, fault-tolerant, high-performance memory addressing system and method
EP1257916A4 (en) System and method for translating to and from hierarchical information systems
BR9205350A (en) Data transfer device for radiotelephone peripheral and radiotelephone unit, data transfer process from radiotelephone peripheral to radiotelephone unit, and data transfer process in radiotelephone unit from radiotelephone peripheral to master unit .
DE69426728D1 (en) SYNTHETIZED STEREOSCOPIC IMAGE GENERATION SYSTEM AND METHOD
AU4691600A (en) System and method for increasing the snoop bandwidth to cache tags in a cache memory subsystem
AU2002225957A1 (en) Method and system for responding to file system requests
AU2618300A (en) Shared memory apparatus and method for multiprocessor systems
CA2299547A1 (en) Pci slot control apparatus with dynamic configuration for partitioned systems
WO2001048606A3 (en) Allocation of data to threads in multi-threaded network processor
AU2001279632A1 (en) Distributor module for use in telecommunications and data systems technology
AU2001257574A1 (en) Method and system for using pervasive device to access webpages
SG101472A1 (en) Method and computer system for controlling access by applications to this and other computer systems
AU1601400A (en) Method and system for selective dram refresh to reduce power consumption
GB9817416D0 (en) Fast access to a shared resource on a computer bus
WO2001016761A3 (en) Efficient page allocation
EP0855057A4 (en) Address transformation in a cluster computer system
AU2417901A (en) A system, a device, a computer program product and a method for allocating resources to users
TW200609727A (en) Method and apparatus for dynamic hosting partition page assignment
DE69626670T2 (en) IMPROVED MESSAGE PROCESSING SYSTEM IN TWO-WAY DATA DEVICES
CA2385079A1 (en) Parallel computer architecture, and information processing unit using the architecture
AU2001255651A1 (en) System and method for using a page tracking buffer to reduce main memory latencyin a computer system
WO2004107184A3 (en) A method and apparatus to improve multi-cpu system performance for accesses to memory
GB0000816D0 (en) Method and system for enabling pervasive computing devices to communicate with each other
DE69426812T2 (en) Image generation system in which the image processing device is connected to the image generation device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US US US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US US US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)