WO2000026791A3 - Secure memory management unit which uses multiple cryptographic algorithms - Google Patents

Secure memory management unit which uses multiple cryptographic algorithms Download PDF

Info

Publication number
WO2000026791A3
WO2000026791A3 PCT/US1999/026171 US9926171W WO0026791A3 WO 2000026791 A3 WO2000026791 A3 WO 2000026791A3 US 9926171 W US9926171 W US 9926171W WO 0026791 A3 WO0026791 A3 WO 0026791A3
Authority
WO
WIPO (PCT)
Prior art keywords
management unit
encrypted data
memory management
secure memory
uses multiple
Prior art date
Application number
PCT/US1999/026171
Other languages
French (fr)
Other versions
WO2000026791A2 (en
Inventor
Gregory Clayton Eslinger
Mark Leonard Buer
Original Assignee
Philips Electronics Na
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/186,546 external-priority patent/US6910094B1/en
Application filed by Philips Electronics Na filed Critical Philips Electronics Na
Priority to JP2000580099A priority Critical patent/JP2002529815A/en
Priority to EP99961596A priority patent/EP1125206A2/en
Publication of WO2000026791A2 publication Critical patent/WO2000026791A2/en
Publication of WO2000026791A3 publication Critical patent/WO2000026791A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories

Abstract

An integrated circuit accesses first encrypted data stored in an external random access memory and accesses second encrypted data stored in an external read-only memory. The external random access memory and the external read-only memory are external to the integrated circuit. When accessing a first portion of the first encrypted data stored in the external random access memory, a first algorithm is used to decrypt the first portion of the first encrypted data. When accessing a first portion of the second encrypted data stored in the external read-only memory, a second algorithm is used to decrypt the first portion of the second encrypted data. The second algorithm is different than the first algorithm.
PCT/US1999/026171 1998-11-05 1999-11-04 Secure memory management unit which uses multiple cryptographic algorithms WO2000026791A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000580099A JP2002529815A (en) 1998-11-05 1999-11-04 Secure memory management unit using multiple encryption algorithms
EP99961596A EP1125206A2 (en) 1998-11-05 1999-11-04 Secure memory management unit which uses multiple cryptographic algorithms

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/186,546 1998-11-05
US09/186,546 US6910094B1 (en) 1997-10-08 1998-11-05 Secure memory management unit which uses multiple cryptographic algorithms

Publications (2)

Publication Number Publication Date
WO2000026791A2 WO2000026791A2 (en) 2000-05-11
WO2000026791A3 true WO2000026791A3 (en) 2000-07-27

Family

ID=22685369

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/026171 WO2000026791A2 (en) 1998-11-05 1999-11-04 Secure memory management unit which uses multiple cryptographic algorithms

Country Status (3)

Country Link
EP (1) EP1125206A2 (en)
JP (1) JP2002529815A (en)
WO (1) WO2000026791A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100538587C (en) 2000-07-18 2009-09-09 辛普雷克斯梅杰有限公司 Digital data protection arrangement
JP4153653B2 (en) 2000-10-31 2008-09-24 株式会社東芝 Microprocessor and data protection method
GB0123417D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Improved data processing
DE10238095B4 (en) * 2002-08-21 2007-08-30 Audi Ag Method for protection against manipulation of a control unit for at least one motor vehicle component and control unit
DE10306844A1 (en) * 2003-02-18 2004-09-02 Micronas Gmbh Processor for computer, encodes and/or decodes data to be transferred via interface to external memory
US7325115B2 (en) * 2003-11-25 2008-01-29 Microsoft Corporation Encryption of system paging file
US7444523B2 (en) 2004-08-27 2008-10-28 Microsoft Corporation System and method for using address bits to signal security attributes of data in the address space
US7822993B2 (en) 2004-08-27 2010-10-26 Microsoft Corporation System and method for using address bits to affect encryption
US7653802B2 (en) 2004-08-27 2010-01-26 Microsoft Corporation System and method for using address lines to control memory usage
US7734926B2 (en) 2004-08-27 2010-06-08 Microsoft Corporation System and method for applying security to memory reads and writes
DE102005051577B4 (en) * 2005-10-21 2008-04-30 Engel Solutions Ag Method for encrypting or decrypting data packets of a data stream and signal sequence and data processing system for carrying out the method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4847902A (en) * 1984-02-10 1989-07-11 Prime Computer, Inc. Digital computer system for executing encrypted programs
US5224166A (en) * 1992-08-11 1993-06-29 International Business Machines Corporation System for seamless processing of encrypted and non-encrypted data and instructions
EP0694846A1 (en) * 1994-07-29 1996-01-31 STMicroelectronics S.A. Numerial scrambling method and its application to a programmable circuit
US5757919A (en) * 1996-12-12 1998-05-26 Intel Corporation Cryptographically protected paging subsystem

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4847902A (en) * 1984-02-10 1989-07-11 Prime Computer, Inc. Digital computer system for executing encrypted programs
US5224166A (en) * 1992-08-11 1993-06-29 International Business Machines Corporation System for seamless processing of encrypted and non-encrypted data and instructions
EP0694846A1 (en) * 1994-07-29 1996-01-31 STMicroelectronics S.A. Numerial scrambling method and its application to a programmable circuit
US5757919A (en) * 1996-12-12 1998-05-26 Intel Corporation Cryptographically protected paging subsystem

Also Published As

Publication number Publication date
WO2000026791A2 (en) 2000-05-11
JP2002529815A (en) 2002-09-10
EP1125206A2 (en) 2001-08-22

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