WO1998012620A1

WO1998012620A1 - Microcomputer having reset control function

Info

Publication number: WO1998012620A1
Application number: PCT/JP1996/002725
Authority: WO
Inventors: Taiki Nishiuchi; Yuji Kitaguchi
Original assignee: Mitsubishi Denki Kabushiki Kaisha; Mitsubishi Denki Engineering Kabushiki Kaisha
Priority date: 1996-09-20
Filing date: 1996-09-20
Publication date: 1998-03-26
Also published as: TW422947B

Abstract

A microcomputer comprising a central processing unit for executing collective processings; a peripheral unit for executing predetermined operations; a hardware-resettable peripheral register for setting the operation of the peripheral unit; a first flag for storing information on whether or not the reset operation of the central processing unit by an external reset signal is the first since the power is on; and a reset control unit for delivering a register reset signal for hardware resetting of the peripheral register when the external reset signal is inputted under the state where the information stored in the first flag represents the first reset operation, and inhibiting the output of the register reset signal when the external reset signal is inputted under the state where the information stored in the first flag represents that the reset operation is not the first reset operation.

Description

Description Microcomputer with reset control function

The present invention relates to a microcomputer used for controlling electronic devices, for example, and more particularly to a reset function of a microcomputer. Background art

Conventionally, semiconductor circuits such as microcomputers have c

A reset is applied immediately after the power is turned on to operate the PU and peripheral devices normally.

FIG. 27 is a block diagram showing the configuration of such a conventional microcomputer. In the figure, reference numeral 10 denotes a reset IC, and 100 denotes a single-chip microcomputer. The Singnore chip microcontroller 100 has a CPU 110 for overall processing, a memory 120 for storing programs and data, a peripheral function section 130, and a special function for the peripheral function section. A section register (hereinafter referred to as SFR) section 140, a reset determination flag 150, an address bus 160 for specifying the end address of the memory 120, etc., and a data section for each section. And a bus 170 for transferring data.

The memory 120 has RAM I 21 and ROM 122. The peripheral function section 130 converts the digital signal into an analog signal and outputs it. The D-to-A converter 13 1 and the analog-to-digital converter 1 that inputs the analog signal and converts it into a digital signal. 3 2 and serial I / 0 (hereinafter referred to as SI / 0) that communicates with external devices in serial 1 3 3 and CPU 11 It has a watchdog timer (hereinafter referred to as WDT) 1334 that resets the CPU 110 when it is determined that a runaway has occurred, and a timer 135 that performs a timing operation for control and the like. . Also, the SFR section 140 is composed of the SFR 14 1 for D-A, the 5 1 4 2 for −0, the SFR 1 4 3 for SI / 0, the SFR 1 4 4 for WDT, and the SFR 1 4 for timer. 4 5. The single-chip microcomputer 100 is configured to receive the power supply undervoltage VCC.

Next, the operation will be described.

When the power supply voltage V CC rises from zero to a predetermined voltage due to the reset IC 10, the reset voltage rises slightly later than the rise. Due to this delay, hardware reset of the CPU 110 and the SFR section 140 to which the reset signal is supplied is executed. That is, every time the power is turned on, the CPU 110 and the SFR section 140 are reset. After that, the CPU 110 performs initial setting processing of the register value in the CPU 110 and the register value of the SFR section 140 by the program of the CPU 110.

By the way, even when the power is not turned off, the reset signal output from the reset IC 10 may be at the “low” level due to noise or the like. In consideration of such circumstances, when turning on the power and in other cases, C P U

A reset determination flag 150 is provided to distinguish 110 from 110. FIG. 28 is a flowchart showing the operation of the reset processing of the CPU 110. As shown in the figure, the CPU 110 determines the value of the reset determination flag 150 (step ST2801), and sets the “L” level, that is, the reset determination flag 150, to ON. If not, reset judgment flag

Set 150 to the "H" level (step ST2802 :), and set the initial value of the CPU 110 register time (step ST2803). Then S Set the initial value of FR section 140 (step ST2804). On the other hand, when the reset determination flag 150 is set in step ST2801, that is, when it is "H", it is recognized that the power supply is not turned on, and step ST2801 is recognized. Move to 4 to set the initial value of SFR section 140.

Therefore, if the reset signal goes to “L” level while the power supply voltage VCC is maintained at the predetermined voltage, the reset judgment flag 150 is set and the CPU 110 Is not performed. However, if the SFR section 140 is reset, it will be set to a constant value in terms of hardware. Therefore, as shown in the flowchart of FIG. 28, the reset judgment of the SFR section 140 is performed. Regardless of the flag 150, 'H' or 'L', the address bus 16 0 and the data bus 17 are set to the default values required by the single-chip microcomputer 110 program. The setting must be reset via 0, which takes time and interrupts the operation of the peripheral function unit 130. For this reason, if the CPU 110 is reset due to noise or the like, the SFR section 140 is reset even if the CPU 110 performs a hot-shut-down that does not initialize data. The SFR value must be set, and the peripheral function unit 130 cannot operate continuously.

The present invention has been made in order to solve the above problems, and a microcontroller capable of continuing the operation of a peripheral function unit even when noise or the like is superimposed on a reset signal after power-on. An object of the present invention is to provide an electronic device having a reset function such as a pu-y setting. Disclosure of the invention

The invention described in claim 1 is characterized in that the reset control unit determines whether or not the information stored in the reset determination flag indicates the first reset operation. When an external reset signal is input, a reset signal is sent to reset the peripheral function register in a hardware manner, and the information stored in the reset determination flag is not the first reset operation. When an external reset signal is input in such a case, the reset control of the peripheral function register is executed without sending the register reset signal, so the reset signal is generated due to noise etc. However, the peripheral function register section is not reset, and the peripheral function section has an effect that the operation can be continued continuously thereafter.

The invention according to claim 2 includes a peripheral function unit including an AD converter for converting an analog signal to a digital signal, and a peripheral function register unit including an A-D converter. The peripheral function register is not reset even if a reset signal is generated due to noise or the like, and the A / D converter operates continuously thereafter. Has the effect of being able to continue.

The invention according to claim 3 is characterized in that the peripheral function unit includes a DA converter for converting an analog signal to a digital signal, and the peripheral function register unit operates the DA converter. Configuration register is included, the peripheral function register is not reset even if a reset signal is generated due to noise, etc., and the DA converter continues to operate continuously thereafter There is an effect that can be.

The invention described in claim 4 includes a serial input / output device in which the peripheral function unit converts an analog signal to a digital signal, and a peripheral function register in which the operation setting of the serial input / output device is performed. The peripheral function register section is not reset even if a reset signal is generated due to noise, etc., and the serial input / output device can continue to operate continuously thereafter. There is an effect that can be done. The invention described in claim 5 is configured such that the peripheral function unit includes a timer for converting an analog signal to a digital signal, and the peripheral function register unit includes a register for setting the operation of the timer. Therefore, even if a reset signal is generated due to noise or the like, the peripheral function register is not reset, and the timer can continue to operate continuously thereafter. The invention described in claim 6 includes a watchdog timer in which the peripheral function unit converts an analog signal into a digital signal, and a peripheral function register unit in which the setting of the operation of the watchdog timer is performed. The peripheral function register section is not reset even if a reset signal is generated due to noise or the like, and the watchdog timer can continue to operate continuously thereafter. effective.

According to the invention described in claim 7, when the watchdog timer outputs a signal indicating runaway, the reset control unit sends the register reset signal regardless of the information stored in the reset determination flag. Then, the reset control of the peripheral function register is performed, so that there is an effect that more stable reset control can be performed.

The invention described in claim 8 is characterized in that the reset control unit receives the external reset signal when the information indicating the flag-independent mode is stored in the reset mode flag. Since the register reset signal is sent to the peripheral function register regardless of the information stored in the first flag, the mode can be changed depending on the nature of the program to be executed and the reset can be performed more efficiently. There is an effect that can be processed.

The invention described in claim 9 is characterized in that the first reset signal generated from the first power supply for supplying power to the central processing unit and the second reset signal generated for supplying power to the peripheral function unit are generated. A signal for executing the reset of the central processing unit is sent to the central processing unit only when both of the input second reset signal and the reset signal are input. With such a configuration, even when noise is superimposed on the reset signal line, it is difficult to reset the central processing unit, and there is an effect that the central processing unit operates stably. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of the reset control circuit shown in FIG.

FIG. 3 is a flowchart showing the operation of the reset processing of the CPU according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing timing of input / output signals of the reset control circuit shown in FIG.

FIG. 5 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 2 of the present invention.

FIG. 6 is a circuit diagram showing a detailed configuration of the reset control circuit shown in FIG.

FIG. 7 is a flowchart showing the operation of the reset processing of the CPU according to the second embodiment of the present invention.

FIG. 8 is a timing chart showing the timing of the signals of the respective units when the reset signal goes “L” when the power is on in the second embodiment of the present invention.

FIG. 9 is a block ^ showing the configuration of a single-chip microcomputer according to Embodiment 3 of the present invention.

FIG. 10 is a circuit diagram showing the configuration of the reset control circuit shown in FIG. FIG. 11 is a flowchart showing an operation at the time of resetting the CPU according to the third embodiment of the present invention.

FIG. 12 is an evening chart showing timings of signals of respective parts according to the third embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a single-chip microcomputer according to the fourth embodiment of the present invention.

FIG. 14 is a circuit diagram showing a detailed configuration of the reset control circuit of FIG.

FIG. 15 is a flowchart showing the operation of the reset processing of the CPU according to the fourth embodiment of the present invention.

FIG. 16 is a timing chart showing the timing of the input / output signals of the reset control circuit shown in FIG.

FIG. 17K is a block diagram illustrating a configuration of a single-chip microcomputer according to Embodiment 5 of the present invention.

FIG. 18 is a flowchart showing the operation of the reset processing of the CPU according to the fifth embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of a single-chip micro computer according to Embodiment 6 of the present invention.

FIG. 20 is a flowchart showing the operation of the reset process of the CPU according to the sixth embodiment of the present invention.

FIG. 21 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 7 of the present invention.

FIG. 22 is a flowchart showing the operation of the reset process of the CPU according to the seventh embodiment of the present invention.

FIG. 23 is a block diagram showing a configuration of a single-chip microcomputer according to an eighth embodiment of the present invention. FIG. 24 is a circuit diagram showing a detailed configuration of the reset control circuit shown in FIG.

FIG. 25 is a flowchart showing the operation of the reset process of the CPU according to the eighth embodiment of the present invention.

FIG. 26 is a timing chart showing the timing of the input / output signals of the reset control circuit shown in FIG.

Fig. 27 is a block diagram showing the configuration of a conventional microcomputer.

FIG. 28 is a flowchart showing the operation of the reset processing of the CPU of the conventional microcomputer. BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1

FIG. 1 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 1 of the present invention. In the same figure, reference numeral 20 denotes a reset IC, and reference numeral 200 denotes a single-chip microcomputer. The single-chip microcomputer 200 has a central processing unit (CPU) 210 that performs overall processing, a memory 220 that stores programs and data, a peripheral function unit 230, and a peripheral function unit. 230 SFR part (peripheral function register part), which is a fusion of special function register evening (hereinafter referred to as SFR) on river 240, and reset judgment flag (first flag) 2 50, an address bus 260 for designating an address such as a memory 220, and a data bus 270 for transferring data to each section.

The memory 220 has a RAM 222 and a ROM 222. The peripheral function section 230 converts the digital signal into an analog signal and outputs it. — A converter 2 31 and an analog signal that converts an analog signal to a digital signal A — D converter 2 32 and communicates with external devices serially I / 0 (hereafter SI / 0) A serial I / O device) 2 3 3 and a watchdog timer (hereinafter abbreviated as WDT) that resets CPU 210 when it detects runaway of CPU 210 and determines that it is running away. 2 and a timer 235 for executing a timekeeping operation for control and the like. The SFR section 240 is composed of the SFR 241 for D-A, the SFR 242 for A-D, the SFR 243 for SI ZO, the SFR 244 for WDT, and the SFR 244 for the timer. 4 5. The power supply voltage VCC is applied to the single-chip microcomputer 200.

Further, the single-chip microcomputer 200 has a reset control circuit (reset control unit) 280. Then, the reset signal from the reset IC 20 is directly input to the CPU 210 and the reset control circuit 280. The reset control circuit 280 is configured so that the value of the reset determination flag 250 is input to the reset control circuit 280. FIG. 2 is a detailed diagram of the reset control circuit 280 in FIG. FIG. 3 is a circuit diagram showing a configuration. As shown in the figure, the reset control circuit 280 is composed of inverters 281, 282 and a NAND gate 283.

Next, the operation will be described.

When the power is turned on, the reset signal from the reset IC 20 is input to the CPU 210 and the reset control circuit 280. The CPU 210 is reset, and a reset program described later is executed. When the power is turned on, the reset determination flag 250 is “L” and the reset signal is “Si”, so the output of the NAND gate 283 is “L”. For this reason, the reset control circuit 280 outputs an “L” level signal, and the SFR section 240 Reset as hardware.

FIG. 3 is a flowchart showing the reset processing operation of the CPU 210. As shown in the figure, first, when the value of the reset determination flag 250 is “L” (step ST 301), the reset determination flag is determined as a power-on reset. Setting 250 to “H” (step ST302), the CPU 210 registers are initialized (step ST303), and then the SFR value of the SFR section 240 is set. Is initialized (step ST304). On the other hand, if the reset judgment flag 250 is set to “H” in step ST301, the CPU 210 judges that it is a hot start, and the registers of the SFR section 240 and the CPU 210 The reset processing ends without performing the initial setting operation of the values such as.

FIG. 4 is a timing chart showing the timing of the input / output signals of the reset control circuit 280 shown in FIG. In the figure, (a) is the reset signal input to the reset control circuit 280, (b is the value of the reset determination flag 250, and (c) is the output f of the reset control circuit 280. As shown in the figure, when the reset judgment flag 250 is set to the “H” level, it is judged that it is not at the time of turning on the 1 power source and reset ^ signal Even if the signal becomes “L”, the output signal of the reset control circuit 280 remains at the “H” level, so that the SFR section 240 is not reset in hardware.

Note that the reset control circuit 280 needs to send the SFR section 240 helicopter signal before the CPU 210 executes step ST303 in Fig. 3 when the power is turned on. Since the CPU control circuit 280 performs signal processing with small-scale hardware consisting of two inverters and one gate, the CPU 210 executes the step ST303 while the CPU 210 executes the step ST303. Thus, the signal transmission processing of the reset control circuit 280 is performed sufficiently earlier. As described above, according to the first embodiment, the SFR section 240 is not reset by the reset control circuit 280 even when the reset signal goes to the “L” level except when the power is turned on. The SFR section 240 is not reset even if the reset signal becomes “no” due to noise, etc., and the peripheral function section 230 can continue to operate continuously thereafter. There is. Embodiment 2

FIG. 5 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 2 of the present invention. The same parts as those shown in FIG. 1 are denoted by the same reference numerals, and overlapping description will be omitted. In the figure, reference numeral 300 denotes a single-chip microcomputer, 310 denotes a reset mode flag (second flag) for setting a reset mode, and 320 denotes a reset IC 20. The reset control circuit supplies a reset signal to the SFR section 240 based on the output reset signal, the value of the reset determination flag 250 and the reset mode flag 310.

FIG. 6 is a circuit diagram showing a detailed configuration of the reset control circuit 320. In the figure, 3221 and 3222 indicate the evening, 3223 indicates the age, and 3224 indicates the NAND gate, respectively.

Next, the operation will be described.

First, the user sets the value of the reset mode flag 310 by the CPU 210 program. To select the flag-independent mode that resets the SFR block 240 by a reset signal that is input independently of the reset determination flag 250, set the reset mode flag 310 to “H”. Set to On the other hand, similarly to the first embodiment described above, a reset determination flag 250 and a flag for resetting the SFR section 240 based on the reset signal are set. To select the dependent mode, set the reset mode flag 310 to “L”. As shown in Fig. 6, when the reset mode flag 310 is set to "H", the output of OR gate 3 23 is always set to "H" and the reset signal is output from the NAND gate 3 2 4 The same signal as is output as SFR reset signal. On the other hand, when the “low” level signal is set in the reset mode flag 310, the output signal of the output 32 3 becomes the same as the output signal of the inverter 3 2 1. FIG. 7 shows the same operation as that described in the first embodiment. FIG. 7 is a flowchart showing the operation of the reset process of CPU 210. First, when reset, the reset judgment flag 250 is output in step ST701, and if it is “L” (step ST701), it is determined that the power is turned on and reset. The CPU 250 sets the CPU determination flag 250 to “H” (step ST 702), initializes the registers of the CPU 210 (step ST 703), and subsequently sets the SFR Initial setting of the SFR value of the section 240 is performed (step ST704). On the other hand, if the reset determination flag 250 is still "H" at step ST701, the reset mode flag 310 is referred to (step ST705), indicating the flag-dependent mode. In this case, the process proceeds to step ST704, and if the flag-independent mode is indicated, the reset processing is terminated as it is.

That is, the CPU 210 performs the reset processing of the CPU 210 and the initial setting of the SFR section 240 as reset processing when the power is turned on. In the mode, the initial value of the SFR section 240 is set, and in the flag-independent mode, the reset processing is terminated as it is.

FIG. 8 is a timing chart showing the timing of the signal of each part when the reset signal becomes “OFF” when the power is on. In the figure (A) is the reset signal input to the reset control circuit 320, (b) is the value of the reset determination flag 250, and (c) is the value of the reset mode flag 310. , (D,) indicate the SFR reset signal which is the output signal of the reset control circuit 320. If a “H” level signal is stored in the reset mode flag 310 as shown at time T 1 in the figure, the reset determination flag 2 will be output even if the reset signal becomes “HI”. If the value of 50 is “H”, the SFR reset signal is “H”, and no hardware reset is applied to the SFR section 240. On the other hand, when the reset mode flag 310 is set to “L” as shown at time T 2, that is, in the flag-independent mode, the SFR reset signal is the same as the input reset signal. When the reset signal becomes “L”, the SFR 240 is reset in hardware.

As described above, according to the second embodiment, the reset mode flag 310 is provided, and the value of this flag is used to determine the flag independent mode that does not depend on the value of the reset determination flag 250 and the reset determination. The SFR section 240 can be reset by switching to the flag-dependent mode depending on the flag 250. For this reason, there is an effect that the mode can be changed depending on the property of the program to be executed and more efficient reset processing can be performed. Embodiment 3.

FIG. 9 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 3 of the present invention. The same parts as those shown in FIG. 1 are denoted by the same reference numerals, and overlapping description will be omitted. In the third embodiment, the peripheral function unit 230, the SFR unit 240, and the reset IC 20 are supplied with 3 volts VCC 3 (second power supply) as a power supply. 10 is powered by 5 volts VCC 5 (the first power supply). 9th (Puni Here, 21 indicates a reset IC, and VCC 5 is input. Note that the output signals of reset IC 20 and reset IC 21 are configured so that the rise of VCC 5 and VCC 3 is slow enough to reset the SFR section 240 and CPU 210. Have been. 400 is a single-chip microcomputer of the third embodiment, and 410 is a CPU based on a reset signal output from the reset IC 20 and a reset signal output from the reset IC 21. The figure shows a reset control circuit that outputs a CPU reset signal for resetting 210.

FIG. 10 is a circuit diagram showing the configuration of the reset control circuit 410 shown in FIG. As shown in the figure, the reset control Id path 410 is composed of an orifice 411. The output of the reset IC 20 and the output of the reset IC 21 are input to the input of the OR gate 411, and the logical sum of these signals is calculated and supplied to the CPU 210 as a CPU reset signal. Has been. Further, the reset signal from the reset IC 20 is also supplied to the SFR section 240.

Next, the operation will be described.

First, at power-on, V CC 5 and V CC 3 rise simultaneously. At this time, the outputs of the reset IC 20 and the reset IC 21 are input to the reset control circuit 410, the logical sum of these two signals is obtained, and the CPU 210 resets the CPU. Supplied as a signal. Therefore, when power is turned on, CPU 210 is reset. The processing after the CPU 210 is reset will be described later in detail. Further, the reset signal output from the reset IC 20 is also supplied to the SFR section 240 and is reset in hardware.

When the power is on, the logical sum is obtained by OR gate 411. Therefore, even if noise or the like is superimposed on either reset signal, When only the signal of “L” becomes “L” level, it is not reset.

FIG. 11 is a flowchart showing the operation when the CPU 210 is reset. As shown in the figure, first, when reset is performed, the reset determination flag 250 is set to “L” (step ST 1101). The flag 250 is set to "H" (step ST1102), and the initial setting of the CPU 210 register is performed (step ST1103). Subsequently, the initial setting of the SFR value of the SFR section 240 is performed (step ST1104). On the other hand, if the reset determination flag 250 is "H" at step ST1101, the process proceeds to step ST1104 to set the initial value of the SFR section 240.

FIG. 12 is a timing chart showing timings of signals of respective parts according to the third embodiment. In the figure, (a) is VCC 5, (b) is VCC 3, (c) is the reset signal from reset IC 20, (d) is the CPU reset signal supplied to CPU 210, (E) shows the value of the reset determination flag 250. As shown in the figure, at time T1, V CC 3 is at the “L” level, but V CC 5 remains at the “H” level. Therefore, the reset signal of the “L” level is not supplied to the CPU 210 from the reset control circuit 410, and the CPU 210 is not reset. On the other hand, at time T2, since V CC 5 and V CC 3 are simultaneously at the “L” level, the reset control circuit 410 outputs the “P” reset signal at the “L” level. At this time, the CPU 210 refers to the reset determination flag 250 and executes the reset processing shown in FIG. 11 depending on whether the force is at the “H” level or the “L” level.

As described above, according to the third embodiment, the reset control circuit 410 resets the reset signal generated from VCC3 and the reset signal generated from VCC5. Since the CPU reset signal is generated from the logical sum with the reset signal, the CPU 210 is reset even if noise is superimposed on the output of the reset ICs 20 and 21. This makes it difficult for the CPU 210 to operate stably. Embodiment 4.

FIG. 13 is a block diagram showing a configuration of a single-chip microcomputer of Embodiment 4 of the present invention. The same parts as those shown in FIG. 1 are denoted by the same reference numerals, and overlapping description will be omitted. In FIG. 13, reference numeral 500 denotes a single-chip microcomputer according to the fourth embodiment, and reference numeral 501 denotes a reset for generating an individual SFR reset signal for resetting the SFR 243 for SIZO. 3 shows a control circuit. The output of reset IC 20 is CPU 210, reset control circuit 510, D-A | ff SFR 241, A-Dffl SFR 24, WD Tffl SFR 24, and timer ffl It is lined up with SFR 245. S IZOffl S F F 243 includes parity, synchronization type, transmission buffer register, register for setting stop bit, and the like.

FIG. 14 is a circuit diagram showing a detailed configuration of the reset control circuit 5110 of FIG. In Fig. 14, 511 and 512 indicate overnight and 513 indicates a NAND gate. The reset signals of the reset determination flag 250 and the reset signal and the reset signal of the reset IC 210 are input to the inverters 512 and 511, respectively.

Next, the operation will be described.

When the power is turned on, the reset signal from reset IC 20 is reset control circuit 510, D—A SFR 241, A—D SFR 2 42, WD Tffl SFR 24 Supplied to SFR 2 4 5 for timer and timer Reset as wear. On the other hand, when the reset signal β is input from the reset IC 20, the CPU 210 executes a reset operation described later. On the other hand, resets 1 and † from the reset IC 20 are input to the reset control circuit 510. When the power is turned on, the reset judgment flag 250 is “L” and the reset signal is “L”, so the output of the NAND gate 5 13 of the reset control circuit 51 is “L”. . For this reason, the reset control circuit 510 outputs an “L” level signal, and the SFR 243 for SI0 is reset in hardware.

FIG. 15 is a flowchart showing the operation of the reset processing of the CPU 210. As shown in the figure, first, when the value of the reset determination flag 250 is “L” (step ST 1501), it is determined that the power is turned on, and the reset determination flag is determined. Set “250” to “H” (step ST1502 :), set the initial settings of the CPU 210 register (step ST1503), and use the SI / O SFR The initial setting of the value of (step ST1504) and the initial setting of other SFRs (step ST1505) are performed. On the other hand, in step ST1501, the reset determination flag 250 is turned on, and if "H", the CPU 210 determines that it is a hot start and shifts to step S1505 to proceed to SIZO. The initial value of other SFRs is set without performing the initial setting operation of the values of the SFRs 243 and CPU 210 registers, and the reset processing ends.

FIG. 16 is a timing chart showing the evening timing of the input / output signals of the reset control circuit 510 shown in FIG. In the figure, (a) shows the reset signal input to the reset control circuit 510, (b) shows the value of the reset determination flag 250, and (c) shows the output of the reset control circuit 510. This shows the individual SFR reset signal to be performed. As shown in the figure, when the reset judgment flag is set to 250 H level, Even if it is determined that the reset signal does not exist, the reset signal of the reset control circuit 510 remains at the “H” level even if the reset signal becomes “HI”. Not reset.

When the power is turned on, the reset control circuit 510 must send the SFR2 43 helicopter signal for SI0 before the CPU 210 executes step ST1504 in Fig. 15. However, the reset control circuit 510 performs signal processing with small-scale hardware consisting of two inverters and one gate, so the CPU 210 executes the step ST 1504. On the other hand, the reset control circuit 510 performs the signal transmission process sufficiently sooner than described above. According to the fourth embodiment, as described above, the reset signal becomes “L” except when the power is turned on. The SFR 243 for SI ZO is configured so that it will not be reset by the reset control circuit 510 even when the level reaches the '' level, so even if the reset ^ signal becomes `` S '' due to noise etc. SI0 SFR 243 is not reset and SIZ 233 does not require initialization There is an effect that the operation can be continued continuously thereafter. Embodiment 5.

FIG. 17 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 5 of the present invention. The same parts as those shown in FIG. 13 are denoted by the same reference numerals, and overlapping description will be omitted. The difference between Fig. 17 and Fig. 13 is that the individual SFR reset signal from the reset control circuit 510 is supplied to the timer SFR 245 instead of the SI S SFR 243. The reset signal output from the reset IC 20 is the CPU 210, the reset control circuit 510, D—SFR 241 for A, SFR 242 for A—D, SFR 2 for SI ZO 4 3, supplied to SFR 2 4 4 for WDT Is Rukoto. In FIG. 17, 600 indicates a single-chip microcomputer according to the fifth embodiment.

The 18th is a chart showing the operation of the reset processing of the CPU 210. The same parts as those in FIG. 15 are denoted by the same reference numerals, and redundant description will be omitted. FIG. 18 is different from FIG. 15 in steps S 1801 and step ST 1802. That is, the initial value of the timer SFR 245 is set in step ST1801, and the initial value of the SFR other than the timer SFR245 is set in step ST1802.

Therefore, in the fifth embodiment, the timer control SFR 245 is not reset by the reset control circuit 510 even if the reset signal goes to “L” level except when the power is turned on. Therefore, even if the reset signal becomes “L” due to noise, etc., the SFR 245 for evening image is not reset, and the timer 235 does not need the initial setting operation, and then continuously. There is an effect that the operation can be continued. Embodiment 6.

FIG. 19 [] is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 6 of the present invention. The same parts as those shown in FIG. 13 are denoted by the same reference numerals, and overlapping description will be omitted. The difference between Fig. 19 and 13 is that the individual SFR reset signal from the reset control circuit 5 10 is supplied not to the SFR 2 4 3 for SI Z0 but to the 5 1 2 4 2 for 8 0 The reset signal output from the reset IC 20 is the CPU 210, the reset control circuit 510, the D-A SFR 2 41, the SI ZO SFR 2 43, and the WDT It is supplied to SFR 244 and SFR 245 for timer. In FIG. 19, reference numeral 700 denotes a single-chip microcomputer of the sixth embodiment. FIG. 20 is a flowchart showing the operation of the reset process of the CPU 210. The same parts as those in FIG. 15 are denoted by an I-sign ^, and redundant description is omitted. FIG. 20 differs from FIG. 15 in steps ST2001 and step ST2002. That is, the initial value of the SFR 242 for A_D is set in step ST2001, and the initial value of the SFR other than the SFR224 for A-D is set in step ST2002.

Therefore, in the sixth embodiment, even if the reset signal goes to the “L” level except when the power is turned on, the reset control circuit 510 does not reset the A-D SFRs 242. Therefore, even if the reset signal becomes “L” due to noise, etc., the SFR 242 for A-D is not reset, and the A-D converter 232 requires the initial setting operation. However, there is an effect that the operation can be continued continuously thereafter. Embodiment Ί.

FIG. 21 is a block diagram showing a configuration of a single-chip micro-computer according to a seventh embodiment of the present invention. The same reference numerals are given to the same portions as those shown in the 13th paragraph, and the overlapping description is omitted. The difference between Fig. 21 and Fig. 13 is that the individual SFR reset signal from the reset control circuit 510 is supplied to the D-A SFR 241 instead of the SI / 0 SFR 243 The reset signal output from reset IC 20 is CPU 210, reset control circuit 510, A—Dffl SFR 24, SIZO SFR 243, and WDT SFR It is supplied to SFR 245 for evening and ima. In FIG. 21, reference numeral 800 denotes a single-chip microphone mouth computer according to the seventh embodiment.

FIG. 22 is a flowchart showing the operation of the reset process of the CPU 210. 15th [The same parts as in ¾1 are marked with the same symbols, and duplicate descriptions are omitted. You. FIG. 22 is different from FIG. 15 in steps ST2201 and ST2202. That is, the initial value of the SFR 241 for DA is set in step ST222, and the initial value of the SFR other than the SFR241 for DA is set in step ST222.

Therefore, in this embodiment 7, even when the reset signal goes to “L” level except when the power is turned on, the reset control circuit 510 does not reset the SFR 241 for DA. Therefore, even if the reset signal becomes “no” due to noise or the like, the SFR 241 for DA is not reset, and the DA converter 231 needs to perform the initial setting operation. However, there is an effect that the operation can be continued continuously thereafter. Embodiment 8.

FIG. 23 is a block diagram showing a configuration of a single-chip microcomputer according to Embodiment 8 of the present invention. The same parts as those shown in FIG. 1 are denoted by the same reference numerals, and overlapping description will be omitted. In FIG. 23, reference numeral 900 denotes a single-chip micro combination of the eighth embodiment, and reference numeral 9100 denotes a reset signal output from the reset IC 20 and a CPU output from the WDT 234. A reset control circuit that outputs the individual reset signal of the WDT SFR 244 from the WDT interrupt signal indicating that 210 is running away and the reset determination flag 250 . The output of reset IC 20 is CPU 210, reset control circuit 910, SFR 2 41 for D-A, 5 2 4 2 for 8-0, SFR 2 4 3 for SI / 0, And Sima for evening life Supplied to SFR 245.

FIG. 24 is a circuit diagram showing a detailed configuration of the reset control circuit 910 of FIG. In FIG. 24, 911 and 912 indicate the evening, 913 indicates the NAND gate, and 914 indicates the AND gate. Inverter 9 1 The signals from the reset determination flag 250 and the reset ^ from the reset IC 20 are input to 1, 9 and 12, respectively. Note that the reset signal for hardware reset of the SFR 244 for WD II is output from the AND gate 914.

Next, the operation will be described.

When the power is turned on, SFRs other than CΡU210 and WDTJHSFFR244 are reset by the output signal from reset IC20. The reset processing of CPU 210 will be described later in detail. As described in the first embodiment, since the output of the NAND gate 913 of the reset control circuit 910 becomes “L”, regardless of the WDT interrupt signal, the output gate 914 is “ Outputs an “L” level signal. For this reason, a signal of the "low" level is supplied to the WDT SFR 244 and the hardware is reset.

After that, when the power is on, the WDT 234 sends an “H” level signal to the CPU 210 and reset control if it determines that the CPU 210 is operating normally. Output to circuit 910. In this case, the input terminal on the side connected to the gate 914 of the AND gate 911 becomes “H” level, and the output signal of the AND gate 914 becomes the NAND gate. It becomes the same as the output signal of 9 13. On the other hand, if the WDT 234 detects a runaway of the CPU 210, it sends an “L” level WDT interrupt signal to the CPU 210 and the reset control circuit 910. Upon receiving this signal, the CPU 210 stops operating. When a “W” level WDT interrupt signal S− is input to the reset control circuit 910, the output of the AND gate 914 will be “regardless of the state of the signal input to the other input terminal. ”Level. Therefore, the SFR 244 for the WDT is reset in hardware.

FIG. 25 is a flowchart showing the reset processing operation of the CPU 210. The same parts as those in FIG. 15 are denoted by the same reference numerals, and duplicate description will be omitted. You. FIG. 25 differs from FIG. 15 in steps ST 2 501 and step ST 2 502. That is, in step ST2501, the initial value of the WDT SFR 244 is set, and in step ST2502, the initial value of the SFR other than the WDT SFR 244 is set.

FIG. 26 is a timing chart showing the timing of the input / output signals of the reset control circuit 910 shown in FIG. 24 [¾]. In the figure, (: a;) is the reset signal input to the reset control circuit 910, (b) is the value of the reset determination flag 250, and (c) is the output from the WDT 234. (D) indicates a WDT SFR reset signal which is an output signal of the reset control circuit 910. When the reset signal becomes “L” at time T1 of the timing chart shown in FIG. 26, the reset judgment flag 250 is “11” level, and the WDT interrupt signal is “H”. When is

The SFR reset signal for WDT becomes “H”. On the other hand, if the WDT interrupt signal becomes “L” at time T 2, that is, if the WDT 234 detects a runaway of the CPU 210, the WD / SFR reset signal becomes “L”. A hardware reset of WDT 234 is performed.

In the above description, the output signal of the reset control circuit 910 is supplied only to the SFR 244 for WDT, but the reset signal from the reset IC 20 is also applied to other SFRs. The signal may be supplied instead of the signal.

As described above, according to the eighth embodiment, when the CPU 210 is running out of control by monitoring the WDT 234, a specific SFR is forcibly reset to achieve more stability. This has the effect that reset control with a certain level can be performed.

In the first to eighth embodiments described above, at least one of the reset ICs is provided in a part of the single-chip microcomputer. You may comprise. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention is applicable to, for example, a microcomputer used for controlling an electronic device.

Claims

The scope of the claims

1. A micro-combination unit in which a reset operation is performed by an external reset signal input from outside,

A central processing unit that performs overall processing of the microcomputer; a peripheral function unit that performs a predetermined operation;

A peripheral function register unit which can be reset in hardware, and which sets the operation of the peripheral function unit;

A first flag for storing information on whether or not the reset operation of the central processing unit by the input of the external reset signal is the first reset operation from the time when the microcomputer is turned on;

^ If the information stored in the first flag indicates that this is the first reset operation, reset the peripheral function register unit in hardware when an external reset signal is input. When the external reset signal is input when the information stored in the flag in step 1 indicates that the reset operation is not the first reset operation, the register reset signal is transmitted. And a reset control unit for executing reset control of the peripheral function register unit so as not to transmit

A microcomputer with reset control function.

2. The microcomputer according to claim 1, wherein the peripheral function unit includes an AD converter for converting an analog signal into a digital signal, and the peripheral function register unit includes the AD converter. A microphone-equipped computer that has a reset control function that includes a register for setting the operation of the mixer.

3. The microcomputer according to claim 1, wherein the peripheral function unit includes a DA converter for converting a digital signal to an analog signal, and the peripheral function register unit includes the DA converter. Register for setting the operation of D-A converter Micro computer that performs the reset control function including scanning.

4. The microcomputer according to claim 1, wherein the peripheral function unit includes a serial input / output device that performs serial signal input / output control, and the peripheral function register unit includes a serial input / output device of the serial input / output device. A microcomputer with a reset control function that includes registers for setting operations.

5. The microcomputer according to claim 1, wherein the peripheral function unit includes a timer for performing a timing function, and the peripheral function register unit includes a reset including a register for setting an operation of the timer. Microcomputer with a remote control function.

6. Claim 1. The microcomputer on its own, wherein the peripheral function unit monitors the runaway of the central processing unit and outputs a signal indicating runaway when it is determined that the central processing unit is running away. A microcomputer having a reset control function including a register for setting operation of the watch dog timer;

7. The microcomputer according to claim 6, wherein the reset control unit outputs the information stored in the first flag when the watchdog timer outputs a signal indicating indeterminate. Regardless, the microcomputer has a reset control function that sends a register reset signal and executes reset control of the peripheral function register.

8-The microcomputer according to claim 1, wherein

Flag-dependent mode for resetting peripheral function registers depending on the first flag, or flag-independent mode for resetting peripheral function registers without depending on the first flag The reset control unit further includes a second flag for storing information about whether the flag is a flag-independent mode or a flag-independent mode. When the reset signal is input, the information stored in the first flag of lW is Regardless, a micro computer that performs a reset control function of sending a register reset signal to the peripheral function register section.

9. A microcomputer supplied with a first power supply and a second power supply,

A central processing unit that performs overall processing of the microcomputer and is driven by the first and first power supplies;

Performing a predetermined operation, a peripheral device driven by the second power supply, a first reset signal generated from the first power supply, and a second reset generated from the second power supply A reset control unit for executing a reset control of the central processing unit by transmitting a signal for executing the reset of the central processing unit to the central processing unit only when both of the signals are input;

A microcomputer with reset control function.