USRE35520E - Interfacing device for a computer games system - Google Patents

Interfacing device for a computer games system Download PDF

Info

Publication number
USRE35520E
USRE35520E US08/174,700 US17470093A USRE35520E US RE35520 E USRE35520 E US RE35520E US 17470093 A US17470093 A US 17470093A US RE35520 E USRE35520 E US RE35520E
Authority
US
United States
Prior art keywords
processing unit
address
data
interfacing device
storage medium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/174,700
Inventor
Richard Darling
Edward A. Carron
David Darling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Codemasters Software Co Ltd
Original Assignee
Codemasters Software Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/530,617 external-priority patent/US5112051A/en
Application filed by Codemasters Software Co Ltd filed Critical Codemasters Software Co Ltd
Priority to US08/174,700 priority Critical patent/USRE35520E/en
Assigned to CODEMASTERS SOFTWARE COMPANY LIMITED reassignment CODEMASTERS SOFTWARE COMPANY LIMITED CHANGE OF ADDRESS Assignors: CODEMASTERS SOFTWARE COMPANY LIMITED
Application granted granted Critical
Publication of USRE35520E publication Critical patent/USRE35520E/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F13/00Video games, i.e. games using an electronically generated display having two or more dimensions
    • A63F13/20Input arrangements for video game devices
    • A63F13/23Input arrangements for video game devices for interfacing with the game device, e.g. specific interfaces between game controller and console
    • A63F13/02
    • A63F13/10
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F13/00Video games, i.e. games using an electronically generated display having two or more dimensions
    • A63F13/20Input arrangements for video game devices
    • AHUMAN NECESSITIES
    • A63SPORTS; GAMES; AMUSEMENTS
    • A63FCARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F13/00Video games, i.e. games using an electronically generated display having two or more dimensions
    • A63F13/45Controlling the progress of the video game

Definitions

  • This invention relates to computer games systems and it relates particularly to an interfacing device for modifying the manner in which a computer game is played.
  • a conventional computer games system typically includes a computer containing the main processing unit, a visual display unit (VDU) on which a game is displayed and which may constitute a part of the computer, some form of interactive unit (e.g. a keyboard or joystick) enabling a player or players to react to and influence events during the course of a game, and an external data storage medium (e.g. a game cartridge) that can be plugged into or otherwise connected to the main processing unit and that contains data defining the characteristics (e.g. the rules) or the particular game being played.
  • VDU visual display unit
  • some form of interactive unit e.g. a keyboard or joystick
  • an external data storage medium e.g. a game cartridge
  • the main processing unit is programmed to address different storage locations in the external data storage medium, whereby to access the stored data as it is needed.
  • the main processing unit generates an address identifying a respective storage location in the storage medium, and this address is routed to the storage medium on an address bus.
  • the processing unit sends a request signal to the storage medium, whereupon the data in the addressed storage location is accessed and then routed to the processing unit on a data bus.
  • the data stored in an external data storage medium determines the characteristics of the game stored therein and typically defines such game parameters as the number of playing units (e.g. cars, planes, etc.), the number of lives ascribed to individual players, the duration of particular events, time limits and speed settings, color and so on.
  • game parameters as the number of playing units (e.g. cars, planes, etc.), the number of lives ascribed to individual players, the duration of particular events, time limits and speed settings, color and so on.
  • an external data storage medium such as a cartridge with a read-only memory (ROM) and the like.
  • Another object of the invention is to provide an interfacing device for connecting a processing unit of a computer games system to an external dais storage medium, the interfacing device being capable of operating in various ways, either user-selected or preset, for modifying the rules of the game, thereby enhancing the playability of the game.
  • an interfacing device for connecting a processing unit of a computer games system to an external data storage medium so as to enable the processing unit to address, and receive data from, different storage locations in the external data storage medium, the interfacing device comprising means responsive to the processing unit for recognition of a selected address and means for modification of data processed by the processing unit in response to such recognition.
  • the user has the capability to substitute his own, user-generated data for that which would otherwise be supplied to the processor by the external data storage medium, and in this way the user can control and radically change the parameters or the game normally defined by the data stored in the external data storage medium and thereby enhance the "playability" of the game
  • the modification means comprises user-operable means for generating a first signal and a second signal representing the selected address and user-selected data respectively, means for comparing the selected address represented by the first signal with an address from the processor, and means for supplying the user-selected data to the processor, in substitution for the data in the addressed storage location of the external data storage medium if the compared addresses are the same.
  • the supplying means may be a semiconductor switching device responsive to an output from the comparing means.
  • a computer games system comprising a main processing unit, an external data storage medium and an interfacing device, in accordance with the first aspect of the invention, for interconnecting the main processing unit and the external data storage medium.
  • a method of playing a computer game using a computer games system having a processing unit and an external data storage medium, including the steps of comparing an address from the processing unit with a selected address and modifying data supplied to the processing unit whenever the compared addresses are the same.
  • the modifying of the data takes place only if the data from the external data storage medium matches data set by user-operable input means (which may be switches, keypad, joystick, etc.). In other words, the data is modified only if it is what the interface expects to find there.
  • user-operable input means which may be switches, keypad, joystick, etc.
  • the data is modified only if it is what the interface expects to find there.
  • Some large programs have “bank switching,” which means that several banks of data are stored at each address. This "data compare" feature of the invention ensures that only data at the correct address and the correct bank is modified.
  • FIGS. 1a, and 1b and 1c are respectively top plan, side and perspective views of an interfacing device in accordance with the invention.
  • FIG. 2 is a block diagram of circuitry used in the interfacing device of FIGS. 1a, 1b and 1c;
  • FIG. 3 shows the circuitry of FIG. 2 in more detail
  • FIG. 4a, 4b and 4c are respectively top plan, side and perspective views of another interfacing device in accordance with the invention.
  • FIG. 5 is a block diagram of circuitry used in the interfacing device of FIG. 4;
  • FIG. 6 is a block diagram of an alternative embodiment of the invention.
  • FIG. 7a, 7b and 7c are respectively top plan, side and perspective views of another embodiment of an interfacing device according to the invention.
  • FIG. 7d is a perspective view showing an embodiment of the present invention just prior to its connection to a game cartridge
  • FIG. 7e is a perspective view showing apparatus in accordance with the invention after it has been connected with a game cartridge to form an assembly;
  • FIG. 7f is a perspective view showing the assembly of FIG. 7e just prior to insertion in a games machine
  • FIG. 7g is a side elevation showing the apparatus after the insertion of the assembly of FIG. 7e in a games machine
  • FIG. 8a and 8b collectively form a block diagram of circuitry used in the interfacing device of FIGS. 7a, 7b and 7c;
  • FIG. 8c is a more detailed block diagram of a portion of the circuitry of FIG. 8a;
  • FIG. 8d is a more detailed block diagram of a portion of the circuitry of FIG. 8b;
  • FIG. 8e is a schematic diagram showing 16 character cell definitions achievable in a cell measuring 8 ⁇ 8 pixels wherein only each group of 4 ⁇ 4 pixels is selectable on or off;
  • FIG. 8f is a truth table relating the inputs and outputs of FIG. 8d to each other and to the 16 character cell definitions of FIG. 8e;
  • the interfacing device shown generally in FIGS. 1a, 1b and 1c comprises a shallow case 1 of which one end 2 is intended to fit into a receiving port of a computer games console such as the well-known Nintendo console and the opposite end 3 is intended to receive an external data storage medium (hereinafter referred to as a memory), such as a cartridge having a read-only memory (ROM).
  • a memory such as a cartridge having a read-only memory (ROM).
  • the case contains a printed circuit board 4 that carries interfacing circuitry, the board 4 being provided at each end thereof with suitable end connectors enabling the interfacing circuit to detachably interconnect the main processing unit of the games console and the external memory.
  • user-adjustable switches 5 set into the upper wall 6 of case 1 may be utilized to modify the manner in which a game stored in the memory is played.
  • six 16- position rotary switches are provided.
  • the interfacing circuitry comprises a main address but 11 for interconnecting the address bus 11' of the main processing unit and the address bus 11" of the external memory, whereby addresses can pass from the main processing unit to the memory.
  • the interfacing circuit has a main data bus 12 that interconnects the data bus 12' of the main processing unit and the data bus 12" of the external memory, whereby data can pass from the external memory to the main processing unit in response to received addresses, provided such data has not been blocked by circuitry (to be described) in the interfacing device.
  • the interfacing device has a user-operable selection unit 13 by which the user can generate a user-selectable address (A u ) and user-selectable data (D u ).
  • the user-selectable address (A u ) is routed on a subsidiary address bus 14 to one input I 1 of an address comparison circuit 15, and the user-selectable data (D u ) is routed on a subsidiary data bus 16 to an input of a data switching device 17.
  • addresses on the main address bus 11 (which are, of course, generated in the main processing unit) are routed to a second input I 2 of the address comparison circuit 15 for comparison with the user-selectable address (A u ) at the first input I 1 .
  • the address comparison circuit 15 If, however, the compared addresses are the same, the address comparison circuit 15 generates an actuation signal on line L causing the data switching device 17 to change its switching condition, blocking the transmission of data from the external memory and routing the user-selected data D u onto the main data bus 12 for onward transmission to the main processing unit.
  • the user-selected data generated by selection unit 13 is substituted for data from the respective storage location of the memory upon recognition of an address selected by the user.
  • the user has set the user-selectable address A u at a value 1002 (which location contains "7") and the user-selectable data D u at a value "3".
  • the selected address and data are normally encoded n accordance with a hexadecimal coding format, though of course this is not a requirement.
  • the current address from the processing unit is 1001, say, it is not recognized by the address comparison circuit 15 and so the data held on the addressed storage location of the external memory (i.e. that corresponding to address 1001) is routed to the main processing unit on the main data bus 12.
  • the stored data supplied to the processing unit in this way might have the value "9", say, different from the value of the user-selected data.
  • the current address from the processing unit is the same as that selected by the user, then the user-selected data, having the value "3", is supplied to the processing unit in substitution for the data stored in the addressed storage location of the external memory.
  • the alternative data values ("3" and "7") may represent the number of lives ascribed to a player and so, by changing the value from "7" (the value stored in the external memory) to a different value ("3" in this example), the user has the capability to modify (increase in this example) the difficulty of the game to a desired extent.
  • FIG. 3 shows the interfacing circuit in somewhat more detail.
  • the main address and data buses, which interconnect the main processing unit and the external memory, are again referenced at 11 and 12 respectively, and a data request bus is shown at 18.
  • the user-controllable selection unit 13 comprises two banks 21, 22 of user-selectable switches, one 21 of the banks comprising switches A ⁇ VietnameseA14 for setting the user-selectable address A u and the other 22 of the banks comprising switches D ⁇ VietnameseD7 for setting the user-selectable data D u .
  • the user-selectable address and data signals can alternatively be held in latches.
  • many types of data entry system e.g. keypad, voice input
  • the data switching device 17 comprises three identical integrated-circuit data switches 23(1), 23(2), 23(3) (Ref. No. 74HC4053P) which are connected, as shown, to the external memory and to the bank of switches 22 by the main and subsidiary data buses 12 and 16, respectively.
  • the address comparison circuit 15 comprises two identical integrated circuits 24(1), 24(2) (Ref. No: 74LS684N) that are connected, as shown, to the main processing unit and the bank of switches 21 by the main and subsidiary address buses 11, 14 respectively, and an integrated OR gate 25 (Ref. No.: 74LS32) is provided to effect an change in the switching condition of the device 17 in response to recognition by the address comparison circuit 15 of an address selected by the user.
  • the interfacing device utilizes preselected addresses and preselected data.
  • FIGS. 4 and 5 is similar to that shown in FIGS. 1 to 3, and common components are given like reference numerals.
  • the user operable switch (shown at 13 FIGS. 2 and 3) is replaced by an internal memory in the form of a read-only memory (ROM) 40.
  • ROM read-only memory
  • the subsidiary address bus 14 connects the address output of the ROM 40 to a 24-bit address comparison circuit 15 via two address latches 41 and 42 that are connected in parallel, and the subsidiary data bus 16 connects the data output from the ROM 40 to the input of an 8-bit buffer 43 via a further latch 44.
  • the output of the buffer 43 is connected to the main data bus 12, which, as shown, also incorporates an 8-bit buffer 45.
  • Both buffers 43 and 45 are controlled by an address comparison signal L generated by the address comparison circuit 15, whereby data is selectively routed to the processing unit either on the main data bus 12 or on the subsidiary data bus 16, depending on the result of a comparison carried out in the address comparison circuit.
  • Latches 41 and 42 are set to hold the high and low bytes respectively of a preselected, two-byte (16-bit) address A p transmitted thereto from the ROM 40 over the subsidiary address bus 14.
  • the latch 44 is set to hold pre-selected data D p (corresponding to the preselected address A p in the latches 41 and 42) transmitted thereto from the ROM 40 over the subsidiary data bus 16.
  • the preselected address A p held in the latches 41 and 42 is compared with the current addresses transmitted from the processing unit over the main address bus 11.
  • the address comparison signal L goes high, thereby maintaining the buffer 43 (which is supplied via an inventor 43a) closed and the buffer 45 (which is supplied via a logical AND gate 46) open and allowing data to pass directly from the external memory to the processing unit over the main data bus 12.
  • the address comparison signal L goes low, thereby maintaining the buffer 43 open and the buffer 45 closed and enabling the preselected data D p held in the latch 44 to pass to the processing unit in substitution for the data in the external memory.
  • the interfacing device has the capability to modify data received from any one of a range of different external data storage media (containing different computer games) that can be plugged into the device.
  • the ROM 40 (.Iadd.a data source.Iaddend.) stores a plurality of different pre-selected addresses together with a corresponding plurality of different preselected data, and each preselected address is utilized in conjunction with the corresponding preselected data to modify the data from a respective external memory.
  • the interfacing device in order to access the correct preselected address (and data) to the latches, to enable address comparison and (possible) data substitution to take place, the interfacing device must be capable of identifying which external memory has been plugged into its receiving port.
  • additional control circuitry is provided that, in effect, enables the interfacing device to interrogate two data bytes of the external memory.
  • the identification procedure is controlled by means of a controller 50 that is clocked by a counter 51 operating in conjunction with a clock circuit 52 and a "power-on" timing circuit 53.
  • the counter 51 is initialized and the external memory is isolated from the processing unit (by setting input A of the AND gate 46 low).
  • the controller 50 then transmits successive control signals to the ROM 40 on a control bus 54, causing the high and low bytes of the first address stored in the ROM 40 (corresponding to the first data byte for identification in the external memory) to be routed to the latches 55 and 56 respectively.
  • the latches 55 and 56 which are connected to the external memory via the main address bus 12, are set to hold the first address (corresponding to the first data byte in the external memory).
  • the first data byte is transferred from the external memory to an encoder 57 (the main data bus 12 being blocked by the buffer 46), where it is latched. This procedure is repeated for the second data byte for identification in the external memory, which is also transferred to, and latched in, the encoder 57.
  • the encoder 57 then performs preset, logical operations on the first and second latched data bytes and generates an output that uniquely identifies the external memory. This output is held in a ROM latch 58 (which had previously held a zero data field), and the encoder 57 is then disabled.
  • the controller 50 selects from the ROM 40 the pre-selected address (and the preselected data) appropriate for the external memory represented by the output held in the ROM latch 58 and causes the high and low bytes of this preselected address to be transferred to the latches 41 and 42 respectively and the required preselected data to be transferred to the latch 44.
  • the address comparison circuit 15 compares the latched, preselected address with the current addresses from the processing unit. However, the address comparison circuit 15 also compares current data transmitted from the external memory over the main data bus with data held in a fourth latch 47.
  • the latched data (which is also derived from the ROM 40) is chosen to be the same as the data (from the external memory) which is to be replaced by the preselected data held in the latch 44. This additional comparison ensures substitution of the correct data and prevents errors which could arise as a result of an ambiguity in the process of comparing addresses.
  • the ROM 40 may have a number of different data banks, and so the data and address associated with each external memory may have a number of alternative values.
  • a user-operable switch 59 may be provided, enabling the user to select a desired data bank from the ROM 40 and thereby select a desired effect, e.g. a desired degree of difficulty (hard, medium or easy, say) with which the game is to be played.
  • each preselected address is allocated to a respective external memory.
  • more than one of the preselected addresses can be allocated to the same external memory, thereby enabling more than one aspect of a game to be changed.
  • an interfacing device for a computer games machine connects to the external program cartridge and the computer games machine allows the program cartridge to function normally except for one or more modifications performed by the interface.
  • FIG. 6 is the same as the other embodiments.
  • the interface allows the program to execute normally but interrupts the processor at a particular point or points (user-selected or preset) in the program.
  • the interface banks its own ROM into the processor's memory and executes a piece of code. This code is such that a modification is effected on the games computer's internal memory.
  • This interface then banks its own ROM out and allows the computer to continue executing the game as if nothing had happened.
  • This process allows a user or a preset ROM to change many of the variables that control aspects of a game, modifying the game in countless different ways.
  • the device 70 is an interface between a games computer (via edge connector 71) and a plug-in game cartridge external memory (via edge connector 72).
  • the address comparator circuit 73 compares the value on the address bus 74 with a preset value, in this case a value supplied on a bus 75 from registers 1 and 2.
  • the computer accesses the external memory unhindered.
  • a switch circuit 76 which in a practical embodiment may be a semiconductor device.
  • the ROM 77 can then make changes to the RAM and other registers housed in the computer (or in the interface 70) to effect changes in the way the program operates.
  • the switch 76 then reverses and re-enables the external memory by switching the output enable line 80 back to connect from the computer to the external memory through the extension 80a. In this example this is done by way of register 3, which controls control line B.
  • the external memory programs When the external memory programs (games) are running on a computer, they constantly use the computer's internal RAM as a temporary scratch-pad for storing values that change. These values are typically used for parameters such as number of lives remaining, current level number, counters for timing loops (speed). number of cars, etc.
  • the user--or the programmer of the ROM 77--can change these values in response to reaching a particular point in the program.
  • FIGS. 7a, 7b and 7c are respectively top plan, side and perspective vies of another embodiment of an interfacing device according to the invention. These figures show the best mode contemplated by the inventors for putting the invention into practice.
  • the device comprises, as in the embodiments described above, a case 1 of which one end 2 is intended to fit within a receiving port of a computer games console and the opposite end 3 is intended to receive an external data storage medium or memory, such as a cartridge having a read-only memory or ROM.
  • the case contains, as in the embodiments described above, a printed circuit board 4 that carries interfacing circuitry, the board 4 being provided at each end thereof with suitable end connectors enabling the interfacing circuit to detachably interconnect the main processing unit of the games console and the external memory.
  • a handle portion H of generally triangular construction (as viewed from above) has an inclined portion I, a stop S, and a concave thumb rest TR provided with ridges R.
  • the external data storage medium is connectable to the interfacing device in such a manner as to be positioned underneath the handle portion H.
  • the concave thumb rest TR formed on the upper surface of the handle portion H an assembly of the interfacing device and the external data storage medium can conveniently be grasped with a thumb engaging the thumb rest TR and fingers engaging the external data storage medium for connection of the assembly to the processing unit of a computer games system.
  • the protruding thumb rest TR and particularly the stop S thereof, prevents inadvertent insertion of the assembly of the interfacing device and game cartridge into the computer games machine in a n upside-down relation, since the stop S will in case of such an attempted erroneous insertion latch on the lower rim of the cartridge-receiving opening into the games machine.
  • FIG. 7d is a perspective view showing a "game X," which can be any conventional game cartridge, about to be assembled with the device according to the invention.
  • FIG. 7e shows the game cartridge and the device according to the invention in assembled relation
  • FIG. 7f shows the assembly about to be inserted into a games machine, for example a Nintendo machine.
  • the assembly is conveniently grasped with the thumb of the user in the thumb rest TR and the fingers of the user below the game cartridge. The assembly is inserted and appears then as in FIG. 7g, with the lid of the games machine resting on the thumb rest TR.
  • the printed circuit board 4 is thicker than normal, to allow the edge connector to make good contact with the games machine connector without the need for the interface to be pushed down fully in the normal way. That is, the printed circuit board 4 has sufficient thickness that the connection of the assembly or the interfacing device and game cartridge to the processing unit of the computer games machine can be effected with a movement that is rectilinear. This enables the unit to be made smaller overall and more elegant than it would otherwise be.
  • FIGS. 8a-8c The circuitry incorporated in the device of FIGS. 7a-7g is illustrated in FIGS. 8a-8c.
  • the circuitry shown in these figures has two modes or operation.
  • Mode 1 is a latch-setting mode, wherein values for the address comparison, data comparison, and data replacement functions are set by the user.
  • Mode 2 is an active mode, very similar to the operation of the embodiments described above, wherein the address comparators (as well as data comparators) send a signal to a data replacement unit to effect a replacement of the data when the conditions for data replacement are met.
  • the selection of mode 1 or mode 2 is made by an output signal from a control latch 103 on a mode select line 102.
  • a CE line 92 that comes from the computer edge connector 71 (for example from a video games machine made by Nintendo) is connected to the CE selector 90, which is controlled by the signal on the line 102.
  • the line 92 would normally connect directly to the external memory, allowing it to respond to data read/write requests from the video games machine.
  • the signal on the line 92 is passed either to the external memory 93 via a CE' line 94 or to an interface ROM 96 via a CE" line 98, depending on the state or the line 102. In this way, either the external memory 93 or the interface ROM 98 is made active.
  • the circuitry also has a power-on circuit 100, which ensures that the line 102 from the control latch 103 is set to the latch setting mode when the power is first turned on.
  • the purpose of this mode is to allow the user to select the address comparison data and replacement data.
  • the program in the ROM 96 is designed in such a way that it will accept input from the normal game control pad, operated by the user, and use it to move an on-screen pointer around the screen. Also on the screen there are 16 different letters (which represent values). The user can move the pointer to any of these letters and select them using a button oh the game control pad. By repeating this process the user can enter this data to represent addresses, comparison data bytes and replacement data bytes, as well as function enable/disable information.
  • the software stores the data entered by the user in the latches in each of the comparison/replacement units 1, 2 and 3 as well as in a control latch 103.
  • the external memory has control of the CPU and the game will function normally, with the exception of any data replacement operations performed by the interface.
  • the comparison/replacement units are now active, provided that the appropriate bit in the control latch has been set to enable them.
  • FIGS. 8a, 8b and 8c The structure illustrated in FIGS. 8a, 8b and 8c includes an address bus 104 connected to comparison/replacement units 1, 2 and 3 and a data bus 105 connected to the same units.
  • the address and data buses connect to the games machine, and at the right to the game cartridge that is currently in use.
  • a read/write line 106 is connected to the comparison/replacement units 1, 2 and 3, to the ROM 96 and to the video games machine and the particular game cartridge in use.
  • the chip enable line 92 is connected to the chip enable or CE selector 90 as described before and also to the comparison/replacement units 1, 2 and 3.
  • the address and data buses 104, 105 are also connected to the ROM 96, and the address bus 104 is connected to a register address decoder 107.
  • the latter produces three outputs which go respectively to inputs R.SELO...3 of each of the comparison/replacement units 1, 2 and 3.
  • R.SELO...3 inputs
  • FIG. 8c shows, the latter input goes to a replacement data latch 0-7, a comparison data latch 0-7, a comparison address latch 0-7, and a comparison address latch 8-14.
  • the data bus 105 also connects to the control latch 103, which produces the output on the line 102 to the CE selector, as noted above.
  • the output on the line 102 also goes to the register address decoder 107 and to an output to FIG. 8b labeled G.CONT (graphics control).
  • the control latch 103 produces an output to an input labeled R.EN on each of the comparison/replacement units 1, 2, and 3 and an output to an input labeled DC.EN on each of the comparison/replacement units 1, 2 and 3.
  • Each of the comparison/replacement units 1, 2 and 3 produces an output on a terminal labeled REP ("replace") which is supplied to the CE selector 90.
  • the graphics address 0-12 bus is connected to a graphics generator 110, which produces an output to a graphic output buffer 111.
  • a device selector 112 receives inputs from the G.CONT terminal and from a G CE terminal and produces outputs to the graphic output buffer 111 and the G CE terminal of the game cartridge.
  • the graphics lines GWE and GOE connect through FIG. 8b from the games machine to the game cartridge in use, and the latter line connects also to the graphic output buffer 111.
  • the replacement data latch 0-7 connects to an 8 bit buffer 115.
  • An 8-bit comparator 116 receives comparison inputs from the data line D0-7 and the comparison data latch 0-7 and produces an output signal to a control 117 when the inputs are equal.
  • a fifteen bit comparator 118 receives at one input an output from the comparison address latch 0-7 and an output from the comparison address latch 8-14 and at the other input data from the address line 0-14. It produces a control output to the control 117 when the inputs are equal.
  • the control 117 also receives signals from the R.EN, read/write, chip enable, DC.EN and F.EN terminals. Its output controls the 8-bit buffer 115 and is also supplied to the output terminal REP.
  • Certain computer games devices for example one made by Nintendo, normally generate a screen display by reading data from a graphics ROM. This data defines the bit patterns that make up the letters and graphical shapes that appear on the screen.
  • the screen is made up of many character- or letter-sized squares (or rectangles), called character cells, which are 8 by 8 pixels (picture elements, or dots) in size. Each pixel is defined by 2 bits in memory, representing one of four colors.
  • graphics ROM is a minimum of 8K bytes in size, giving 512 different character cell definitions, as is needed for a normal game. This allows the system to produce colorful, detailed and varied graphics displays.
  • the device of FIGS. 8a-8d When in its latch setting mode, the device of FIGS. 8a-8d needs to use the screen for display purposes. Specifically, it needs to display the 16 letters for the user to choose from, the selected letters, and the product name at the top of the screen. It has been found it is not necessary to use the full capability of the normal graphic system, and that the complexity, size and cost of the device can be reduced by eliminating the graphics ROM chip normally required.
  • a simple circuit emulates a graphics ROM containing the 16 character cell definitions (FIG. 10b). Even though the graphics produced with this system are cruder (only each group of 4 by 4 pixels is selectable on or off, instead of each pixel being individual selectable) it is perfectly adequate for the purpose of displaying the 16 letters, selected letters and product name.
  • FIG. 8d a small circuit is added to the circuitry needed for the rest of the device.
  • the circuit of FIG. 8d has a negligible cost and size, in contrast to the substantial cost and size of the separate ROM which would otherwise be required.
  • a conventional computer games device such as one made by Nintendo is designed specifically to get its graphics data from external memory (ROM or RAM).
  • ROM or RAM external memory
  • FIG. 8d shows the inputs to the graphic generator 110 on lines GA 2, GA 4, GA 5, GA 6 and GA 7 and outputs on lines GD 0, GD 1, GD 2, GD 3, GD 4, GD 5, GD 6 and GD 7 plus a select input G.OE and C.CE'.
  • the graphic generator 110 includes four AND gates 201, 202, 203, 204, two OR gates 205, 206 and an invertor 207. If the input GA 2 is high, the OR gate 205 is high only if the input GA 4 is high and the OR gate 206 is high only if the input GA 5 is high. On the other hand, if GA 2 is low, then the OR gate 205 is high only if Ga 6 is high and the OR gate 206 is high only if GA 7 is high.
  • the object of the circuitry in FIG. 8d is to produce the 16 character bit patterns of FIG. 8e, these patterns being numbered respectively 0-15. Since 4 ⁇ 4 pixels are addressed as a unit, there is a sacrifice of resolution, as indicated above, but, for reasons also indicated above, it is of no particular consequence.
  • a space that is not blackened corresponds to "0”
  • a space that is blackened corresponds to "1”. There is, of course, only one combination of all "1's”. These two possibilities correspond to "0" and "15", respectively, in FIG. 8e.
  • FIG. 8f is a truth table showing the address lines in a logical order and the data values they produce to make the 16 character shapes.
  • all address line combinations are shown in binary order. Of course, the order can be changed and is not critical.
  • the character bit patterns produced can be viewed with the left side of FIG. 8f up to see the character shapes from the same perspective as in FIG. 8e.
  • the input line GA 2 is set to "0" it designates the top half of the pattern and when set to "1" designates the bottom half.
  • the OR gate 205 produces an output which is supplied to the four input terminals of the buffer 111 that relate to the output lines GD 4-GD 7, and the OR gate 206 produces an output which is supplied to the four input terminals of the buffer 111 that relate to the outputs GD 0-GD 3.
  • the inputs GA 4-GA 7 of respectively “1", “0", “0”, “0” correspond to no shading in the third quadrant of the output; but when GA 2 changes to "1", the same inputs GA 4-GA 7 of "1", "0", “0", “0” corresponds to shading in the third quadrant.
  • the inputs GA 2 and GA 4-GA 7 shown in FIG. 8f produce the outputs on GD 0-GD 7 shown in FIG. 10f to form all of the bit patterns "0" through "15". These patterns are shown more pictorially in FIG. 8e.
  • FIGS. 9a, 9b and 9c when taken together form a flowchart showing the process performed with the aid of the circuitry of FIGS. 8a-8d.
  • steps 201 and 202 are performed by the power-on circuit, steps 203-213 by the interfacing ROM, steps 214 and 215 by the program in the internal memory of the games machine, and steps 217-227 by the interfacing ASIC.
  • the process moves to step 202, wherein the control latch defaults to a value which sets the CE selector 90 so as to enable the ROM 96 on line CE" 98.
  • the process then moves to step 203, wherein the ROM 96 begins execution and the screen in accordance with the invention appears on the display screen on which the game is displayed.
  • the program in the ROM determines whether the user has pressed a button on the control pad. If the user is not pressed such a button, the program loops back and makes the determination repeatedly until it is found that user has pressed a button on the control pad. When an affirmative determination is made, the program moves to step 205, wherein a determination is made whether a movement button has been pressed by the user. If so, then at step 206 the program moves the cursor to a new letter and then reverts to step 204. If no movement button has been pressed, the program determines whether a fire button has been pressed by the user. If so, the program causes display of the letter under the cursor on the screen as a selected letter and then loops back to step 204. If the fire button is not found to have been pressed, the program determines at step 209 whether the start button has been pressed. If not, the program loops back to step 204.
  • the program converts the selected letters (if any) to hexadecimal values which represent data to be stored in the latches.
  • the program then stores hexadecimal values in latches corresponding to the addresses, data replacement values, and data compare values (if any).
  • a program is transferred to the control deck's internal RAM.
  • control is passed to the program in the RAM.
  • the program in internal memory stores a value in the control latch with the CE selector bit set so as to enable the external memory on the line CE' 94 (FIG. 8a) and conditionally enable the comparison/replacement units 1, 2, 3 and disable graphic emulation.
  • control is passed to the reset address of the external memory and, at step 216, the game program begins execution.
  • the device determines whether the game control is requesting a read from the external memory. If not, it loops back until an affirmative determination is made. When an affirmative determination is made, the device determines whether the value of the address bus corresponds to the address stored in one or the comparison/replacement units 1, 2 and 3. If not, the process loops back to step 217. When an affirmative determination is made, the process advances to step 219 (FIG. 9c).
  • step 219 a determination is made whether the corresponding comparison/replacement function is enabled. If not, the process loops back to step 217.
  • step 220 a determination is made whether the corresponding data comparison function is enabled. If it is determined that the function has been enabled, the process advances to step 221, where a determination is made whether the value of the data bus corresponds to the comparison data stored in the corresponding address/comparison unit. If no such correspondence is found, the process loops back to step 217.
  • step 220 If at step 220 the corresponding data comparison function is not enabled, or if at step 221 the value of the data bus is found to correspond to the comparison data stored in the corresponding data and comparison latch, the process moves to step 222.
  • the external memory is prevented from outputting data by setting the CE selector to disable the line CE' 94 (FIG. 8a) via the terminal REF.
  • the corresponding comparison/replacement unit is set to output the data stored in its data replacement latch to the data bus.
  • step 225 a determination is made whether the read cycle is finished. If not the process stays in the loop at step 225 until it is determined that the read cycle is finished. When the read cycle is finished, the process advances to step 226. At step 226, the corresponding comparison/replacement unit is prevented from outputting data. Then, at step 227, the external memory is re-enabled by enabling the line CE' 94 (FIG. 8a). The process then loops back to step 217 in FIG. 9b.
  • each instruction consists of two or three bytes. An explanation of the function of each instruction is given in the right-hand column.
  • This section of the program causes a unit, e.g. a plane or car, to move at a particular speed.
  • a unit e.g. a plane or car
  • This section of the program causes the subroutine "MOVE UNIT" to be executed when the program steps corresponding to addresses 3000 to 3003 have been executed 50 times.
  • the interfacing device sets the selected address at 3006 and sets the selected data value at 10, then the value 50 in variable "A" in the processor (the value in the corresponding storage location of the memory) is replaced by the user-selected value (10 in this example).
  • This causes the subroutine "MOVE UNIT" to be executed when the program steps corresponding to addresses 3000 to 3003 have been executed 10 times instead of 50 times.
  • This number of laps required to be completed by the player is set at the value 3 derived from the addressed storage location of the memory. If, therefore, the interfacing device sets the selected address at 2005 and sets the selected data value at 7, say, then the value 3 in variable A in the processor (the value derived from the memory) is replaced by the designated value, 7 in this example.
  • changes can alternatively, or additionally, be made to the instructions themselves, e.g. to change an instruction to increase a value to an instruction, to decrease a value, to change an instruction to perform a particular task to one that requires no action, to change a branch instruction (BEQ to BNE, say), and so on.
  • the described embodiments enable recognition of a single address and substitution of data corresponding thereto, the invention also embraces recognition of two or more different addresses and substitution of the respective data corresponding thereto.
  • the device can alternatively be incorporated into the processing unit as an integral part thereof.

Abstract

An interfacing device for connecting the processing unit of a computer games system to an external data storage medium has a user-operable selection unit for generating a user-selected address and user-selected data. The user-operable selection unit may comprise user-operable switches or electronic latches that are set by a program in response to selections made by the user by means of a joystick, keypad or any other input device. An address comparison unit compares the user-selected address with the addresses from the processing unit, and a data switching device causes the user-selected data to be substituted for data in the storage medium whenever the compared addresses are the same. Instead of a user-operable selection unit, preselected addresses and preselected data may be stored in a ROM, which in one embodiment changes the way the computer interprets external memory and in another changes the computer's internal memory itself.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer games systems and it relates particularly to an interfacing device for modifying the manner in which a computer game is played.
2. Description of the Prior Art
A conventional computer games system typically includes a computer containing the main processing unit, a visual display unit (VDU) on which a game is displayed and which may constitute a part of the computer, some form of interactive unit (e.g. a keyboard or joystick) enabling a player or players to react to and influence events during the course of a game, and an external data storage medium (e.g. a game cartridge) that can be plugged into or otherwise connected to the main processing unit and that contains data defining the characteristics (e.g. the rules) or the particular game being played.
In general terms, the main processing unit is programmed to address different storage locations in the external data storage medium, whereby to access the stored data as it is needed.
To that end, the main processing unit generates an address identifying a respective storage location in the storage medium, and this address is routed to the storage medium on an address bus. When the stored data is required, the processing unit sends a request signal to the storage medium, whereupon the data in the addressed storage location is accessed and then routed to the processing unit on a data bus.
The data stored in an external data storage medium determines the characteristics of the game stored therein and typically defines such game parameters as the number of playing units (e.g. cars, planes, etc.), the number of lives ascribed to individual players, the duration of particular events, time limits and speed settings, color and so on.
Generally, computer games require the players to complete various tasks (e.g. to complete a fixed number of laps of a track), and failure to complete a task satisfactorily results in some cases in the elimination of a player from the game. In many games, the players may be ascribed more than one "life," and this can affect the difficulty, or ease, with which the game is played.
With existing systems, the characteristics of a game, and in particular its degree of difficulty, are to a large extent predetermined by the data stored in the external data storage medium. Consequently, existing computer games tend to lose their appeal and present less of a challenge to the player the more times they are played--that is to say the games have limited "playability."
OBJECTS AND SUMMARY OF THE INVENTION
It is an object or the present invention to alleviate the aforementioned shortcomings of existing computer games systems that use an external data storage medium such as a cartridge with a read-only memory (ROM) and the like.
Another object of the invention is to provide an interfacing device for connecting a processing unit of a computer games system to an external dais storage medium, the interfacing device being capable of operating in various ways, either user-selected or preset, for modifying the rules of the game, thereby enhancing the playability of the game.
The foregoing and other objects of the invention are attained by the provision of an interfacing device for connecting a processing unit of a computer games system to an external data storage medium so as to enable the processing unit to address, and receive data from, different storage locations in the external data storage medium, the interfacing device comprising means responsive to the processing unit for recognition of a selected address and means for modification of data processed by the processing unit in response to such recognition.
With an interfacing device constructed in accordance with the invention, the user has the capability to substitute his own, user-generated data for that which would otherwise be supplied to the processor by the external data storage medium, and in this way the user can control and radically change the parameters or the game normally defined by the data stored in the external data storage medium and thereby enhance the "playability" of the game
In a particular embodiment of the invention, the modification means comprises user-operable means for generating a first signal and a second signal representing the selected address and user-selected data respectively, means for comparing the selected address represented by the first signal with an address from the processor, and means for supplying the user-selected data to the processor, in substitution for the data in the addressed storage location of the external data storage medium if the compared addresses are the same.
The supplying means may be a semiconductor switching device responsive to an output from the comparing means.
In accordance with another aspect of the invention, there is provided a computer games system comprising a main processing unit, an external data storage medium and an interfacing device, in accordance with the first aspect of the invention, for interconnecting the main processing unit and the external data storage medium.
According to a yet further aspect of the invention there is provided a method of playing a computer game using a computer games system having a processing unit and an external data storage medium, including the steps of comparing an address from the processing unit with a selected address and modifying data supplied to the processing unit whenever the compared addresses are the same.
In accordance with another aspect of the invention, the modifying of the data takes place only if the data from the external data storage medium matches data set by user-operable input means (which may be switches, keypad, joystick, etc.). In other words, the data is modified only if it is what the interface expects to find there. Some large programs have "bank switching," which means that several banks of data are stored at each address. This "data compare" feature of the invention ensures that only data at the correct address and the correct bank is modified.
BRIEF DESCRIPTION OF THE DRAWING
Interfacing devices embodying the present invention are now described, by way of example only, with reference to the accompanying drawings, in which:
FIGS. 1a, and 1b and 1c are respectively top plan, side and perspective views of an interfacing device in accordance with the invention;
FIG. 2 is a block diagram of circuitry used in the interfacing device of FIGS. 1a, 1b and 1c;
FIG. 3 shows the circuitry of FIG. 2 in more detail;
FIG. 4a, 4b and 4c are respectively top plan, side and perspective views of another interfacing device in accordance with the invention;
FIG. 5 is a block diagram of circuitry used in the interfacing device of FIG. 4;
FIG. 6 is a block diagram of an alternative embodiment of the invention;
FIG. 7a, 7b and 7c are respectively top plan, side and perspective views of another embodiment of an interfacing device according to the invention;
FIG. 7d is a perspective view showing an embodiment of the present invention just prior to its connection to a game cartridge;
FIG. 7e is a perspective view showing apparatus in accordance with the invention after it has been connected with a game cartridge to form an assembly;
FIG. 7f is a perspective view showing the assembly of FIG. 7e just prior to insertion in a games machine;
FIG. 7g is a side elevation showing the apparatus after the insertion of the assembly of FIG. 7e in a games machine;
FIG. 8a and 8b collectively form a block diagram of circuitry used in the interfacing device of FIGS. 7a, 7b and 7c;
FIG. 8c is a more detailed block diagram of a portion of the circuitry of FIG. 8a;
FIG. 8d is a more detailed block diagram of a portion of the circuitry of FIG. 8b;
FIG. 8e is a schematic diagram showing 16 character cell definitions achievable in a cell measuring 8×8 pixels wherein only each group of 4×4 pixels is selectable on or off;
FIG. 8f is a truth table relating the inputs and outputs of FIG. 8d to each other and to the 16 character cell definitions of FIG. 8e; and
FIGS. 9a, 9b and 9c when taken together form a flow chart showing the steps of a process performed with the aid of the circuitry of FIGS. 8a-8d.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The interfacing device shown generally in FIGS. 1a, 1b and 1c comprises a shallow case 1 of which one end 2 is intended to fit into a receiving port of a computer games console such as the well-known Nintendo console and the opposite end 3 is intended to receive an external data storage medium (hereinafter referred to as a memory), such as a cartridge having a read-only memory (ROM).
The case contains a printed circuit board 4 that carries interfacing circuitry, the board 4 being provided at each end thereof with suitable end connectors enabling the interfacing circuit to detachably interconnect the main processing unit of the games console and the external memory.
As will become clear hereinafter, in this embodiment of the invention user-adjustable switches 5 set into the upper wall 6 of case 1 may be utilized to modify the manner in which a game stored in the memory is played. In the illustrated example, six 16- position rotary switches are provided.
As FIG. 2 shows, the interfacing circuitry comprises a main address but 11 for interconnecting the address bus 11' of the main processing unit and the address bus 11" of the external memory, whereby addresses can pass from the main processing unit to the memory.
Similarly, the interfacing circuit has a main data bus 12 that interconnects the data bus 12' of the main processing unit and the data bus 12" of the external memory, whereby data can pass from the external memory to the main processing unit in response to received addresses, provided such data has not been blocked by circuitry (to be described) in the interfacing device.
The interfacing device has a user-operable selection unit 13 by which the user can generate a user-selectable address (Au) and user-selectable data (Du). The user-selectable address (Au) is routed on a subsidiary address bus 14 to one input I1 of an address comparison circuit 15, and the user-selectable data (Du) is routed on a subsidiary data bus 16 to an input of a data switching device 17. As FIG. 2 shows, addresses on the main address bus 11 (which are, of course, generated in the main processing unit) are routed to a second input I2 of the address comparison circuit 15 for comparison with the user-selectable address (Au) at the first input I1.
If the compared addresses are different, data from the external memory is routed, via the switching device 17, onto the main data bus 12 for onward transmission to the main processing unit.
If, however, the compared addresses are the same, the address comparison circuit 15 generates an actuation signal on line L causing the data switching device 17 to change its switching condition, blocking the transmission of data from the external memory and routing the user-selected data Du onto the main data bus 12 for onward transmission to the main processing unit.
By this means, the user-selected data generated by selection unit 13 is substituted for data from the respective storage location of the memory upon recognition of an address selected by the user.
This substitution may be illustrated by the following simple example.
It will be assumed that the user has set the user-selectable address Au at a value 1002 (which location contains "7") and the user-selectable data Du at a value "3". In tact, as will be described hereinafter, the selected address and data are normally encoded n accordance with a hexadecimal coding format, though of course this is not a requirement.
If the current address from the processing unit is 1001, say, it is not recognized by the address comparison circuit 15 and so the data held on the addressed storage location of the external memory (i.e. that corresponding to address 1001) is routed to the main processing unit on the main data bus 12. The stored data supplied to the processing unit in this way might have the value "9", say, different from the value of the user-selected data.
If, on the other hand, the current address from the processing unit is the same as that selected by the user, then the user-selected data, having the value "3", is supplied to the processing unit in substitution for the data stored in the addressed storage location of the external memory.
The alternative data values ("3" and "7") may represent the number of lives ascribed to a player and so, by changing the value from "7" (the value stored in the external memory) to a different value ("3" in this example), the user has the capability to modify (increase in this example) the difficulty of the game to a desired extent.
FIG. 3 shows the interfacing circuit in somewhat more detail. The main address and data buses, which interconnect the main processing unit and the external memory, are again referenced at 11 and 12 respectively, and a data request bus is shown at 18.
The user-controllable selection unit 13 comprises two banks 21, 22 of user-selectable switches, one 21 of the banks comprising switches Aφ.....A14 for setting the user-selectable address Au and the other 22 of the banks comprising switches Dφ.....D7 for setting the user-selectable data Du.
The switching arrangement shown in appropriate to generate binary address and data signals encoded in accordance with the hexadecimal coding formal and can in practice be embodied as respectively four and two 16-position rotary, or alternatively configured, switches. Alternatively, a preset plug-in pin connection package can be substituted for the arrangement of switches.
The user-selectable address and data signals can alternatively be held in latches. In this case many types of data entry system (e.g. keypad, voice input) can be used to set the latches.
The data switching device 17 comprises three identical integrated-circuit data switches 23(1), 23(2), 23(3) (Ref. No. 74HC4053P) which are connected, as shown, to the external memory and to the bank of switches 22 by the main and subsidiary data buses 12 and 16, respectively.
The address comparison circuit 15 comprises two identical integrated circuits 24(1), 24(2) (Ref. No: 74LS684N) that are connected, as shown, to the main processing unit and the bank of switches 21 by the main and subsidiary address buses 11, 14 respectively, and an integrated OR gate 25 (Ref. No.: 74LS32) is provided to effect an change in the switching condition of the device 17 in response to recognition by the address comparison circuit 15 of an address selected by the user.
While the described embodiment enables recognition of a single address and substitution of data corresponding thereto, the invention also embraces recognition of two or more different addresses and substitution of the respective data corresponding thereto.
In another embodiment of the invention, shown in FIGS. 4 and 5, the interfacing device utilizes preselected addresses and preselected data.
The embodiment shown in FIGS. 4 and 5 is similar to that shown in FIGS. 1 to 3, and common components are given like reference numerals.
However, in this embodiment, the user operable switch (shown at 13 FIGS. 2 and 3) is replaced by an internal memory in the form of a read-only memory (ROM) 40.
The subsidiary address bus 14 connects the address output of the ROM 40 to a 24-bit address comparison circuit 15 via two address latches 41 and 42 that are connected in parallel, and the subsidiary data bus 16 connects the data output from the ROM 40 to the input of an 8-bit buffer 43 via a further latch 44. The output of the buffer 43 is connected to the main data bus 12, which, as shown, also incorporates an 8-bit buffer 45.
Both buffers 43 and 45 are controlled by an address comparison signal L generated by the address comparison circuit 15, whereby data is selectively routed to the processing unit either on the main data bus 12 or on the subsidiary data bus 16, depending on the result of a comparison carried out in the address comparison circuit.
Latches 41 and 42 are set to hold the high and low bytes respectively of a preselected, two-byte (16-bit) address Ap transmitted thereto from the ROM 40 over the subsidiary address bus 14.
Similarly, the latch 44 is set to hold pre-selected data Dp (corresponding to the preselected address Ap in the latches 41 and 42) transmitted thereto from the ROM 40 over the subsidiary data bus 16.
The preselected address Ap held in the latches 41 and 42 is compared with the current addresses transmitted from the processing unit over the main address bus 11.
If the compared addresses are different, the address comparison signal L goes high, thereby maintaining the buffer 43 (which is supplied via an inventor 43a) closed and the buffer 45 (which is supplied via a logical AND gate 46) open and allowing data to pass directly from the external memory to the processing unit over the main data bus 12.
However, if the compared addresses are the same, the address comparison signal L goes low, thereby maintaining the buffer 43 open and the buffer 45 closed and enabling the preselected data Dp held in the latch 44 to pass to the processing unit in substitution for the data in the external memory.
In this embodiment, the interfacing device has the capability to modify data received from any one of a range of different external data storage media (containing different computer games) that can be plugged into the device.
To that end, the ROM 40 (.Iadd.a data source.Iaddend.) stores a plurality of different pre-selected addresses together with a corresponding plurality of different preselected data, and each preselected address is utilized in conjunction with the corresponding preselected data to modify the data from a respective external memory.
Clearly, in order to access the correct preselected address (and data) to the latches, to enable address comparison and (possible) data substitution to take place, the interfacing device must be capable of identifying which external memory has been plugged into its receiving port.
To that end, additional control circuitry is provided that, in effect, enables the interfacing device to interrogate two data bytes of the external memory.
These data bytes carry sufficient information to unambiguously identify the external memory and thereby enable the correct preselected address and the corresponding preselected data to be accessed to latches 41, 42 and 44 to facilitate the desired data substitution, as described hereinbefore.
The identification procedure is controlled by means of a controller 50 that is clocked by a counter 51 operating in conjunction with a clock circuit 52 and a "power-on" timing circuit 53.
When the external memory is first plugged into the interfacing device and power is supplied to the processing unit, the counter 51 is initialized and the external memory is isolated from the processing unit (by setting input A of the AND gate 46 low).
The controller 50 then transmits successive control signals to the ROM 40 on a control bus 54, causing the high and low bytes of the first address stored in the ROM 40 (corresponding to the first data byte for identification in the external memory) to be routed to the latches 55 and 56 respectively. In this way, the latches 55 and 56, which are connected to the external memory via the main address bus 12, are set to hold the first address (corresponding to the first data byte in the external memory). In response to this address, the first data byte is transferred from the external memory to an encoder 57 (the main data bus 12 being blocked by the buffer 46), where it is latched. This procedure is repeated for the second data byte for identification in the external memory, which is also transferred to, and latched in, the encoder 57.
The encoder 57 then performs preset, logical operations on the first and second latched data bytes and generates an output that uniquely identifies the external memory. This output is held in a ROM latch 58 (which had previously held a zero data field), and the encoder 57 is then disabled. The controller 50 selects from the ROM 40 the pre-selected address (and the preselected data) appropriate for the external memory represented by the output held in the ROM latch 58 and causes the high and low bytes of this preselected address to be transferred to the latches 41 and 42 respectively and the required preselected data to be transferred to the latch 44.
As described hereinbefore, the address comparison circuit 15 compares the latched, preselected address with the current addresses from the processing unit. However, the address comparison circuit 15 also compares current data transmitted from the external memory over the main data bus with data held in a fourth latch 47. The latched data (which is also derived from the ROM 40) is chosen to be the same as the data (from the external memory) which is to be replaced by the preselected data held in the latch 44. This additional comparison ensures substitution of the correct data and prevents errors which could arise as a result of an ambiguity in the process of comparing addresses.
The ROM 40 may have a number of different data banks, and so the data and address associated with each external memory may have a number of alternative values. In these circumstances, a user-operable switch 59 may be provided, enabling the user to select a desired data bank from the ROM 40 and thereby select a desired effect, e.g. a desired degree of difficulty (hard, medium or easy, say) with which the game is to be played.
In the described embodiment, each preselected address is allocated to a respective external memory. Alternatively, however, more than one of the preselected addresses can be allocated to the same external memory, thereby enabling more than one aspect of a game to be changed.
In another embodiment of the invention, illustrated in FIG. 6, an interfacing device for a computer games machine connects to the external program cartridge and the computer games machine allows the program cartridge to function normally except for one or more modifications performed by the interface.
These modifications affect one or more aspects of the game and can be either user selectable or preset in the interface.
In this respect, the embodiment of FIG. 6 is the same as the other embodiments.
However, in the embodiment of FIG. 6, the interface allows the program to execute normally but interrupts the processor at a particular point or points (user-selected or preset) in the program. When this interrupt occurs, the game is temporarily suspended while the interface banks its own ROM into the processor's memory and executes a piece of code. This code is such that a modification is effected on the games computer's internal memory. This interface then banks its own ROM out and allows the computer to continue executing the game as if nothing had happened.
This process allows a user or a preset ROM to change many of the variables that control aspects of a game, modifying the game in countless different ways.
The effect of this is very similar to the effect of the previous embodiments. The manner of operation is, however, different. Instead of changing the way the computer interprets or accesses external memory, this method changes the computer's internal memory itself in such a way that very similar results can be achieved: e.g., extra lives, skipped levels, increased or decreased car speed, etc.
Conventional devices that interrupt a program perform a designated function and then pass control back to original program. The purpose is normally to perform additional tasks rather than to change the way the existing program works. Also, the conventional devices are normally "stand-alone units" that do the same thing regardless of the program that is running. In contrast, the apparatus of the present invention produces its visible and audible effects in a manner that is intrinsically dependent on the "host" program. Moreover, it acts as an interface between the computer and the external memory in order to prevent access to the external memory when it wants to present its own program to the computer instead.
Conventional interrupt-controlled devices are activated entirely independently of the program that is running. In contrast, apparatus constructed in accordance with the present invention is activated upon detection of the exact address of a particular piece of program being accessed. It then makes changes to the computer's internal memory to affect the way the program works. This is not needed in conventional usage because it is easier for the original programmer to make the change before the external memory is produced.
In FIG. 6 the device 70 is an interface between a games computer (via edge connector 71) and a plug-in game cartridge external memory (via edge connector 72).
The address comparator circuit 73 compares the value on the address bus 74 with a preset value, in this case a value supplied on a bus 75 from registers 1 and 2.
When the compared values are different (i.e. normally), the computer accesses the external memory unhindered.
When the compared values are equal (i.e. the program is at the correct stage for the device to interrupt), an output signal is sent on control line A to a switch circuit 76, which in a practical embodiment may be a semiconductor device.
This has the effect of connecting the output enable line 80 from the computer through the switch 76 and alternative output enable line 81 to the device's internal ROM 77 instead of connecting the output enable line 80 to the external memory edge connector 72 through the extension 80a. At this point the computer starts addressing the ROM 77 instead of the external memory.
The ROM 77 can then make changes to the RAM and other registers housed in the computer (or in the interface 70) to effect changes in the way the program operates.
The switch 76 then reverses and re-enables the external memory by switching the output enable line 80 back to connect from the computer to the external memory through the extension 80a. In this example this is done by way of register 3, which controls control line B.
The program then continues where it left off but operating differently because of the changes that have been made.
When the external memory programs (games) are running on a computer, they constantly use the computer's internal RAM as a temporary scratch-pad for storing values that change. These values are typically used for parameters such as number of lives remaining, current level number, counters for timing loops (speed). number of cars, etc. In accordance with the present invention, the user--or the programmer of the ROM 77--can change these values in response to reaching a particular point in the program.
FIGS. 7a, 7b and 7c are respectively top plan, side and perspective vies of another embodiment of an interfacing device according to the invention. These figures show the best mode contemplated by the inventors for putting the invention into practice. The device comprises, as in the embodiments described above, a case 1 of which one end 2 is intended to fit within a receiving port of a computer games console and the opposite end 3 is intended to receive an external data storage medium or memory, such as a cartridge having a read-only memory or ROM.
The case contains, as in the embodiments described above, a printed circuit board 4 that carries interfacing circuitry, the board 4 being provided at each end thereof with suitable end connectors enabling the interfacing circuit to detachably interconnect the main processing unit of the games console and the external memory.
A handle portion H of generally triangular construction (as viewed from above) has an inclined portion I, a stop S, and a concave thumb rest TR provided with ridges R. The external data storage medium is connectable to the interfacing device in such a manner as to be positioned underneath the handle portion H. By virtue of the concave thumb rest TR formed on the upper surface of the handle portion H, an assembly of the interfacing device and the external data storage medium can conveniently be grasped with a thumb engaging the thumb rest TR and fingers engaging the external data storage medium for connection of the assembly to the processing unit of a computer games system. Moreover, the protruding thumb rest TR, and particularly the stop S thereof, prevents inadvertent insertion of the assembly of the interfacing device and game cartridge into the computer games machine in a n upside-down relation, since the stop S will in case of such an attempted erroneous insertion latch on the lower rim of the cartridge-receiving opening into the games machine.
FIG. 7d is a perspective view showing a "game X," which can be any conventional game cartridge, about to be assembled with the device according to the invention. FIG. 7e shows the game cartridge and the device according to the invention in assembled relation, and FIG. 7f shows the assembly about to be inserted into a games machine, for example a Nintendo machine. As noted above, the assembly is conveniently grasped with the thumb of the user in the thumb rest TR and the fingers of the user below the game cartridge. The assembly is inserted and appears then as in FIG. 7g, with the lid of the games machine resting on the thumb rest TR.
The printed circuit board 4 is thicker than normal, to allow the edge connector to make good contact with the games machine connector without the need for the interface to be pushed down fully in the normal way. That is, the printed circuit board 4 has sufficient thickness that the connection of the assembly or the interfacing device and game cartridge to the processing unit of the computer games machine can be effected with a movement that is rectilinear. This enables the unit to be made smaller overall and more elegant than it would otherwise be.
The circuitry incorporated in the device of FIGS. 7a-7g is illustrated in FIGS. 8a-8c. The circuitry shown in these figures has two modes or operation. Mode 1 is a latch-setting mode, wherein values for the address comparison, data comparison, and data replacement functions are set by the user. Mode 2 is an active mode, very similar to the operation of the embodiments described above, wherein the address comparators (as well as data comparators) send a signal to a data replacement unit to effect a replacement of the data when the conditions for data replacement are met.
The selection of mode 1 or mode 2 is made by an output signal from a control latch 103 on a mode select line 102. A CE line 92 that comes from the computer edge connector 71 (for example from a video games machine made by Nintendo) is connected to the CE selector 90, which is controlled by the signal on the line 102. In conventional structures, the line 92 would normally connect directly to the external memory, allowing it to respond to data read/write requests from the video games machine. In the circuit of FIG. 8a, the signal on the line 92 is passed either to the external memory 93 via a CE' line 94 or to an interface ROM 96 via a CE" line 98, depending on the state or the line 102. In this way, either the external memory 93 or the interface ROM 98 is made active. The circuitry also has a power-on circuit 100, which ensures that the line 102 from the control latch 103 is set to the latch setting mode when the power is first turned on.
MODE I: LATCH-SETTING MODE
The purpose of this mode is to allow the user to select the address comparison data and replacement data. The program in the ROM 96 is designed in such a way that it will accept input from the normal game control pad, operated by the user, and use it to move an on-screen pointer around the screen. Also on the screen there are 16 different letters (which represent values). The user can move the pointer to any of these letters and select them using a button oh the game control pad. By repeating this process the user can enter this data to represent addresses, comparison data bytes and replacement data bytes, as well as function enable/disable information. When the user presses the start button on the game controller, the software stores the data entered by the user in the latches in each of the comparison/ replacement units 1, 2 and 3 as well as in a control latch 103.
It then sets a particular bit "0" in the control latch 103, which alters the state of the mode select line 102. thereby switching the device to its active mode by changing the state of the CE selector 90 to its other position. This has the effect of conditionally enabling the comparison/ replacement units 1, 2 and 3.
MODE II: ACTIVE MODE
In this mode, the external memory has control of the CPU and the game will function normally, with the exception of any data replacement operations performed by the interface. The comparison/replacement units are now active, provided that the appropriate bit in the control latch has been set to enable them.
The structure illustrated in FIGS. 8a, 8b and 8c includes an address bus 104 connected to comparison/ replacement units 1, 2 and 3 and a data bus 105 connected to the same units. At the left of FIG. 8a, the address and data buses connect to the games machine, and at the right to the game cartridge that is currently in use. In addition, a read/write line 106 is connected to the comparison/ replacement units 1, 2 and 3, to the ROM 96 and to the video games machine and the particular game cartridge in use. The chip enable line 92 is connected to the chip enable or CE selector 90 as described before and also to the comparison/ replacement units 1, 2 and 3.
The address and data buses 104, 105 are also connected to the ROM 96, and the address bus 104 is connected to a register address decoder 107. The latter produces three outputs which go respectively to inputs R.SELO...3 of each of the comparison/ replacement units 1, 2 and 3. As FIG. 8c shows, the latter input goes to a replacement data latch 0-7, a comparison data latch 0-7, a comparison address latch 0-7, and a comparison address latch 8-14.
the data bus 105 also connects to the control latch 103, which produces the output on the line 102 to the CE selector, as noted above. The output on the line 102 also goes to the register address decoder 107 and to an output to FIG. 8b labeled G.CONT (graphics control).
The control latch 103 produces an output to an input labeled R.EN on each of the comparison/ replacement units 1, 2, and 3 and an output to an input labeled DC.EN on each of the comparison/ replacement units 1, 2 and 3.
Each of the comparison/ replacement units 1, 2 and 3 produces an output on a terminal labeled REP ("replace") which is supplied to the CE selector 90.
In FIG. 8b, the graphics address 0-12 bus is connected to a graphics generator 110, which produces an output to a graphic output buffer 111. A device selector 112 receives inputs from the G.CONT terminal and from a G CE terminal and produces outputs to the graphic output buffer 111 and the G CE terminal of the game cartridge. The graphics lines GWE and GOE connect through FIG. 8b from the games machine to the game cartridge in use, and the latter line connects also to the graphic output buffer 111.
In FIG. 8c, the replacement data latch 0-7 connects to an 8 bit buffer 115. An 8-bit comparator 116 receives comparison inputs from the data line D0-7 and the comparison data latch 0-7 and produces an output signal to a control 117 when the inputs are equal. A fifteen bit comparator 118 receives at one input an output from the comparison address latch 0-7 and an output from the comparison address latch 8-14 and at the other input data from the address line 0-14. It produces a control output to the control 117 when the inputs are equal. The control 117 also receives signals from the R.EN, read/write, chip enable, DC.EN and F.EN terminals. Its output controls the 8-bit buffer 115 and is also supplied to the output terminal REP.
The Graphics Generator
Certain computer games devices, for example one made by Nintendo, normally generate a screen display by reading data from a graphics ROM. This data defines the bit patterns that make up the letters and graphical shapes that appear on the screen.
The screen is made up of many character- or letter-sized squares (or rectangles), called character cells, which are 8 by 8 pixels (picture elements, or dots) in size. Each pixel is defined by 2 bits in memory, representing one of four colors. Usually the graphics ROM is a minimum of 8K bytes in size, giving 512 different character cell definitions, as is needed for a normal game. This allows the system to produce colorful, detailed and varied graphics displays.
When in its latch setting mode, the device of FIGS. 8a-8d needs to use the screen for display purposes. Specifically, it needs to display the 16 letters for the user to choose from, the selected letters, and the product name at the top of the screen. It has been found it is not necessary to use the full capability of the normal graphic system, and that the complexity, size and cost of the device can be reduced by eliminating the graphics ROM chip normally required.
In accordance with the invention as embodied in the circuitry of FIG. 8d, a simple circuit emulates a graphics ROM containing the 16 character cell definitions (FIG. 10b). Even though the graphics produced with this system are cruder (only each group of 4 by 4 pixels is selectable on or off, instead of each pixel being individual selectable) it is perfectly adequate for the purpose of displaying the 16 letters, selected letters and product name.
In FIG. 8d, a small circuit is added to the circuitry needed for the rest of the device. The circuit of FIG. 8d has a negligible cost and size, in contrast to the substantial cost and size of the separate ROM which would otherwise be required.
The graphics generator and the graphic output buffer of FIG. 8d together function as a graphics ROM emulator circuit.
A conventional computer games device such as one made by Nintendo is designed specifically to get its graphics data from external memory (ROM or RAM). The structure of FIG. 8d eliminates the need to have any external memory for graphics generation.
In FIG. 8d, the graphic generator 110 and graphic buffer output 111 are of course the same as the units shown schematically in FIG. 8b. FIG. 8d shows the inputs to the graphic generator 110 on lines GA 2, GA 4, GA 5, GA 6 and GA 7 and outputs on lines GD 0, GD 1, GD 2, GD 3, GD 4, GD 5, GD 6 and GD 7 plus a select input G.OE and C.CE'.
The graphic generator 110 includes four AND gates 201, 202, 203, 204, two OR gates 205, 206 and an invertor 207. If the input GA 2 is high, the OR gate 205 is high only if the input GA 4 is high and the OR gate 206 is high only if the input GA 5 is high. On the other hand, if GA 2 is low, then the OR gate 205 is high only if Ga 6 is high and the OR gate 206 is high only if GA 7 is high.
The object of the circuitry in FIG. 8d is to produce the 16 character bit patterns of FIG. 8e, these patterns being numbered respectively 0-15. Since 4×4 pixels are addressed as a unit, there is a sacrifice of resolution, as indicated above, but, for reasons also indicated above, it is of no particular consequence. In FIG. 8e (and also in the output portion of FIG. 8f), a space that is not blackened corresponds to "0", and a space that is blackened corresponds to "1". There is, of course, only one combination of all "1's". These two possibilities correspond to "0" and "15", respectively, in FIG. 8e. There are four different ways in which one darkened space can be arranged, corresponding to boxes 1, 2, 4 and 8 in FIG. 8e. Similarly, there are four ways in which 3 darkened spaces (i.e., one space that is not darkened) can be arranged, namely those corresponding to 7, 11, 13 and 14 in FIG. 8e. Finally, there are 6 ways in which 2 darkened spaces (corresponding to 2 spaces that are not darkened) can be arranged: these correspond to 3, 5, 6, 9, 10 and 12 in FIG. 8e.
FIG. 8f is a truth table showing the address lines in a logical order and the data values they produce to make the 16 character shapes. In FIG. 8e, all address line combinations are shown in binary order. Of course, the order can be changed and is not critical. The character bit patterns produced can be viewed with the left side of FIG. 8f up to see the character shapes from the same perspective as in FIG. 8e. When the input line GA 2 is set to "0" it designates the top half of the pattern and when set to "1" designates the bottom half.
The OR gate 205 produces an output which is supplied to the four input terminals of the buffer 111 that relate to the output lines GD 4-GD 7, and the OR gate 206 produces an output which is supplied to the four input terminals of the buffer 111 that relate to the outputs GD 0-GD 3. Accordingly, in FIG. 8f, in the case of pattern "1", for example, the inputs GA 4-GA 7 of respectively "1", "0", "0", "0" correspond to no shading in the third quadrant of the output; but when GA 2 changes to "1", the same inputs GA 4-GA 7 of "1", "0", "0", "0" corresponds to shading in the third quadrant. In a similar way, the inputs GA 2 and GA 4-GA 7 shown in FIG. 8f produce the outputs on GD 0-GD 7 shown in FIG. 10f to form all of the bit patterns "0" through "15". These patterns are shown more pictorially in FIG. 8e.
The operation of the circuitry of FIGS. 8a-8d will now be described in connection with the flow chart of FIG. 9.
FIGS. 9a, 9b and 9c when taken together form a flowchart showing the process performed with the aid of the circuitry of FIGS. 8a-8d. In FIGS. 9a-9c, steps 201 and 202 are performed by the power-on circuit, steps 203-213 by the interfacing ROM, steps 214 and 215 by the program in the internal memory of the games machine, and steps 217-227 by the interfacing ASIC. When power is turned on as indicated at step 201 in FIG. 9a, the process moves to step 202, wherein the control latch defaults to a value which sets the CE selector 90 so as to enable the ROM 96 on line CE" 98. The process then moves to step 203, wherein the ROM 96 begins execution and the screen in accordance with the invention appears on the display screen on which the game is displayed.
At step 204, the program in the ROM determines whether the user has pressed a button on the control pad. If the user is not pressed such a button, the program loops back and makes the determination repeatedly until it is found that user has pressed a button on the control pad. When an affirmative determination is made, the program moves to step 205, wherein a determination is made whether a movement button has been pressed by the user. If so, then at step 206 the program moves the cursor to a new letter and then reverts to step 204. If no movement button has been pressed, the program determines whether a fire button has been pressed by the user. If so, the program causes display of the letter under the cursor on the screen as a selected letter and then loops back to step 204. If the fire button is not found to have been pressed, the program determines at step 209 whether the start button has been pressed. If not, the program loops back to step 204.
When the start button has been pressed, then, as FIG. 9b shows, the program converts the selected letters (if any) to hexadecimal values which represent data to be stored in the latches. At step 211, the program then stores hexadecimal values in latches corresponding to the addresses, data replacement values, and data compare values (if any). Then, at step 212, a program is transferred to the control deck's internal RAM. At step 213, control is passed to the program in the RAM.
At step 214, the program in internal memory stores a value in the control latch with the CE selector bit set so as to enable the external memory on the line CE' 94 (FIG. 8a) and conditionally enable the comparison/ replacement units 1, 2, 3 and disable graphic emulation. At step 215, control is passed to the reset address of the external memory and, at step 216, the game program begins execution.
At step 217, the device determines whether the game control is requesting a read from the external memory. If not, it loops back until an affirmative determination is made. When an affirmative determination is made, the device determines whether the value of the address bus corresponds to the address stored in one or the comparison/ replacement units 1, 2 and 3. If not, the process loops back to step 217. When an affirmative determination is made, the process advances to step 219 (FIG. 9c).
At step 219, a determination is made whether the corresponding comparison/replacement function is enabled. If not, the process loops back to step 217. When it is found at step 219 that the corresponding comparison/replacement function is enabled, then, at step 220, a determination is made whether the corresponding data comparison function is enabled. If it is determined that the function has been enabled, the process advances to step 221, where a determination is made whether the value of the data bus corresponds to the comparison data stored in the corresponding address/comparison unit. If no such correspondence is found, the process loops back to step 217.
If at step 220 the corresponding data comparison function is not enabled, or if at step 221 the value of the data bus is found to correspond to the comparison data stored in the corresponding data and comparison latch, the process moves to step 222. At step 222, the external memory is prevented from outputting data by setting the CE selector to disable the line CE' 94 (FIG. 8a) via the terminal REF. Then, at step 223, the corresponding comparison/replacement unit is set to output the data stored in its data replacement latch to the data bus.
At step 225, a determination is made whether the read cycle is finished. If not the process stays in the loop at step 225 until it is determined that the read cycle is finished. When the read cycle is finished, the process advances to step 226. At step 226, the corresponding comparison/replacement unit is prevented from outputting data. Then, at step 227, the external memory is re-enabled by enabling the line CE' 94 (FIG. 8a). The process then loops back to step 217 in FIG. 9b.
The versatility of the described interfacing devices is demonstrated by short extracts from typical computer games programs given in examples I and II below.
In these examples, the four-digit numbers (e.g. 3000) appearing in the left-hand column are coded addresses; they are followed by coded instructions (e.g. DEC1000) from the addressed storage location of the external memory. In fact, in the examples given, each instruction consists of two or three bytes. An explanation of the function of each instruction is given in the right-hand column.
EXAMPLE I
This section of the program causes a unit, e.g. a plane or car, to move at a particular speed.
______________________________________                                    
ADDRESS INSTRUCTION     EXPLANATION                                       
______________________________________                                    
3000    DEC 1000        This reduces the content                          
                        of address 1000 by 1                              
                        (e.g. a value 28 changes                          
                        to 27).                                           
3003    BNE 300D        If the value of the last                          
                        step is not zero the                              
                        program returns to                                
                        address 3000.                                     
3005    LDA 50          This puts value 50 (from                          
                        the storage location                              
                        corresponding to address                          
                        3006) into a variable                             
                        "A."                                              
3007    STA 1000        This puts the valve of                            
                        variable A (i.e. 50) into                         
                        address 1000.                                     
300A    JSR "MOVE UNIT" This calls up subroutine                          
                        "MOVE UNIT" which                                 
                        causes the unit to move.                          
300D    JMP 3000        The section of the                                
                        program set out above is                          
                        repeated.                                         
______________________________________                                    
This section of the program causes the subroutine "MOVE UNIT" to be executed when the program steps corresponding to addresses 3000 to 3003 have been executed 50 times.
If, therefore, the interfacing device sets the selected address at 3006 and sets the selected data value at 10, then the value 50 in variable "A" in the processor (the value in the corresponding storage location of the memory) is replaced by the user-selected value (10 in this example). This causes the subroutine "MOVE UNIT" to be executed when the program steps corresponding to addresses 3000 to 3003 have been executed 10 times instead of 50 times.
Consequently the playing unit is caused to move more quickly.
EXAMPLE II
In this game, a player is required to complete a given number of laps of a track.
______________________________________                                    
ADDRESS INSTRUCTION     EXPLANATION                                       
______________________________________                                    
2000    INC 1200        This increments the                               
        (LAP COUNT)     content of address 1200                           
                        by one (increasing the                            
                        lap count by one every                            
                        time a player completes a                         
                        lap).                                             
2002    LDA 1200        This puts the content of                          
                        address 1200 into                                 
                        variable A (i.e. it puts                          
                        the current lap count                             
                        into variable A).                                 
2004    CMP 3 (LAP 3?)  This compares the last                            
                        value of the lap count                            
                        with 3 (the value derived                         
                        from the storage location                         
                        corresponding to address                          
                        2005)                                             
2006    BNE 200A        If the answer is no                               
                        (i.e., the comparison                             
                        shows an inequality),                             
                        then the program goes to                          
                        200A: otherwise it                                
                        continues on.                                     
2008    JMP             This causes a jump to the                         
        "RACE COMPLETE" "RACE COMPLETE"                                   
                        parts of the program.                             
______________________________________                                    
This number of laps required to be completed by the player is set at the value 3 derived from the addressed storage location of the memory. If, therefore, the interfacing device sets the selected address at 2005 and sets the selected data value at 7, say, then the value 3 in variable A in the processor (the value derived from the memory) is replaced by the designated value, 7 in this example.
This requires the player to complete 7 instead of 3 laps, thereby increasing the difficulty of the game.
Clearly, these examples are merely illustrative of the many different modifications that can be effected using the interfacing device or the invention. The examples given effect a change of a single byte in a data table so as to change selected game variables such as screen color, sound volume, number of players, number of laps, time intervals, etc.
However, changes can alternatively, or additionally, be made to the instructions themselves, e.g. to change an instruction to increase a value to an instruction, to decrease a value, to change an instruction to perform a particular task to one that requires no action, to change a branch instruction (BEQ to BNE, say), and so on.
Although the described embodiments enable recognition of a single address and substitution of data corresponding thereto, the invention also embraces recognition of two or more different addresses and substitution of the respective data corresponding thereto.
Also, although the specific embodiments relate to a detachable interfacing device, the device can alternatively be incorporated into the processing unit as an integral part thereof.

Claims (37)

We claim:
1. An interfacing device for connecting a processing unit of a computer games system to an external data storage medium so as to enable the processing unit to address, and receive data from, different storage locations in the external data storage medium, said interfacing device being removably connectable to the processing unit and to the external data storage medium and comprising means responsive to the processing unit for recognition of a selected address and means responsive to said recognition for modification of data processed by the processing unit.
2. An interfacing device according to claim 1 wherein said recognition means includes means for comparing the selected address with an address from the processing unit and said modification means effects the modification if the compared addresses are the same.
3. An interfacing device according to claim 1 or 2 wherein the selected address is an address selected by the user.
4. An interfacing device according to clam 3 wherein the modification means comprises user-operable selection means for generating the selected address and user-selected data and means for supplying the user-selected data to the processing unit in substitution for the data in the addressed storage location of the external data storage medium if the compared addresses are the same.
5. An interfacing device according to claim 4 wherein the data supplying means includes a semiconductor switching device responsive to an output from the comparing means.
6. An interface device according to claim 4 wherein the user-operable selection means comprises a first plurality of user-operable switching devices for setting the selected address and a second plurality of user-operable switching devices for setting the user-selected data.
7. An interfacing device according to claim 6 wherein the switching devices are user-operable rotary switches.
8. An interfacing device according to claim 7 wherein the rotary switches are 16-position rotary switches.
9. An interfacing device according to claim 6 wherein the first plurality comprises four said switching devices and the second plurality comprises two said switching devices.
10. An interfacing device according to claim 1 or 2 wherein said selected address is preselected.
11. An interfacing device according to claim 10 wherein the modification means effects the modification in response to recognition of one of a plurality of preselected addresses in accordance with identification data from the external data storage medium.
12. An interfacing device according to claim 11 wherein the recognition means includes a memory for storing said plurality of preselected addresses together with a plurality of corresponding preselected data, and means for comparing said one address with an address from the processing unit, and said modification means includes means for supplying to the processing unit the preselected data, corresponding to the one address, in substitution for the data in the external data storage medium, if the compared addresses are the same.
13. An interfacing device according to claim 12 wherein the preselected data corresponding to one or more of said preselected address each may be user-selected from a corresponding set of possible values, said interfacing device further including user-operable means for selecting from each said corresponding set.
14. An interfacing device according to claim 1 wherein the modification means effects a modification in response to recognition of any one of two or more selected addresses from the processing unit.
15. In combination, an interfacing device according to claim 1, the processing unit and the external data storage medium.
16. An interfacing device according to claim 1 wherein the modification means comprises a .[.read-only memory.]. .Iadd.data source .Iaddend.and the modification means interrupts the processing unit in response to said recognition and .[.banks.]. .Iadd.presents .Iaddend.data from said .[.read-only memory into.]. .Iadd.data source to .Iaddend.said processing unit in order to modify an internal memory in the processing unit.
17. An interfacing device according to claim 16 wherein said selected address is user-selected.
18. An interfacing device according to claim 16 wherein said selected address is preset in said recognition means.
19. An interfacing device according to claim 16 wherein said recognition means comprises bus means connected to said processing unit, register means, and comparator means connected to said bus means and said register means, said register means being adapted to store a value corresponding to said selected address and said comparator means producing an output indicative of correspondence between an address on said bus means and said stored value.
20. An interfacing device according to claim 16, wherein said recognition means includes comparator means for comparing in selected address with an address from the processing unit and said modification means comprises switch means responsive to said comparator means for enabling access by said processing unit to data in said .[.read-only memory.]. .Iadd.data source.Iaddend..
21. An interfacing device according to claim 20 wherein said switch means comprises a semiconductor device.
22. An interfacing device according to claim 1 wherein said recognition means also recognizes a selected data value, and said modification means effects said modification of data only if said recognition means recognizes both said selected address and said selected data value.
23. An interfacing device according to claim 1 further comprising case means containing said recognition means and said modification means, said case means including a handle portion.
24. An interfacing device according to claim 23, said external data storage medium being connectable thereto in such a manner as to be positioned underneath said handle portion, and said handle portion being formed with a thumb rest protruding from an upper portion thereof, said thumb rest being formed with a concave portion for accommodating the thumb of a user, whereby an assembly of said interfacing device and said external data storage medium can conveniently be grasped with a thumb engaging said thumb rest and fingers engaging said external data storage medium for connection of said assembly to said processing unit of said computer games system.
25. An interfacing device according to claim 24 wherein said protruding thumb rest prevents connection of said assembly to said processing unit in an up-side-down relation.
26. An interfacing device according to claim 24 wherein said recognition means and said modification means are incorporated in a printed circuit board that has sufficient thickness that said connection of said assembly to said processing unit of said computer games system can be effected with a movement that is rectilinear.
27. An interfacing device according to claim 1 that operates in a latch-setting mode wherein a user can determine said selected address and replacement data and further operates in an active mode wherein said recognition means recognizes said selected address and said modification means effects said modification of data in response to said recognition.
28. An interfacing device according to claim 27 wherein a display screen used with the interfacing device has a plurality of character cells each measuring a plurality of display screen pixels in each of two mutually orthogonal directions.
29. An interfacing device according to claim 28 wherein, at least in the latch setting mode, a plurality of pixels in each cell are controlled as a unit.
30. An interfacing device according to claim 29 further comprising a graphic generating means for generating said graphic display, said display screen presenting said graphic display, at least in said latch-setting mode.
31. An interfacing device according to claim 30 wherein said graphic generating means comprises a plurality of gate means responsive to graphic address signals and a graphic output buffer responsive to said gate means, said graphic output buffer producing graphic data outputs that control said pixels, whereby said graphics display is generated without the provision of a read-only memory.
32. A method or playing a computer game controlled by a computer games system having an internal processing unit and an external data storage medium, comprising the following steps performed outside the internal processing unit:
comparing an address from the processing unit with a selected address; and
modifying data processed by the processing unit whenever the compared addresses are the same.
33. A method according to claim 32 wherein aid selected address is selected by a player of the game.
34. A method according to claim 32 wherein aid selected address is presettable.
35. A method according to claim 32 wherein the modification of data processed by the processing unit comprises the step of replacing data being transmitted to the processing unit from the external data storage medium.
36. A method according to claim 32 wherein the modification of data processed by the processing unit comprises the step of supplying to said processing unit data from a source external to both the external data storage medium and the processing unit. .Iadd.
37. An interfacing device for interconnecting a processing unit of a computer games system and an external data storage medium of a kind which is directly connectable to the processing unit, the interfacing device being removably connectable to the processing unit and to the external storage data storage medium to enable the processing unit to address, and receive data from, different data storage locations in the external data storage medium, and the interfacing device comprising:
means for conveying addresses from an address output of the processing unit to an address input of the external data storage medium;
recognition means for recognizing a selected address from the processing unit; and
modifications means responsive to recognition of said selected address for causing the processing unit to process different data than the processing unit would process if the external data storage medium is directly connected to the processing unit. .Iaddend..Iadd.38. A method of operating a computer games system in which an interfacing device interconnects a processing unit of the computer games system and an external data storage medium of a kind which is directly connectable to the processing unit, the interfacing device being removably connectable to the processing unit and to the external data storage medium to enable the processing unit to address and receive data from different data storage locations in the external data storage medium, the method including the following steps performed in the interfacing device:
conveying addresses from an address output of the processing unit to an address input of the external data storage medium;
recognizing a selected address from the processing unit addressing a storage location in the external data storage medium; and
in response to recognition of said selected address, causing the processing unit to process different data than the processing unit would process if the external data storage medium is directly connected to the processing unit. .Iaddend.
US08/174,700 1989-06-05 1993-12-28 Interfacing device for a computer games system Expired - Lifetime USRE35520E (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/174,700 USRE35520E (en) 1989-06-05 1993-12-28 Interfacing device for a computer games system

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB8912866 1989-06-05
GB898912866A GB8912866D0 (en) 1989-06-05 1989-06-05 Interfacing device for a computer games system
GB8915975 1989-07-12
GB898915975A GB8915975D0 (en) 1989-06-05 1989-07-12 Interfacing device for a computer games system
US07/530,617 US5112051A (en) 1989-06-05 1990-05-30 Interfacing device for a computer games system
US08/174,700 USRE35520E (en) 1989-06-05 1993-12-28 Interfacing device for a computer games system

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US07/530,617 Reissue US5112051A (en) 1989-06-05 1990-05-30 Interfacing device for a computer games system

Publications (1)

Publication Number Publication Date
USRE35520E true USRE35520E (en) 1997-05-27

Family

ID=10657891

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/174,700 Expired - Lifetime USRE35520E (en) 1989-06-05 1993-12-28 Interfacing device for a computer games system

Country Status (2)

Country Link
US (1) USRE35520E (en)
GB (2) GB8912866D0 (en)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6048270A (en) 1998-09-21 2000-04-11 Chiu-Hao; Cheng Data-transfer device
US20010031665A1 (en) * 2000-03-30 2001-10-18 Sagahiro Taho Game information storage medium and game system using the same
US6315669B1 (en) 1998-05-27 2001-11-13 Nintendo Co., Ltd. Portable color display game machine and storage medium for the same
US6373462B1 (en) 1999-12-07 2002-04-16 Nintendo Co., Ltd. Method and apparatus for displaying higher color resolution on a hand-held LCD device
US6386979B1 (en) 1998-11-04 2002-05-14 Std Manufacturing Ltd. Methods and systems for transferring game saves between a game system memory card and a computer
US6565443B1 (en) 1999-09-14 2003-05-20 Innovative Gaming Corporation System and method for verifying the contents of a mass storage device before granting access to computer readable data stored on the device
US20030189576A1 (en) * 1999-11-24 2003-10-09 Jun Pan Method and apparatus for displaying higher color resolution on a hand-held LCD device
US6672963B1 (en) 2000-09-18 2004-01-06 Nintendo Co., Ltd. Software implementation of a handheld video game hardware platform
US6810463B2 (en) 2000-05-24 2004-10-26 Nintendo Co., Ltd. Gaming machine that is usable with different game cartridge types
US6877096B1 (en) 2000-04-11 2005-04-05 Edward J. Chung Modular computer applications with expandable capabilities
US20050130744A1 (en) * 2000-09-18 2005-06-16 Nintendo Co., Ltd Video game distribution network
US20050245313A1 (en) * 2004-03-31 2005-11-03 Nintendo Co., Ltd. Game console and memory card
US20060094512A1 (en) * 2004-03-31 2006-05-04 Nintendo Co., Ltd. Game console and emulator for the game console
US20060111190A1 (en) * 2004-03-31 2006-05-25 Nintendo Co., Ltd. Game console connector and emulator for the game console
US7243053B1 (en) 1999-10-22 2007-07-10 Shoot The Moon Products Ii, Llc Method and apparatus for virtual control of operational scale models
US7285051B2 (en) 2000-05-25 2007-10-23 Nintendo Co., Ltd. Game information storage medium and game system using the same
US7445551B1 (en) 2000-05-24 2008-11-04 Nintendo Co., Ltd. Memory for video game system and emulator using the memory
US20100248823A1 (en) * 2006-11-17 2010-09-30 Smith Darren C System and method for downloadinng video game programs
US7837558B2 (en) 2004-03-31 2010-11-23 Nintendo Co., Ltd. Game console and emulator for the game console
US8157654B2 (en) 2000-11-28 2012-04-17 Nintendo Co., Ltd. Hand-held video game platform emulation
US11278793B2 (en) 2004-03-31 2022-03-22 Nintendo Co., Ltd. Game console

Citations (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1346219A (en) * 1970-10-16 1974-02-06 Honeywell Bull Sa Memory arrangements for digital electronic computers
US3803470A (en) * 1972-01-18 1974-04-09 R Vosteen Speed servo for a permanent magnet direct current motor
US4028684A (en) * 1975-10-16 1977-06-07 Bell Telephone Laboratories, Incorporated Memory patching circuit with repatching capability
US4028678A (en) * 1975-10-16 1977-06-07 Bell Telephone Laboratories, Incorporated Memory patching circuit
US4051460A (en) * 1975-02-01 1977-09-27 Nippon Telegraph And Telephone Public Corporation Apparatus for accessing an information storage device having defective memory cells
GB1491702A (en) * 1975-04-01 1977-11-16 Int Computers Ltd Memory systems
US4095278A (en) * 1975-10-08 1978-06-13 Hitachi, Ltd. Instruction altering system
US4149027A (en) * 1977-05-27 1979-04-10 Atari, Inc. TV game cartridge and method
US4150428A (en) * 1974-11-18 1979-04-17 Northern Electric Company Limited Method for providing a substitute memory in a data processing system
FR2407527A1 (en) * 1977-10-28 1979-05-25 Rockwell International Corp Microprocessor controlled pin ball machine - operates with memories and input and output units to control playing modes and displays
GB1550675A (en) * 1975-07-03 1979-08-15 Texas Instruments Inc Fault-tolerant cell addressable array
US4218757A (en) * 1978-06-29 1980-08-19 Burroughs Corporation Device for automatic modification of ROM contents by a system selected variable
US4368515A (en) * 1981-05-07 1983-01-11 Atari, Inc. Bank switchable memory system
GB2115989A (en) * 1982-02-12 1983-09-14 Voltmace Limited Programmed cartridge/video machine adaptor
GB2118809A (en) * 1982-01-11 1983-11-02 Atari Inc Self-adjusting game difficulty method and apparatus for electronic games
US4432067A (en) * 1981-05-07 1984-02-14 Atari, Inc. Memory cartridge for video game system
GB2129585A (en) * 1982-10-29 1984-05-16 Inmos Ltd Memory system including a faulty rom array
US4456966A (en) * 1981-02-26 1984-06-26 International Business Machines Corporation Memory system with flexible replacement units
US4480835A (en) * 1983-03-02 1984-11-06 Williams Theodore R Cartridge adapter for programmable video games
US4485457A (en) * 1983-05-31 1984-11-27 Cbs Inc. Memory system including RAM and page switchable ROM
USD285926S (en) 1983-12-14 1986-09-30 Rockwell International Corp. Housing for interface module
EP0268419A2 (en) * 1986-11-19 1988-05-25 Nintendo Co. Limited Memory cartridge and data processing apparatus
US4763300A (en) * 1985-08-28 1988-08-09 Nintendo Co., Ltd. Front loading apparatus for a memory cartridge utilized for a data processing machine
US4788537A (en) * 1987-09-17 1988-11-29 Potiker Lowell A Mouse interface assembly
US4799635A (en) * 1985-06-24 1989-01-24 Nintendo Co., Ltd. System for determining authenticity of an external memory used in an information processing apparatus
US4844465A (en) * 1986-07-11 1989-07-04 Nintendo Company, Ltd. Adaptor of a cartridge for gaming machine
US4860128A (en) * 1985-04-24 1989-08-22 Nintendo Co., Ltd. Recordable data device having identification symbols formed thereon and cooperating data processing system having registering symbols
US4922420A (en) * 1986-07-23 1990-05-01 Nintendo Company Limited Video game software selection data processing system
US4926372A (en) * 1986-05-06 1990-05-15 Nintendo Company Limited Memory cartridge bank selecting
USD308197S (en) 1986-10-14 1990-05-29 Nintendo Company Limited Adaptor for a game machine cartridge
USD311737S (en) 1988-12-07 1990-10-30 Plus Development Removable hard disk drive module
USD315577S (en) 1988-10-04 1991-03-19 Wen-Fu Wang Video game console
US5004232A (en) * 1989-10-13 1991-04-02 Macronix, Inc. Computer game cartridge security circuit
US5112051A (en) * 1989-06-05 1992-05-12 Westinghouse Electric Corp. Interfacing device for a computer games system
US5134391A (en) * 1989-01-10 1992-07-28 Nintendo Company Limited System for preventing the use of an unauthorized external memory
US5140110A (en) * 1986-03-13 1992-08-18 Nintendo Co. Ltd. Printed circuit board capable of preventing electromagnetic interference
USRE34161E (en) * 1985-10-04 1993-01-12 Nintendo Company Limited Memory cartridge and information processor unit using such cartridge
US5226136A (en) * 1986-05-06 1993-07-06 Nintendo Company Limited Memory cartridge bank selecting apparatus

Patent Citations (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1346219A (en) * 1970-10-16 1974-02-06 Honeywell Bull Sa Memory arrangements for digital electronic computers
US3803470A (en) * 1972-01-18 1974-04-09 R Vosteen Speed servo for a permanent magnet direct current motor
US4150428A (en) * 1974-11-18 1979-04-17 Northern Electric Company Limited Method for providing a substitute memory in a data processing system
US4051460A (en) * 1975-02-01 1977-09-27 Nippon Telegraph And Telephone Public Corporation Apparatus for accessing an information storage device having defective memory cells
GB1491702A (en) * 1975-04-01 1977-11-16 Int Computers Ltd Memory systems
GB1550675A (en) * 1975-07-03 1979-08-15 Texas Instruments Inc Fault-tolerant cell addressable array
US4095278A (en) * 1975-10-08 1978-06-13 Hitachi, Ltd. Instruction altering system
GB1531528A (en) * 1975-10-16 1978-11-08 Western Electric Co Apparatus for providing valid information for invalid information in unalterable memory means
US4028679A (en) * 1975-10-16 1977-06-07 Bell Telephone Laboratories, Incorporated Memory patching circuit with increased capability
US4028684A (en) * 1975-10-16 1977-06-07 Bell Telephone Laboratories, Incorporated Memory patching circuit with repatching capability
US4028678A (en) * 1975-10-16 1977-06-07 Bell Telephone Laboratories, Incorporated Memory patching circuit
US4149027A (en) * 1977-05-27 1979-04-10 Atari, Inc. TV game cartridge and method
FR2407527A1 (en) * 1977-10-28 1979-05-25 Rockwell International Corp Microprocessor controlled pin ball machine - operates with memories and input and output units to control playing modes and displays
US4218757A (en) * 1978-06-29 1980-08-19 Burroughs Corporation Device for automatic modification of ROM contents by a system selected variable
US4456966A (en) * 1981-02-26 1984-06-26 International Business Machines Corporation Memory system with flexible replacement units
US4368515A (en) * 1981-05-07 1983-01-11 Atari, Inc. Bank switchable memory system
US4432067A (en) * 1981-05-07 1984-02-14 Atari, Inc. Memory cartridge for video game system
GB2118809A (en) * 1982-01-11 1983-11-02 Atari Inc Self-adjusting game difficulty method and apparatus for electronic games
GB2115989A (en) * 1982-02-12 1983-09-14 Voltmace Limited Programmed cartridge/video machine adaptor
GB2129585A (en) * 1982-10-29 1984-05-16 Inmos Ltd Memory system including a faulty rom array
US4480835A (en) * 1983-03-02 1984-11-06 Williams Theodore R Cartridge adapter for programmable video games
US4485457A (en) * 1983-05-31 1984-11-27 Cbs Inc. Memory system including RAM and page switchable ROM
USD285926S (en) 1983-12-14 1986-09-30 Rockwell International Corp. Housing for interface module
US4860128A (en) * 1985-04-24 1989-08-22 Nintendo Co., Ltd. Recordable data device having identification symbols formed thereon and cooperating data processing system having registering symbols
US5070479A (en) * 1985-06-24 1991-12-03 Nintendo Company Limited External memory having an authenticating processor and method of operating same
US4799635A (en) * 1985-06-24 1989-01-24 Nintendo Co., Ltd. System for determining authenticity of an external memory used in an information processing apparatus
US4763300A (en) * 1985-08-28 1988-08-09 Nintendo Co., Ltd. Front loading apparatus for a memory cartridge utilized for a data processing machine
USRE34161E (en) * 1985-10-04 1993-01-12 Nintendo Company Limited Memory cartridge and information processor unit using such cartridge
US5140110A (en) * 1986-03-13 1992-08-18 Nintendo Co. Ltd. Printed circuit board capable of preventing electromagnetic interference
US4926372A (en) * 1986-05-06 1990-05-15 Nintendo Company Limited Memory cartridge bank selecting
US4984193A (en) * 1986-05-06 1991-01-08 Nintendo Co., Ltd. Memory cartridge
US5226136A (en) * 1986-05-06 1993-07-06 Nintendo Company Limited Memory cartridge bank selecting apparatus
US4844465A (en) * 1986-07-11 1989-07-04 Nintendo Company, Ltd. Adaptor of a cartridge for gaming machine
US4922420A (en) * 1986-07-23 1990-05-01 Nintendo Company Limited Video game software selection data processing system
USD308197S (en) 1986-10-14 1990-05-29 Nintendo Company Limited Adaptor for a game machine cartridge
US4949298A (en) * 1986-11-19 1990-08-14 Nintendo Company Limited Memory cartridge having a multi-memory controller with memory bank switching capabilities and data processing apparatus
EP0268419A2 (en) * 1986-11-19 1988-05-25 Nintendo Co. Limited Memory cartridge and data processing apparatus
US4788537A (en) * 1987-09-17 1988-11-29 Potiker Lowell A Mouse interface assembly
USD315577S (en) 1988-10-04 1991-03-19 Wen-Fu Wang Video game console
USD311737S (en) 1988-12-07 1990-10-30 Plus Development Removable hard disk drive module
US5134391A (en) * 1989-01-10 1992-07-28 Nintendo Company Limited System for preventing the use of an unauthorized external memory
US5112051A (en) * 1989-06-05 1992-05-12 Westinghouse Electric Corp. Interfacing device for a computer games system
US5004232A (en) * 1989-10-13 1991-04-02 Macronix, Inc. Computer game cartridge security circuit

Non-Patent Citations (10)

* Cited by examiner, † Cited by third party
Title
"Mark V Action Replay", Instruction Manual, Datel Electronics, 1988, preface and pp. 1-24.
"Your Sinclair", Nov. 1988 issue, pp. 109, 113 and 114.
"ZAPP! 64", Oct. 1988, preface and p. 65.
"ZAPP! C64 Amiga", Jan. 1989, preface and pp. 58 and 59.
Logan, Dr. Ian, "Spectrum Micro Drive Book", Melbourne House Publishers, 1983, preface and pp. 5-7.
Logan, Dr. Ian, Spectrum Micro Drive Book , Melbourne House Publishers, 1983, preface and pp. 5 7. *
Mark V Action Replay , Instruction Manual, Datel Electronics, 1988, preface and pp. 1 24. *
Your Sinclair , Nov. 1988 issue, pp. 109, 113 and 114. *
ZAPP 64 , Oct. 1988, preface and p. 65. *
ZAPP C64 Amiga , Jan. 1989, preface and pp. 58 and 59. *

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6315669B1 (en) 1998-05-27 2001-11-13 Nintendo Co., Ltd. Portable color display game machine and storage medium for the same
US6322447B1 (en) 1998-05-27 2001-11-27 Nintendo Co., Ltd. Portable color display game machine and storage medium for the same
US7137894B2 (en) 1998-05-27 2006-11-21 Nintendo Co., Ltd. Hand-held display system and display method and storage medium therefor
US6048270A (en) 1998-09-21 2000-04-11 Chiu-Hao; Cheng Data-transfer device
US6386979B1 (en) 1998-11-04 2002-05-14 Std Manufacturing Ltd. Methods and systems for transferring game saves between a game system memory card and a computer
US6565443B1 (en) 1999-09-14 2003-05-20 Innovative Gaming Corporation System and method for verifying the contents of a mass storage device before granting access to computer readable data stored on the device
US7243053B1 (en) 1999-10-22 2007-07-10 Shoot The Moon Products Ii, Llc Method and apparatus for virtual control of operational scale models
US20030189576A1 (en) * 1999-11-24 2003-10-09 Jun Pan Method and apparatus for displaying higher color resolution on a hand-held LCD device
US7050064B2 (en) 1999-11-24 2006-05-23 Nintendo Co., Ltd. Method and apparatus for displaying higher color resolution on a hand-held LCD device
US6373462B1 (en) 1999-12-07 2002-04-16 Nintendo Co., Ltd. Method and apparatus for displaying higher color resolution on a hand-held LCD device
US20060009290A1 (en) * 2000-03-30 2006-01-12 Nintendo Co., Ltd. Game information storage medium and game system using the same
US6955606B2 (en) 2000-03-30 2005-10-18 Nintendo Co., Ltd. Game information storage medium and game system using the same
US8187099B2 (en) 2000-03-30 2012-05-29 Nintendo Co., Ltd. Game method and apparatus for enabling a video game system console to execute video game programs originally written for execution on architecturally different video game platforms
US20010031665A1 (en) * 2000-03-30 2001-10-18 Sagahiro Taho Game information storage medium and game system using the same
US6877096B1 (en) 2000-04-11 2005-04-05 Edward J. Chung Modular computer applications with expandable capabilities
US8821287B2 (en) 2000-05-24 2014-09-02 Nintendo Co., Ltd. Video game display system
US20040268042A1 (en) * 2000-05-24 2004-12-30 Nintendo Co., Ltd. Information processing device and peripheral devices used therewith
US20090069083A1 (en) * 2000-05-24 2009-03-12 Satoru Okada Portable video game system
US6810463B2 (en) 2000-05-24 2004-10-26 Nintendo Co., Ltd. Gaming machine that is usable with different game cartridge types
US7445551B1 (en) 2000-05-24 2008-11-04 Nintendo Co., Ltd. Memory for video game system and emulator using the memory
US9205326B2 (en) 2000-05-24 2015-12-08 Nintendo Co., Ltd. Portable video game system
US7285051B2 (en) 2000-05-25 2007-10-23 Nintendo Co., Ltd. Game information storage medium and game system using the same
US7338376B2 (en) 2000-09-18 2008-03-04 Nintendo Co., Ltd. Video game distribution network
US9839849B2 (en) 2000-09-18 2017-12-12 Nintendo Co., Ltd. Hand-held video game platform emulation
US6672963B1 (en) 2000-09-18 2004-01-06 Nintendo Co., Ltd. Software implementation of a handheld video game hardware platform
US20050130744A1 (en) * 2000-09-18 2005-06-16 Nintendo Co., Ltd Video game distribution network
US8795090B2 (en) 2000-09-18 2014-08-05 Nintendo Co., Ltd. Hand-held video game platform emulation
US8157654B2 (en) 2000-11-28 2012-04-17 Nintendo Co., Ltd. Hand-held video game platform emulation
US7837558B2 (en) 2004-03-31 2010-11-23 Nintendo Co., Ltd. Game console and emulator for the game console
US20090305783A1 (en) * 2004-03-31 2009-12-10 Nintendo Co., Ltd. Game console
US20110092285A1 (en) * 2004-03-31 2011-04-21 Hiroshi Yoshino Game console and emulator for the game console
US7988556B2 (en) 2004-03-31 2011-08-02 Nintendo Co., Ltd. Game console and emulator for the game console
US8016681B2 (en) 2004-03-31 2011-09-13 Nintendo Co., Ltd. Memory card for a game console
US11278793B2 (en) 2004-03-31 2022-03-22 Nintendo Co., Ltd. Game console
US20050245313A1 (en) * 2004-03-31 2005-11-03 Nintendo Co., Ltd. Game console and memory card
US8267780B2 (en) 2004-03-31 2012-09-18 Nintendo Co., Ltd. Game console and memory card
US8337304B2 (en) 2004-03-31 2012-12-25 Nintendo Co., Ltd. Game console
US7771280B2 (en) 2004-03-31 2010-08-10 Nintendo Co., Ltd. Game console connector and emulator for the game console
US20090305792A1 (en) * 2004-03-31 2009-12-10 Nintendo Co., Ltd. Game console and memory card
US8972658B2 (en) 2004-03-31 2015-03-03 Nintendo Co., Ltd. Game console and memory card
US10722783B2 (en) 2004-03-31 2020-07-28 Nintendo Co., Ltd. Game console
US20060111190A1 (en) * 2004-03-31 2006-05-25 Nintendo Co., Ltd. Game console connector and emulator for the game console
US10173132B2 (en) 2004-03-31 2019-01-08 Nintendo Co., Ltd. Game console
US20060094512A1 (en) * 2004-03-31 2006-05-04 Nintendo Co., Ltd. Game console and emulator for the game console
US9259654B2 (en) 2006-11-17 2016-02-16 Nintendo Co., Ltd. System and method for obtaining software programs
US8986112B2 (en) 2006-11-17 2015-03-24 Nintendo Co., Ltd. System and method for downloading video game programs
US20100248823A1 (en) * 2006-11-17 2010-09-30 Smith Darren C System and method for downloadinng video game programs

Also Published As

Publication number Publication date
GB8915975D0 (en) 1989-08-31
GB8912866D0 (en) 1989-07-26

Similar Documents

Publication Publication Date Title
US5112051A (en) Interfacing device for a computer games system
USRE35520E (en) Interfacing device for a computer games system
KR0148364B1 (en) System for preventing the use of an unauthorized external memory
US5184830A (en) Compact hand-held video game system
US4156928A (en) Programmable television game and training system with adaptable operator control
US6315669B1 (en) Portable color display game machine and storage medium for the same
EP0675426B1 (en) Computer system with touchpad support in operating system
US4148014A (en) System with joystick to control velocity vector of a display cursor
US7594854B2 (en) Video game system with data transmitting/receiving controller
US6917356B1 (en) User controlled graphics object movement based on amount of joystick angular rotation and point of view angle
US5802544A (en) Addressing multiple removable memory modules by remapping slot addresses
US6778711B2 (en) Recording medium in which image data conforming to image output devices are stored
RU2135250C1 (en) Control device for game appliance
AU724018B2 (en) Three-dimensional image processor
US6241610B1 (en) Three-dimensional image processing system having dynamically changing character polygon number
US4142180A (en) Digital joystick control interface system for video games and the like
GB1600170A (en) Digital control system
JP3242024B2 (en) Game device, game display method, and recording medium
JP3857894B2 (en) Video game apparatus input control method and computer program for executing the method
KR950007343Y1 (en) Auto-executing circuit for joystick
JPH09167544A (en) Operation device for game machine
KR19990034811A (en) PC's Gaming Keyboard Device
NO312864B1 (en) Handheld, electronic gaming machine

Legal Events

Date Code Title Description
AS Assignment

Owner name: CODEMASTERS SOFTWARE COMPANY LIMITED, ENGLAND

Free format text: CHANGE OF ADDRESS;ASSIGNOR:CODEMASTERS SOFTWARE COMPANY LIMITED;REEL/FRAME:007466/0784

Effective date: 19950428

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12