US20170301619A1 - Integrated circuit surface layer with adhesion-functional group - Google Patents
Integrated circuit surface layer with adhesion-functional group Download PDFInfo
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- US20170301619A1 US20170301619A1 US15/641,117 US201715641117A US2017301619A1 US 20170301619 A1 US20170301619 A1 US 20170301619A1 US 201715641117 A US201715641117 A US 201715641117A US 2017301619 A1 US2017301619 A1 US 2017301619A1
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Definitions
- FIG. 1 schematically illustrates a cross-section view of an example integrated circuit (IC) die 100 with layers 102 and 104 , in accordance with some embodiments.
- the die 100 may represent a discrete product made on a substrate of semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching, and the like used in connection with forming IC devices.
- the die 100 may be, include, or be a part of a radio frequency (RF) die, a processor, memory, system-on-chip (SoC), or ASIC, for example.
- RF radio frequency
- SoC system-on-chip
- the method 400 may include heat-treating the die to affix the dielectric layer to the metal layer.
- heat-treating may arise by contact and elevated temperature of a rubber press or a steel press, or by a final IC polymer cure, which may provide a more prolonged heat-treatment period.
- the communication chip 606 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
- GSM Global System for Mobile Communication
- GPRS General Packet Radio Service
- UMTS Universal Mobile Telecommunications System
- High Speed Packet Access HSPA
- E-HSPA Evolved HSPA
- LTE LTE network.
- the communication chip 606 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
- EDGE Enhanced Data for GSM Evolution
- GERAN GSM EDGE Radio Access Network
- UTRAN Universal Terrestrial Radio Access Network
- E-UTRAN Evolved UTRAN
- the computing device 600 may include a plurality of communication chips 606 .
- a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
- Example 2 may include the method of example 1, wherein the at least one of the metal layer or the polymer layer is a polymer layer and forming the surface layer includes copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group.
- Example 47 may include the method of example 45 in which applying the dielectric layer on the surface layer includes applying a dielectric epoxy resin.
Abstract
Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.
Description
- This application is a divisional application of U.S. patent application Ser. No. 14/972,936, entitled “INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP”, filed Dec. 17, 2015, and claims priority to the Ser. No. 14/972,936 application. The Specification of Ser. No. 14/972,936 is hereby fully incorporated by reference.
- Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to adhesion-receptive surfaces for integrated circuit die layers and associated techniques and configurations.
- Currently, integrated circuit dies include successive layers, such as polymer/polymer, polymer/metal or polymer/silica, between which there may be low adhesion. Techniques to improve adhesion between polymer/polymer and polymer/silica layers may include plasma or ultra-violet (UV) treatment of the surfaces to enhance the surface area or surface energy. Techniques to improve adhesion between polymer and an underlying metal layer may include etching of the metal, but etching may degrade electrical performance or patterning.
- Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
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FIG. 1 schematically illustrates a cross-section view of an example integrated circuit (IC) die, in accordance with some embodiments. -
FIG. 2 schematically illustrates a flow diagram for a method of fabricating an IC, in accordance with some embodiments. -
FIG. 3 schematically illustrates a cross-section view of another example IC die, in accordance with some embodiments. -
FIG. 4 schematically illustrates a flow diagram for another method of fabricating an IC, in accordance with some embodiments. -
FIG. 5 schematically illustrates a flow diagram for a method of forming a self-assembled monolayer (SAM) on a metal layer of a die, in accordance with some embodiments. -
FIG. 6 schematically illustrates a computing device incorporating some aspects of embodiments described herein, in accordance with some embodiments. - Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations.
- In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
- For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
- The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
- The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.
- In various embodiments, the phrase “a first layer formed on a second layer” may mean that the first layer is formed over the second layer, and at least a part of the first layer may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other layers between the first layer and the second layer) with at least a part of the second layer.
- In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature,” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
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FIG. 1 schematically illustrates a cross-section view of an example integrated circuit (IC) die 100 withlayers -
Layers layer 102 may be of or include a polymer and may be referred to aspolymer layer 102.Polymer layer 102 may be formed upon one or more die layers 106 (only one shown), which may include a semiconductor substrate.Layer 104 may be applied to die 100 afterpolymer layer 102 and may be formed of or include metal, silica or polymer. An adhesion-receptive surface 108 may be formed betweenlayers receptive surface 108 enhance adhesion betweenlayers polymer layer 102. - In embodiments, a
layer 110 may optionally be applied to die 100 afterlayer 104.Layer 104 and/or 110 may be incorporated onto die 100 or may be an embedding or encapsulating material that embeds or encapsulates die 100 in or as part of an IC package or package assembly (not shown). -
FIG. 2 schematically illustrates a flow diagram for amethod 200 of fabricating an IC, in accordance with some embodiments. Themethod 200 may comport with the configuration of die 100 inFIG. 1 , for example. - At 202, the
method 200 may include dispensing on a polymer layer of a die a solution that includes a polar monomer and a photoinitiator. In embodiments, the polymer layer may bepolymer layer 102, and the polar monomer may include an adhesion-functional group that functionalizes adhesion between the polymer layer and the next layer. In embodiments, the functional group may include an amine group if the next layer includes or is of silica, a cyano group if the next layer includes or is of a metal such as copper (Cu), or a hydroxyl group if the next layer includes or is of a polymer. Dispensing the solution on the polymer layer may include applying the solution in liquid form, such as by dipping the die and the polymer layer into the solution. In other embodiments, the polar monomer may include more than one adhesion-functional group to functionalize adhesion between the polymer layer and the next layer. In embodiments, the more than one functional groups may include an amine group and a cyano group if the next layer includes or is of a metal such as copper, or may include an amine group and a hydroxyl group if the next layer includes or is of silica. - At 204, the
method 200 may include exposing the solution on the polymer layer to light to form on the polymer layer an adhesion-receptive polymer surface, which may also be referred to as a surface layer that includes an adhesion-functional group. In embodiments, the light may be ultra-violet light that may graft copolymerize the polar monomer on the polymer layer to form the adhesion-receptive polymer surface. The adhesion-receptive polymer surface may correspond to adhesion-receptive surface 108 ofFIG. 1 . - At 206, the
method 200 may include applying a next layer to the adhesion-receptive polymer surface to affix the next layer to the polymer layer. In embodiments, the next layer applied to the adhesion-receptive polymer surface may be formed of or include materials that may include metal, silica, or polymer. The next layer may correspond tolayer 104 ofFIG. 1 . In embodiments, the next layer may be of or include silica if the functional group of the polar monomer at 202 includes an amine group, the next layer may be of or include a metal such as copper (Cu) if the functional group of the polar monomer at 202 includes a cyano group, or the next layer may be of or include a polymer if the functional group of the polar monomer at 202 includes or a hydroxyl group. In other embodiments, the next layer may be of or include a metal such as copper if the polar monomer includes more than one adhesion-functional group, such as an amine group and a cyano group, and the next layer may be of or include silica if the polar monomer includes more than one adhesion-functional group, such as an amine group and a hydroxyl group. - The
method 200 may provide topolymer layer 102 the adhesion-receptive surface layer 108 without affecting properties of the bulk ofpolymer layer 102. In embodiments,polymer layer 102 may be free from adhesion-functional groups by which adhesion-receptive surface layer 108 may functionalize adhesion betweenpolymer layer 102 and thenext layer 104. Adhesion-functional groups included in the bulk ofpolymer layer 102 may adversely affect mechanical and/or electrical properties ofpolymer layer 102, including any or all of high modulus, low CTE, low dielectric loss, etc., which may adversely affect reliability of an IC.Polymer layer 102 may be free from adhesion-functional groups such that adhesion-functional groups are completely or sufficiently absent from the bulk ofpolymer layer 102 that its mechanical and/or electrical properties are substantially unchanged. In embodiments, adhesion-receptive surface layer 108 may include an adhesion-functional group, andpolymer layer 102 may be free from the adhesion-functional group. - In embodiments, the adhesion-receptive polymer surface provided by
method 200 may be very thin (40-50 nm) and uniform. The uniformity may smooth out issues that may be observed after some wet or dry process treatments. The adhesion-receptive polymer surface provided bymethod 200 may also enable polymer surfaces with higher surface energy and wettability. In embodiments, polar functional groups (e.g., carboxylic acid, amides, alcohols, etc.) may be employed to improve surface energy and/or wettability without resorting to plasma or UV treatment. If used for a solder resist layer, for example,method 200 may resolve or decrease solder resist surface transparency issues. - Die embedding in a polymer material may be employed in some IC packages and package assemblies, including system-in-package technologies that may include more than one IC die. Delamination between an embedded IC die and an encapsulating dielectric may be a serious reliability issue.
Method 200 may improve wettability for subsequent polymers included in mold, underfill, or encapsulant materials. A polymer or dielectric may be functionalized through graft polymerization with adhesion-functional groups, which may include amines or silanols, to bind embedding surfaces with greater reliability. -
FIG. 3 schematically illustrates a cross-section view of another example IC die 300 withlayers die 300 may represent a discrete product made on a substrate of semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching, and the like used in connection with forming IC devices. In embodiments, thedie 300 may be, include, or be a part of a radio frequency (RF) die, a processor, memory, system-on-chip (SoC), or ASIC, for example. -
Layers die 300. In embodiments,layer 302 may be of or include a metal (e.g., copper) and may be referred to asmetal layer 302.Metal layer 302 may be formed upon one or more die layers 306 (only one shown), which may include a semiconductor substrate.Layer 304 may be applied to die 300 aftermetal layer 302 and may be formed of or include polymer. An adhesion-receptive surface 308 may be formed betweenlayers layer 310 may optionally be applied to die 300 afterlayer 304.Layer 304 and/or 310 may be incorporated ontodie 300 or may be an embedding or encapsulating material that embeds or encapsulates die 300 in or as part of an IC package or package assembly (not shown). -
FIG. 4 schematically illustrates a flow diagram for a method 400 of fabricating an IC, in accordance with some embodiments. The method 400 may comport with the configuration ofdie 300 inFIG. 3 , for example. - At 402, the method 400 may include forming on a metal layer (e.g., copper) of a die a self-assembled monolayer (SAM) that includes amine group terminations. The SAM may be referred to as a surface layer that includes an adhesion-functional group. In embodiments, the metal layer may be
metal layer 302, and forming the SAM may include applying to the metal layer an ethanolic solution that includes an alkane thiol with a terminal amine group, as described in greater detail below. The amine group may be referred to as an adhesion-functional group that functionalizes adhesion between the metal layer and the next layer. - At 404, the method 400 may include applying a dielectric layer on the surface layer. In embodiments, the dielectric layer may include an epoxy resin.
- At 406, the method 400 may include heat-treating the die to affix the dielectric layer to the metal layer. In embodiments, heat-treating may arise by contact and elevated temperature of a rubber press or a steel press, or by a final IC polymer cure, which may provide a more prolonged heat-treatment period.
- SAMs are instances of molecular interactions that lead to supramolecular order. In embodiments, alkanes having a head group with an affinity for a surface may assemble in a close-packed network (e.g., in order to maximize van der Waals interactions). To promote adhesion with a dielectric layer, a terminal amine group may provide a chemical moiety to bond to the layer with enhanced adhesion. In embodiments, a dielectric layer may include an epoxy resin, which may include a high density of epoxide groups. Amine groups may be reactive with epoxides, and amine-based molecules may function as hardening agents for epoxy resins. Thus, after applying a dielectric layer at 404 and heat-treating at 406, covalent bonding between the SAM and the dielectric layer may be established. In embodiments, method 400 may enhance adhesion between copper and a polymer or dielectric layer with chemical interactions or bonds, rather than mechanical interactions. Chemical interactions are individually small or weak. However, when provided at sufficient density, as may be provided the SAM, chemical interaction may provide substantial adhesion.
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FIG. 5 schematically illustrates a flow diagram for amethod 500 of forming a self-assembled monolayer (SAM) on a metal layer (e.g., copper) of a die, in accordance with some embodiments. - At 502,
method 500 may include surface cleaning the metal layer. In embodiments, the surface cleaning may include an acid rinse in an aqueous solution of sulfuric acid to remove oxides from the surface of the metal layer. - At 504,
method 500 may include immersing the die in a SAM bath. In embodiments, the SAM bath may include may include an alkane thiol, such as 11-amino-1-undecanethiol, with a terminal amine group. - At 506,
method 500 may include applying a rinse bath to the die. In embodiments, applying the rinse bath to the die may include immersing the die in an ethanol bath to remove un-bonded thiol. -
Methods 400 and 500 may be performed on a metal layer, such as patterned copper, as an alternative to “CZ” chemistry.Methods 400 and 500 may be improvements over copper-roughening chemistry, which may uses many baths to facilitate oxidative etching. - Various operations are described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order-dependent. For example, actions of the method 400 may be performed in another suitable order than depicted.
- Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software.
FIG. 6 schematically illustrates acomputing device 600 that may include an IC as described herein, in accordance with some embodiments. Thecomputing device 600 may house a board such asmotherboard 602. Themotherboard 602 may include a number of components, including but not limited to aprocessor 604 and at least onecommunication chip 606. Theprocessor 604 may be physically and electrically coupled to themotherboard 602. In some implementations, the at least onecommunication chip 606 may also be physically and electrically coupled to themotherboard 602. In further implementations, thecommunication chip 606 may be part of theprocessor 604. In some embodiments, theprocessor 604 and/orchip 606 may comprise an IC, such asIC FIGS. 1 and 3 . - Depending on its applications,
computing device 600 may include other components that may or may not be physically and electrically coupled to themotherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Theprocessor 604 of thecomputing device 600 may be packaged in a stacked IC package assembly with a memory, as described herein, and/or other components may be packaged together in a stacked IC package assembly with a memory, as described herein. - The
communication chip 606 may enable wireless communications for the transfer of data to and from thecomputing device 600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Thecommunication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 502.11 family), IEEE 502.16 standards (e.g., IEEE 502.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 502.16 compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 502.16 standards. Thecommunication chip 606 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Thecommunication chip 606 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Thecommunication chip 606 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Thecommunication chip 606 may operate in accordance with other wireless protocols in other embodiments. - The
computing device 600 may include a plurality ofcommunication chips 606. For instance, afirst communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and asecond communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. - In various implementations, the
computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In an embodiment, thecomputing device 600 may be a mobile computing device. In further implementations, thecomputing device 600 may be any other electronic device that processes data. - Some non-limiting examples are provided below.
- Example 1 may include a method of fabricating an integrated circuit (IC), the method comprising: forming on at least one of a metal layer or a polymer layer of a die a surface layer that includes an adhesion-functional group; and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group.
- Example 2 may include the method of example 1, wherein the at least one of the metal layer or the polymer layer is a polymer layer and forming the surface layer includes copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group.
- Example 3 may include the method of example 2, wherein forming the surface layer further comprises: dispensing on the polymer layer a solution that includes a photoinitiator and the polar monomer with the adhesion-functional group; and exposing the solution to light to form the surface layer on the polymer layer.
- Example 4 may include the method of example 3 wherein exposing the solution to light copolymerizes the polar monomer on the polymer layer.
- Example 5 may include the method of any of examples 2-4 wherein the adhesion-functional group includes an amine group.
- Example 6 may include the method of example 5 wherein the next layer includes silica.
- Example 7 may include the method of any of examples 2-4 wherein the adhesion-functional group includes a cyano group.
- Example 8 may include the method of example 7 wherein the next layer includes a metal.
- Example 9 may include the method of any of examples 2-4 wherein the adhesion-functional group includes a hydroxyl group.
- Example 10 may include the method of any examples 2-4 wherein the next layer includes a second polymer layer.
- Example 11 may include the method of example 2 wherein the polar monomer further includes a second adhesion-functional group.
- Example 12 may include the method of example 1, wherein the at least one of the metal layer or the polymer layer is a metal layer and forming the surface layer includes forming on the metal layer a self-assembled monolayer that includes amine group terminations.
- Example 13 may include the method of example 12, wherein applying the next layer further comprises: forming the next layer as a dielectric layer; and heat-treating the die to affix the dielectric layer to the metal layer.
- Example 14 may include the method of any of examples 12-13 wherein forming the self-assembled monolayer includes applying to the metal layer an ethanolic solution that includes an alkane thiol with a terminal amine group.
- Example 15 may include the method of example 14 wherein applying the solution to the metal layer includes immersing the die in the solution.
- Example 16 may include an integrated circuit (IC), comprising: a polymer layer of a first monomer on a die; a polymer surface layer with a polar monomer that is copolymerized on the polymer layer, wherein the polar monomer includes a functional group and the polymer layer is free from the functional group.
- Example 17 may include the IC of example 16 further comprising a subsequent layer applied to the polymer surface layer with adhesion functional by the functional group.
- Example 18 may include the IC of example 16 wherein the functional group includes an amine group.
- Example 19 may include the IC of example 16 wherein the functional group includes a cyano group.
- Example 20 may include the IC of example 19 wherein the next layer includes a metal.
- Example 21 may include the IC of example 16 wherein the functional group includes a hydroxyl group.
- Example 22 may include the IC of example 18 in which the next layer includes silica.
- Example 23 may include the IC of example 21 in which the next layer includes a solder resist.
- Example 24 may include the IC of example 16 in which the next layer includes a second polymer layer.
- Example 25 may include the IC of example 24 in which the second polymer layer embeds the die in an IC package assembly.
- Example 26 may include the IC of example 24 in which the second polymer layer includes an underfill material.
- Example 27 may include an integrated circuit (IC), comprising: a die with multiple layers that include a metal layer; a surface layer on the metal layer, wherein the surface layer includes amine group terminations; and a heat-treated dielectric layer on the surface layer.
- Example 28 may include the IC of example 27 wherein the surface layer includes a self-assembled monolayer.
- Example 29 may include the IC of example 28 wherein the self-assembled monolayer is thiol-based.
- Example 30 may include a method of fabricating an integrated circuit (IC), the method comprising: providing a die with a polymer layer; dispensing on the polymer layer a solution that includes a polar monomer and a photoinitiator; exposing the solution to light to form on the polymer layer an adhesion-receptive polymer surface; and applying a next layer to the adhesion-receptive polymer surface.
- Example 31 may include the method of example 30 in which exposing the solution to light copolymerizes the polar monomer on the polymer layer to form the adhesion-receptive polymer surface.
- Example 32 may include the method of example 30 in which the polar monomer includes an amine group.
- Example 33 may include the method of example 32 in which the next layer includes silica.
- Example 34 may include the method of example 30 in which the polar monomer includes a cyano group.
- Example 35 may include the method of example 34 in which the next layer includes a metal.
- Example 36 may include the method of example 30 in which the polar monomer includes a hydroxyl group.
- Example 37 may include the method of example 36 in which the next layer includes a solder resist.
- Example 38 may include the method of example 30 in which the next layer includes a second polymer layer.
- Example 39 may include the method of example 30 in which the light includes ultra-violet light.
- Example 40 may include a method of fabricating an integrated circuit (IC), the method comprising: providing a die with a first metal layer; forming on the metal layer a self-assembled monolayer that includes amine group terminations; forming a dielectric layer on the self-assembled monolayer; and heat-treating the die.
- Example 41 may include the method of example 40 in which forming the self-assembled monolayer includes applying to the first metal layer a solution that includes an alkane thiol with a terminal amine group.
- Example 42 may include the method of example 41 in which the solution is ethanolic.
- Example 43 may include the method of any of examples 41-42 in which applying the solution to the first metal layer includes immersing the die in the solution.
- Example 44 may include the method of example 40 in which forming a dielectric layer on the self-assembled monolayer includes applying a dielectric epoxy resin.
- Example 45 may include a method of fabricating an integrated circuit (IC), the method comprising: providing a die with a first metal layer; applying to the first metal layer an ethanolic solution that includes an alkane thiol with a terminal amine group to form a surface layer with amine group terminations; applying a dielectric layer on the surface layer; and heat-treating the die.
- Example 46 may include the method of example 45 in which applying the ethanolic solution to the first metal layer includes immersing the die in the ethanolic solution.
- Example 47 may include the method of example 45 in which applying the dielectric layer on the surface layer includes applying a dielectric epoxy resin.
- The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.
- These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Claims (13)
1. An integrated circuit (IC), comprising:
a die;
a polymer layer formed on a die; and
a surface layer comprising a polar monomer that is copolymerized on the polymer layer in response to exposure of a solution disposed on the polymer layer to light, wherein the solution includes a photoinitiator and a polar monomer with an adhesion-functional group, wherein the polymer layer is free from the adhesion-functional group.
2. The IC of claim 1 further comprising a next layer applied to the polymer surface layer with adhesion functional by the adhesion-functional group.
3. The IC of claim 2 wherein the adhesion-functional group includes an amine group.
4. The IC of claim 3 , wherein the next layer includes silica.
5. The IC of claim 2 , wherein the adhesion-functional group includes a cyano group.
6. The IC of claim 5 , wherein the next layer includes a metal.
7. The IC of claim 1 , wherein the adhesion-functional group includes a hydroxyl group.
8. The IC of claim 1 , wherein the next layer includes another polymer layer.
9. The IC of claim 1 , wherein the polar monomer further includes another adhesion-functional group.
10. An integrated circuit (IC), comprising:
a die with multiple layers that include a metal layer;
a surface layer disposed on the metal layer, wherein the surface layer comprises an adhesion-functional group and amine group terminations; and
a next layer disposed on the surface layer, wherein the next layer is adhered to the surface layer with the adhesion-functional group.
11. The IC of claim 10 , wherein the surface layer includes a self-assembled monolayer.
12. The IC of claim 11 , wherein the self-assembled monolayer is thiol-based.
13. The IC of claim 10 , wherein the next layer comprises a heat-treated dielectric layer.
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10844658B2 (en) | 2017-02-27 | 2020-11-24 | Alliance For Sustainable Energy, Llc | Energy-harvesting chromogenic devices |
US11043335B2 (en) | 2017-05-10 | 2021-06-22 | Alliance For Sustainable Energy, Llc | Multilayer carbon nanotube film-containing devices |
US11177396B2 (en) | 2017-12-22 | 2021-11-16 | Alliance For Sustainable Energy, Llc | Window-integrated photovoltaic devices |
US11319334B2 (en) * | 2017-12-28 | 2022-05-03 | Intel Corporation | Site-selective metal plating onto a package dielectric |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4218508A (en) * | 1978-04-12 | 1980-08-19 | General Electric Company | Polycarbonate articles coated with an adherent, durable silica filled organopolysiloxane coating and process for producing same |
US6130171A (en) * | 1997-11-18 | 2000-10-10 | Nec Corporation | Residue removal process for forming inter-level insulating layer of paraylene polymer without peeling |
US6143670A (en) * | 1998-12-28 | 2000-11-07 | Taiwan Semiconductor Manufacturing Company | Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer |
US20010046011A1 (en) * | 1996-10-22 | 2001-11-29 | Masahiro Yasukawa | Liquid crystal panel substrate liquid crystal panel and electronic device and projection display device using the same |
US6531340B2 (en) * | 2001-02-23 | 2003-03-11 | Micron Technology, Inc. | Low temperature die attaching material for BOC packages |
US20070065638A1 (en) * | 2005-09-20 | 2007-03-22 | Eastman Kodak Company | Nano-structured thin film with reduced light reflection |
US20070207186A1 (en) * | 2006-03-04 | 2007-09-06 | Scanlon John J | Tear and abrasion resistant expanded material and reinforcement |
US20090186306A1 (en) * | 2007-11-09 | 2009-07-23 | Klas Tommy Haraldsson | Polymeric microfluidic devices from liquid thermoset precursors |
US20090301561A1 (en) * | 2008-06-06 | 2009-12-10 | Optisolar Inc. | Coating composition, substrates coated therewith and methods of making and using same |
US20100032660A1 (en) * | 2008-08-07 | 2010-02-11 | Sony Corporation | Organic thin film transistor, production method thereof, and electronic device |
US20110186830A1 (en) * | 2008-08-05 | 2011-08-04 | Cambridge Display Technology Limited | Method of Making Organic Thin Film Transistors Using a Laser Induced Thermal Transfer Printing Process |
US20130299953A1 (en) * | 2012-05-11 | 2013-11-14 | Robert L. Hubbard | Method for lower thermal budget multiple cures in semiconductor packaging |
US20160016395A1 (en) * | 2014-07-21 | 2016-01-21 | Apple Inc. | Device Structures Bonded With Adhesive Films |
US9565773B2 (en) * | 2014-03-31 | 2017-02-07 | Apple Inc. | Methods for assembling electronic devices with adhesive |
US20170186874A1 (en) * | 2013-11-28 | 2017-06-29 | Tohoku University | Method of production of semiconductor device |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4767674A (en) * | 1984-01-27 | 1988-08-30 | Dainichi-Nippon Cables, Ltd. | Metal cored board and method for manufacturing same |
JP2002513512A (en) * | 1997-04-03 | 2002-05-08 | ダブリュ.エル.ゴア アンド アソシエーツ,インコーポレイティド | Low dielectric constant material with improved dielectric strength |
IT1307040B1 (en) | 1999-05-31 | 2001-10-23 | Alfachimici Spa | PROCEDURE FOR PROMOTING ADHERENCE BETWEEN AN INORGANIC SUBSTRATE AND AN ORGANIC POLYMER. |
TW572980B (en) * | 2000-01-12 | 2004-01-21 | Jsr Corp | Aqueous dispersion for chemical mechanical polishing and chemical mechanical polishing process |
US20050085031A1 (en) | 2003-10-15 | 2005-04-21 | Applied Materials, Inc. | Heterogeneous activation layers formed by ionic and electroless reactions used for IC interconnect capping layers |
US7265381B2 (en) * | 2004-12-30 | 2007-09-04 | Infineon Technologies, Ag | Opto-electronic memory element on the basis of organic metalloporphyrin molecules |
US7972905B2 (en) * | 2009-04-16 | 2011-07-05 | Texas Instruments Incorporated | Packaged electronic device having metal comprising self-healing die attach material |
US9257330B2 (en) | 2013-11-27 | 2016-02-09 | Applied Materials, Inc. | Ultra-thin structure to protect copper and method of preparation |
US9147603B2 (en) | 2014-01-23 | 2015-09-29 | Intel Corporation | Polymer grafting for enhanced dielectric and interconnect material adhesion |
-
2015
- 2015-12-17 US US14/972,936 patent/US9728500B2/en active Active
-
2016
- 2016-11-10 WO PCT/US2016/061275 patent/WO2017105683A1/en active Application Filing
-
2017
- 2017-07-03 US US15/641,117 patent/US20170301619A1/en not_active Abandoned
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4218508A (en) * | 1978-04-12 | 1980-08-19 | General Electric Company | Polycarbonate articles coated with an adherent, durable silica filled organopolysiloxane coating and process for producing same |
US20010046011A1 (en) * | 1996-10-22 | 2001-11-29 | Masahiro Yasukawa | Liquid crystal panel substrate liquid crystal panel and electronic device and projection display device using the same |
US6130171A (en) * | 1997-11-18 | 2000-10-10 | Nec Corporation | Residue removal process for forming inter-level insulating layer of paraylene polymer without peeling |
US6143670A (en) * | 1998-12-28 | 2000-11-07 | Taiwan Semiconductor Manufacturing Company | Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer |
US6531340B2 (en) * | 2001-02-23 | 2003-03-11 | Micron Technology, Inc. | Low temperature die attaching material for BOC packages |
US20070065638A1 (en) * | 2005-09-20 | 2007-03-22 | Eastman Kodak Company | Nano-structured thin film with reduced light reflection |
US20070207186A1 (en) * | 2006-03-04 | 2007-09-06 | Scanlon John J | Tear and abrasion resistant expanded material and reinforcement |
US20090186306A1 (en) * | 2007-11-09 | 2009-07-23 | Klas Tommy Haraldsson | Polymeric microfluidic devices from liquid thermoset precursors |
US20090301561A1 (en) * | 2008-06-06 | 2009-12-10 | Optisolar Inc. | Coating composition, substrates coated therewith and methods of making and using same |
US20110186830A1 (en) * | 2008-08-05 | 2011-08-04 | Cambridge Display Technology Limited | Method of Making Organic Thin Film Transistors Using a Laser Induced Thermal Transfer Printing Process |
US20100032660A1 (en) * | 2008-08-07 | 2010-02-11 | Sony Corporation | Organic thin film transistor, production method thereof, and electronic device |
US20130299953A1 (en) * | 2012-05-11 | 2013-11-14 | Robert L. Hubbard | Method for lower thermal budget multiple cures in semiconductor packaging |
US20170186874A1 (en) * | 2013-11-28 | 2017-06-29 | Tohoku University | Method of production of semiconductor device |
US9565773B2 (en) * | 2014-03-31 | 2017-02-07 | Apple Inc. | Methods for assembling electronic devices with adhesive |
US20160016395A1 (en) * | 2014-07-21 | 2016-01-21 | Apple Inc. | Device Structures Bonded With Adhesive Films |
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US20170179019A1 (en) | 2017-06-22 |
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