US20060224857A1 - Locking entries into translation lookaside buffers - Google Patents

Locking entries into translation lookaside buffers Download PDF

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Publication number
US20060224857A1
US20060224857A1 US11/092,432 US9243205A US2006224857A1 US 20060224857 A1 US20060224857 A1 US 20060224857A1 US 9243205 A US9243205 A US 9243205A US 2006224857 A1 US2006224857 A1 US 2006224857A1
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lookaside buffer
translation lookaside
translation
managed
software
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US11/092,432
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Dennis O'Connor
Stephen Strazdus
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Micron Technology Inc
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Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: O'CONNOR, DENNIS M., STRAZDUS, STEPHEN J.
Publication of US20060224857A1 publication Critical patent/US20060224857A1/en
Priority to US13/197,221 priority patent/US9842058B2/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NUMONYX B.V.
Assigned to NUMONYX B.V. reassignment NUMONYX B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTEL CORPORATION
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning

Definitions

  • This invention relates generally to computer systems and, particularly, to handling of memory access operations.
  • a translation-lookaside buffer (TLB) is employed by microprocessors to provide the translation of linear addresses to physical addresses.
  • the TLB caches linear addresses and corresponding physical addresses.
  • the TLB is initially accessed to determine whether the TLB contains the physical address corresponding to a linear address, identifying a desired memory location. If the linear address is found within the TLB, a “hit” is said to have occurred. The physical address is merely loaded out of the TLB. If the linear and physical addresses are not cached within the TLB, then a TLB “miss” is said to have occurred. In which case, a page miss handler is used to perform a page table walk to determine the physical address corresponding to the desired linear address.
  • TLBs allow some entries to be locked. Some performance critical translations may be locked into the TLB to ensure that the slower page table walk operation will not be triggered when one of those translations is needed. However, determining whether there was a place to lock a particular translation often involves a detailed knowledge of the TLB architecture and detailed tracking of the entries that were locked. The architecture of the TLB may limit the kinds of entries that may be locked into it.
  • FIG. 1 is a block diagram of one embodiment of the present invention.
  • FIG. 2 is a flow chart for the embodiment shown in FIG. 1 in accordance with one embodiment of the present invention.
  • a computer system shown in FIG. 1 , includes a processor 105 coupled to a processor bus 135 .
  • the processor 105 may be a general purpose microprocessor, a complex instruction set computer, a reduced instruction set computer, a very long instruction word, or a hybrid architecture, to mention a few examples.
  • the processor 105 is an out-of-order processor capable of performing operations either out of order or speculatively.
  • the present invention is applicable to any type of processor, including out-of-order and in-order processors.
  • the MCH 140 includes a memory controller 145 and an input/output (I/O) controller 150 .
  • I/O input/output
  • main memory 155 is coupled to the processor bus 135 through the MCH 140 .
  • the processor 105 generates instructions (also referred to herein as micro-operations or “micro-ops”), such as memory loads, stores, and pre-fetches.
  • the micro-ops are, in general, in a sequence that may differ from the sequence in which the instructions appear within a computer program.
  • Micro-ops which involve memory accesses, such as memory loads, stores, and pre-fetches, are executed by a memory management unit (MMU) 110 .
  • MMU memory management unit
  • the MMU 110 includes, among other things, a cache unit 115 , a page miss handler (PMH) 120 , a software managed translation lookaside buffer 125 , a hardware managed translation lookaside buffer 130 with a page table walk logic 165 , the buffers 125 , 130 coupled to a central processing unit (CPU) bus 175 by a multiplexer 170 .
  • the cache unit 115 may comprise a first level (L0) cache memory and a second level (L1) cache memory.
  • the L0 and L1 cache memories may be integrated into a single device.
  • the L1 cache memory may be coupled to the processor 105 by a shared bus (not shown).
  • the main memory 155 and the cache unit 115 store sequences of instructions and data that are executed by the processor 105 .
  • the main memory 155 includes a dynamic random access memory (DRAM); however, the main memory 155 may have other configurations as well.
  • DRAM dynamic random access memory
  • Additional devices may also be coupled to the memory controller hub 140 , such as multiple main memory devices or a wireless interface 185 .
  • the interface 185 may be a dipole antenna for example, to enable radio frequency communications.
  • the memory controller 145 coordinates data transfer to and from the main memory 155 at the request of the processor 105 and/or I/O devices 160 . Data and/or sequences of instructions, executed by the processor 105 , may be retrieved from the main memory 155 , the cache unit 115 , or other storage devices.
  • a computer system has been described in terms of a single processor; however, multiple processors may be coupled to the processor bus 135 .
  • the TLB 125 maintains a mapping of address translations between linear addresses and corresponding physical addresses.
  • a memory access type micro-op When a memory access type micro-op is loaded into an execution pipeline, it is intercepted by TLB 125 , which performs a lookup to determine whether its internal cache lines contain the physical address corresponding to the linear address of the micro-op. If the address translation is found therein, i.e., if a hit occurs, TLB 125 re-dispatches a micro-op, updated to include the physical address. If a miss occurs, TLB 125 notifies the hardware managed translation lookaside buffer 130 . If a hit occurs, the TLB 130 re-dispatches a micro-op, updated to include the physical address. If a miss occurs, the TLB 130 notifies the PMH 120 that a page walk must be performed to determine the physical address corresponding to the linear address of the micro-op.
  • the page table walk may be performed by hardware, microcode, or other types of
  • a micro-op containing, among other things, information relating to the type of instruction and a sequence number is generated and loaded in a pipeline.
  • the processor 105 generates a wide variety of micro-ops, only memory access micro-ops, such as pre-fetch, load, and stored, are handled here.
  • software 220 executed by the processor 105 and stored, for example, within the MMU 110 , begins as shown in FIG. 2 , by checking both TLBs 125 and 130 for a translation (block 202 ). If the translation is in TLB 125 as determined in diamond 204 , the translation is returned from TLB 125 as indicated a block 214 .
  • a check at diamond 206 determines whether the translation is in TLB 130 . If so, the translation is returned from TLB 130 as indicated in block 208 . If the translation is not found in either TLB, the translation must be obtained from a page table walk logic as indicated in block 210 . The translation is then put in the TLB 130 , as indicated in block 212 , and returned from TLB 130 as indicated in block 208 .
  • the sequence of steps shown in FIG. 2 may also be implemented by hardware or microcode.
  • TLB 130 is managed primarily by hardware, using any number of known hardware-resident algorithms to decide which translations to put, replace, or invalidate within itself.
  • Software commands to manage TLB 130 may also exist, but may not provide the ability to lock entries into TLB 130 in some embodiments.
  • TLB 125 is managed entirely via software commands that add and remove entries. TLB 125 can have translations locked into it. The software managed TLB 125 may not use page table walk logic 165 . The page table walk logic is only handled by the TLB 130 .
  • TLB 130 may be a 128-entry, 4-way set associative cache.
  • TLB 125 may be an 8-entry, fully-associative cache in one embodiment of the present invention.
  • the TLBs 125 and 130 may also handle different ranges of page sizes.
  • both TLBs may be consulted in parallel or sequentially.
  • TLB 125 the software managed TLB, takes precedence in one embodiment. If the requested translation is not found in either TLB, then the hardware managed TLB 130 sends a request to the page table walk logic 165 , caches the result according to its hardware resident replacement policies, and returns the translation to the requester. With a processor 105 , having elevated security modes, managing the software managed TLB 125 may be restricted to that mode, while less privileged modes may be allowed to manage the hardware managed TLB 130 .
  • the complexity inherent in locking translations in hardware managed TLBs may be avoided. Determining whether there was a place to lock a particular translation in a hardware managed TLB often involves detailed knowledge of the TLB architecture and detailed tracking of the entries that were locked.
  • the architecture of hardware managed TLBs may also limit the kind of entries that can be locked into hardware managed TLBS. For example, only 4-kilobyte pages may be locked in some cases.
  • the hardware complexity issues may be lessened by using two translation lookaside buffers, coupled together by a simple mechanism.
  • the software's job of locking translations may be made simpler, in some embodiments, because it has a more flexible translation lookaside buffer to manage without having to be concerned about interaction with the hardware managed translation lookaside buffer.

Abstract

Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside buffer may be particularly involved in locking particular translations. As a result, the software's job is made simpler since it has a relatively simpler, software managed translation lookaside buffer to manage for locking translations.

Description

    BACKGROUND
  • This invention relates generally to computer systems and, particularly, to handling of memory access operations.
  • To facilitate memory access operations, a translation-lookaside buffer (TLB) is employed by microprocessors to provide the translation of linear addresses to physical addresses. The TLB caches linear addresses and corresponding physical addresses.
  • In use the TLB is initially accessed to determine whether the TLB contains the physical address corresponding to a linear address, identifying a desired memory location. If the linear address is found within the TLB, a “hit” is said to have occurred. The physical address is merely loaded out of the TLB. If the linear and physical addresses are not cached within the TLB, then a TLB “miss” is said to have occurred. In which case, a page miss handler is used to perform a page table walk to determine the physical address corresponding to the desired linear address.
  • TLBs allow some entries to be locked. Some performance critical translations may be locked into the TLB to ensure that the slower page table walk operation will not be triggered when one of those translations is needed. However, determining whether there was a place to lock a particular translation often involves a detailed knowledge of the TLB architecture and detailed tracking of the entries that were locked. The architecture of the TLB may limit the kinds of entries that may be locked into it.
  • Thus, there is a need for better ways to lock entries in translation lookaside buffers.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram of one embodiment of the present invention; and
  • FIG. 2 is a flow chart for the embodiment shown in FIG. 1 in accordance with one embodiment of the present invention.
    • DETAILED DESCRIPTION
  • A computer system, shown in FIG. 1, includes a processor 105 coupled to a processor bus 135. The processor 105 may be a general purpose microprocessor, a complex instruction set computer, a reduced instruction set computer, a very long instruction word, or a hybrid architecture, to mention a few examples. In one embodiment, the processor 105 is an out-of-order processor capable of performing operations either out of order or speculatively. However, the present invention is applicable to any type of processor, including out-of-order and in-order processors.
  • Also coupled to the processor bus 135 is a memory controller hub (MCH) 140. The MCH 140 includes a memory controller 145 and an input/output (I/O) controller 150. In the illustrated embodiment, a main memory 155 is coupled to the processor bus 135 through the MCH 140. The processor 105 generates instructions (also referred to herein as micro-operations or “micro-ops”), such as memory loads, stores, and pre-fetches. The micro-ops are, in general, in a sequence that may differ from the sequence in which the instructions appear within a computer program. Micro-ops which involve memory accesses, such as memory loads, stores, and pre-fetches, are executed by a memory management unit (MMU) 110.
  • The MMU 110 includes, among other things, a cache unit 115, a page miss handler (PMH) 120, a software managed translation lookaside buffer 125, a hardware managed translation lookaside buffer 130 with a page table walk logic 165, the buffers 125, 130 coupled to a central processing unit (CPU) bus 175 by a multiplexer 170. The cache unit 115 may comprise a first level (L0) cache memory and a second level (L1) cache memory. The L0 and L1 cache memories may be integrated into a single device. Alternatively, the L1 cache memory may be coupled to the processor 105 by a shared bus (not shown).
  • The main memory 155 and the cache unit 115 store sequences of instructions and data that are executed by the processor 105. In one embodiment, the main memory 155 includes a dynamic random access memory (DRAM); however, the main memory 155 may have other configurations as well.
  • Additional devices may also be coupled to the memory controller hub 140, such as multiple main memory devices or a wireless interface 185. The interface 185 may be a dipole antenna for example, to enable radio frequency communications. The memory controller 145 coordinates data transfer to and from the main memory 155 at the request of the processor 105 and/or I/O devices 160. Data and/or sequences of instructions, executed by the processor 105, may be retrieved from the main memory 155, the cache unit 115, or other storage devices. A computer system has been described in terms of a single processor; however, multiple processors may be coupled to the processor bus 135.
  • In operation, the TLB 125 maintains a mapping of address translations between linear addresses and corresponding physical addresses. When a memory access type micro-op is loaded into an execution pipeline, it is intercepted by TLB 125, which performs a lookup to determine whether its internal cache lines contain the physical address corresponding to the linear address of the micro-op. If the address translation is found therein, i.e., if a hit occurs, TLB 125 re-dispatches a micro-op, updated to include the physical address. If a miss occurs, TLB 125 notifies the hardware managed translation lookaside buffer 130. If a hit occurs, the TLB 130 re-dispatches a micro-op, updated to include the physical address. If a miss occurs, the TLB 130 notifies the PMH 120 that a page walk must be performed to determine the physical address corresponding to the linear address of the micro-op. The page table walk may be performed by hardware, microcode, or other types of software.
  • Initially, a micro-op containing, among other things, information relating to the type of instruction and a sequence number is generated and loaded in a pipeline. Although the processor 105 generates a wide variety of micro-ops, only memory access micro-ops, such as pre-fetch, load, and stored, are handled here.
  • In one embodiment, software 220, executed by the processor 105 and stored, for example, within the MMU 110, begins as shown in FIG. 2, by checking both TLBs 125 and 130 for a translation (block 202). If the translation is in TLB 125 as determined in diamond 204, the translation is returned from TLB 125 as indicated a block 214.
  • Otherwise, a check at diamond 206 determines whether the translation is in TLB 130. If so, the translation is returned from TLB 130 as indicated in block 208. If the translation is not found in either TLB, the translation must be obtained from a page table walk logic as indicated in block 210. The translation is then put in the TLB 130, as indicated in block 212, and returned from TLB 130 as indicated in block 208.
  • The sequence of steps shown in FIG. 2 may also be implemented by hardware or microcode.
  • TLB 130 is managed primarily by hardware, using any number of known hardware-resident algorithms to decide which translations to put, replace, or invalidate within itself. Software commands to manage TLB 130 may also exist, but may not provide the ability to lock entries into TLB 130 in some embodiments.
  • TLB 125 is managed entirely via software commands that add and remove entries. TLB 125 can have translations locked into it. The software managed TLB 125 may not use page table walk logic 165. The page table walk logic is only handled by the TLB 130.
  • In one implementation, TLB 130 may be a 128-entry, 4-way set associative cache. TLB 125 may be an 8-entry, fully-associative cache in one embodiment of the present invention. The TLBs 125 and 130 may also handle different ranges of page sizes.
  • When a request for translation is passed to the TLBs 125 and 130, both TLBs may be consulted in parallel or sequentially. TLB 125, the software managed TLB, takes precedence in one embodiment. If the requested translation is not found in either TLB, then the hardware managed TLB 130 sends a request to the page table walk logic 165, caches the result according to its hardware resident replacement policies, and returns the translation to the requester. With a processor 105, having elevated security modes, managing the software managed TLB 125 may be restricted to that mode, while less privileged modes may be allowed to manage the hardware managed TLB 130.
  • In some embodiments of the present invention, the complexity inherent in locking translations in hardware managed TLBs may be avoided. Determining whether there was a place to lock a particular translation in a hardware managed TLB often involves detailed knowledge of the TLB architecture and detailed tracking of the entries that were locked. The architecture of hardware managed TLBs may also limit the kind of entries that can be locked into hardware managed TLBS. For example, only 4-kilobyte pages may be locked in some cases.
  • In some embodiments of the present invention, the hardware complexity issues may be lessened by using two translation lookaside buffers, coupled together by a simple mechanism. Thus, the software's job of locking translations may be made simpler, in some embodiments, because it has a more flexible translation lookaside buffer to manage without having to be concerned about interaction with the hardware managed translation lookaside buffer.
  • While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (23)

1. A method comprising:
providing two translation lookaside buffers for one microprocessor.
2. The method of claim 1 including providing a software and a hardware managed translation lookaside buffer for one microprocessor.
3. The method of claim 2 including providing a page table walk logic handled by said hardware managed translation lookaside buffer.
4. The method of claim 3 wherein, when a request for a translation from a linear to physical address is received, checking the software managed translation lookaside buffer to determine whether or not the translation is resident therein before checking said hardware managed translation lookaside buffer.
5. The method of claim 4 including checking said hardware managed translation lookaside buffer for said translation if said translation is not in said software managed translation lookaside buffer.
6. The method of claim 5 including, if said translation is not in said hardware managed translation lookaside buffer, obtaining the translation from a page table walk logic.
7. The method of claim 6 including returning the translation from the page table walk logic to said hardware managed translation lookaside buffer.
8. The method of claim 2 including locking translations in said software managed translation lookaside buffer.
9. The method of claim 2 including managing the software managed translation lookaside buffer in a restricted mode.
10. An article storing instructions that, if executed, enable a processor-based system to:
search in a software managed translation lookaside buffer for a translation from a linear to a physical address and, if the translation is not resident in said software managed translation lookaside buffer, look for said translation in a hardware managed translation lookaside buffer.
11. The article of claim 10 further storing instructions that, if executed, enable a processor-based system to obtain translations from a table walk logic exclusively via a hardware managed translation lookaside buffer instead of said software managed translation lookaside buffer.
12. The article of claim 10 further storing instructions that, if executed, enable a processor-based system to lock translations in said software managed translation lookaside buffer.
13. The article of claim 10 further storing instructions that, if executed, enable a processor-based system to manage the software managed translation lookaside buffer in a restricted mode.
14. The article of claim 10 further storing instructions that, if executed, enable a processor-based system to return a translation from a page table walk logic to said hardware managed translation lookaside buffer.
15. A system comprising:
a processor comprising a pair of translation lookaside buffers, only one of said buffers having page table walk logic; and
a wireless interface coupled to said processor.
16. The system of claim 15 wherein said wireless interface includes a dipole antenna.
17. The system of claim 15 wherein one of said buffers is a software managed translation lookaside buffer and the other one is a hardware managed translation lookaside buffer that is coupled to a page table walk logic.
18. The system of claim 17 wherein said software managed translation lookaside buffer is consulted first and only if a translation is not in said software managed translation lookaside buffer is said hardware managed translation lookaside buffer checked for the translation.
19. The system of claim 18 including a page table walk logic coupled exclusively to said hardware managed translation lookaside buffer.
20. The system of claim 19 wherein the software managed translation lookaside buffer to determine whether or not the translation is resident therein before said hardware managed translation lookaside buffer is checked for said translation.
21. The system of claim 20 wherein said page table walk logic to return a translation from the page table walk logic to said hardware managed translation lookaside buffer.
22. The system of claim 17, said processor to lock translations exclusively in said software managed translation lookaside buffer.
23. The system of claim 17 wherein said software managed translation lookaside buffer is managed in a restricted mode.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080189232A1 (en) * 2007-02-02 2008-08-07 Veoh Networks, Inc. Indicator-based recommendation system
US20090313227A1 (en) * 2008-06-14 2009-12-17 Veoh Networks, Inc. Searching Using Patterns of Usage
EP2159707A1 (en) * 2007-06-20 2010-03-03 Fujitsu Limited Arithmetic processing unit, entry control program, and entry control method
US20150095611A1 (en) * 2013-10-01 2015-04-02 Synopsys, Inc. Method and processor for reducing code and latency of tlb maintenance operations in a configurable processor
US20150199279A1 (en) * 2014-01-14 2015-07-16 Qualcomm Incorporated Method and system for method for tracking transactions associated with a system memory management unit of a portable computing device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9158696B2 (en) 2011-12-29 2015-10-13 Intel Corporation Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses
US9645934B2 (en) * 2013-09-13 2017-05-09 Samsung Electronics Co., Ltd. System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US5392410A (en) * 1992-04-30 1995-02-21 International Business Machines Corporation History table for prediction of virtual address translation for cache access
US5412787A (en) * 1990-11-21 1995-05-02 Hewlett-Packard Company Two-level TLB having the second level TLB implemented in cache tag RAMs
US5479627A (en) * 1993-09-08 1995-12-26 Sun Microsystems, Inc. Virtual address to physical address translation cache that supports multiple page sizes
US5963984A (en) * 1994-11-08 1999-10-05 National Semiconductor Corporation Address translation unit employing programmable page size
US6418522B1 (en) * 1999-02-13 2002-07-09 International Business Machines Corporation Translation lookaside buffer for virtual memory systems
US20040024986A1 (en) * 2002-08-02 2004-02-05 Devereux Ian Victor Entry lockdown within a translation lookaside buffer mechanism
US20040039893A1 (en) * 1999-12-17 2004-02-26 Lyon Terry L. Parallel distributed function translation lookaside buffer
US6760909B1 (en) * 1996-04-29 2004-07-06 Microsoft Corporation Virtual memory system and methods
US20040194076A1 (en) * 2003-03-25 2004-09-30 Comp Lynn A. Combining compilation and instruction set translation
US20040221090A1 (en) * 2003-04-30 2004-11-04 Fujitsu Limited Microprocessor
US20050050277A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. MicroTLB and micro TAG for reducing power in a processor
US20050081020A1 (en) * 2003-10-08 2005-04-14 Stmicroelectronics S.A. Multicontext processor architecture
US7073173B1 (en) * 2000-12-04 2006-07-04 Microsoft Corporation Code and thread differential addressing via multiplex page maps
US20060271759A1 (en) * 2005-05-27 2006-11-30 Moyer William C Translation information retrieval
US20060271760A1 (en) * 2005-05-31 2006-11-30 Stmicroelectronics Sa Translation look-aside buffer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463750A (en) * 1993-11-02 1995-10-31 Intergraph Corporation Method and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLB's
US6775747B2 (en) * 2002-01-03 2004-08-10 Intel Corporation System and method for performing page table walks on speculative software prefetch operations

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US5412787A (en) * 1990-11-21 1995-05-02 Hewlett-Packard Company Two-level TLB having the second level TLB implemented in cache tag RAMs
US5392410A (en) * 1992-04-30 1995-02-21 International Business Machines Corporation History table for prediction of virtual address translation for cache access
US5479627A (en) * 1993-09-08 1995-12-26 Sun Microsystems, Inc. Virtual address to physical address translation cache that supports multiple page sizes
US5963984A (en) * 1994-11-08 1999-10-05 National Semiconductor Corporation Address translation unit employing programmable page size
US6760909B1 (en) * 1996-04-29 2004-07-06 Microsoft Corporation Virtual memory system and methods
US6418522B1 (en) * 1999-02-13 2002-07-09 International Business Machines Corporation Translation lookaside buffer for virtual memory systems
US6874077B2 (en) * 1999-12-17 2005-03-29 Hewlett-Packard Development Company, L.P. Parallel distributed function translation lookaside buffer
US20040039893A1 (en) * 1999-12-17 2004-02-26 Lyon Terry L. Parallel distributed function translation lookaside buffer
US7073173B1 (en) * 2000-12-04 2006-07-04 Microsoft Corporation Code and thread differential addressing via multiplex page maps
US6941442B2 (en) * 2002-08-02 2005-09-06 Arm Limited Entry lockdown within a translation lookaside buffer mechanism
US20040024986A1 (en) * 2002-08-02 2004-02-05 Devereux Ian Victor Entry lockdown within a translation lookaside buffer mechanism
US20040194076A1 (en) * 2003-03-25 2004-09-30 Comp Lynn A. Combining compilation and instruction set translation
US20040221090A1 (en) * 2003-04-30 2004-11-04 Fujitsu Limited Microprocessor
US20050050277A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. MicroTLB and micro TAG for reducing power in a processor
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20050081020A1 (en) * 2003-10-08 2005-04-14 Stmicroelectronics S.A. Multicontext processor architecture
US20060271759A1 (en) * 2005-05-27 2006-11-30 Moyer William C Translation information retrieval
US20060271760A1 (en) * 2005-05-31 2006-11-30 Stmicroelectronics Sa Translation look-aside buffer

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080189232A1 (en) * 2007-02-02 2008-08-07 Veoh Networks, Inc. Indicator-based recommendation system
US8156059B2 (en) 2007-02-02 2012-04-10 Dunning Ted E Indicator-based recommendation system
EP2159707A1 (en) * 2007-06-20 2010-03-03 Fujitsu Limited Arithmetic processing unit, entry control program, and entry control method
US20100106938A1 (en) * 2007-06-20 2010-04-29 Fujitsu Limited Arithmetic processing unit and entry control method
EP2159707A4 (en) * 2007-06-20 2010-11-24 Fujitsu Ltd Arithmetic processing unit, entry control program, and entry control method
US8688952B2 (en) 2007-06-20 2014-04-01 Fujitsu Limited Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB
US20090313227A1 (en) * 2008-06-14 2009-12-17 Veoh Networks, Inc. Searching Using Patterns of Usage
WO2009152370A3 (en) * 2008-06-14 2010-03-25 Veoh Networks, Inc. Searching using patterns of usage
US20150095611A1 (en) * 2013-10-01 2015-04-02 Synopsys, Inc. Method and processor for reducing code and latency of tlb maintenance operations in a configurable processor
US9507729B2 (en) * 2013-10-01 2016-11-29 Synopsys, Inc. Method and processor for reducing code and latency of TLB maintenance operations in a configurable processor
US20150199279A1 (en) * 2014-01-14 2015-07-16 Qualcomm Incorporated Method and system for method for tracking transactions associated with a system memory management unit of a portable computing device

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