EP0766213A1 - Circuit for securing electronic components - Google Patents

Circuit for securing electronic components Download PDF

Info

Publication number
EP0766213A1
EP0766213A1 EP96114000A EP96114000A EP0766213A1 EP 0766213 A1 EP0766213 A1 EP 0766213A1 EP 96114000 A EP96114000 A EP 96114000A EP 96114000 A EP96114000 A EP 96114000A EP 0766213 A1 EP0766213 A1 EP 0766213A1
Authority
EP
European Patent Office
Prior art keywords
voltage
circuit
monitoring
capacitor
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96114000A
Other languages
German (de)
French (fr)
Other versions
EP0766213B1 (en
Inventor
Robert Depta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Technology Solutions GmbH
Original Assignee
Wincor Nixdorf International GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wincor Nixdorf International GmbH filed Critical Wincor Nixdorf International GmbH
Publication of EP0766213A1 publication Critical patent/EP0766213A1/en
Application granted granted Critical
Publication of EP0766213B1 publication Critical patent/EP0766213B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B13/00Burglar, theft or intruder alarms
    • G08B13/02Mechanical actuation
    • G08B13/12Mechanical actuation by the breaking or disturbance of stretched cords or wires
    • G08B13/126Mechanical actuation by the breaking or disturbance of stretched cords or wires for a housing, e.g. a box, a safe, or a room
    • G08B13/128Mechanical actuation by the breaking or disturbance of stretched cords or wires for a housing, e.g. a box, a safe, or a room the housing being an electronic circuit unit, e.g. memory or CPU chip

Definitions

  • the invention relates to a circuit arrangement for securing electronic components in devices with circuits and / or data to be kept secret, according to the preamble of claim 1.
  • the object of the invention is a further improvement of such a monitoring circuit, in which, in addition to short circuits and interruptions in the protective conductor, partial short circuits on each protective conductor can be detected with low power consumption and high sensitivity.
  • the protective conductors are alternately monitored by two independent monitoring circuits, one of which operates in a conventional manner statically and detects short circuits and interruptions, while the other works dynamically by applying a periodically recurring voltage pulse to the series connection of the protective conductors and the voltage drop at one point summarized protective conductors measured and compared with that of the previous measurement. If the voltage difference exceeds a predetermined value, the monitoring circuit then also triggers the necessary switching functions.
  • FIG. 1 shows in dashed lines a device which can be switched on to a supply voltage U via the switch ON, with the electronic parts DEV to be secured and with several Detector units existing monitoring device SENS.
  • This monitoring device is powered when the switch ON is closed by the supply voltage U in conjunction with a diode D U and a capacitor C, to which a battery BAT is connected in parallel with a diode D BAT , so that the battery BAT takes over the supply when the switch ON is open.
  • the monitoring device SENS consists of several detectors, namely DX for radiation monitoring, DU for monitoring the upper voltage limit of the supply voltage V C , DT / U for monitoring the permissible temperature limits and the lower voltage limit of V C and DM for monitoring the protective conductor.
  • the detector unit DM is also coupled to an oscillator OS as a clock generator, which is monitored by a further detector unit D-OS.
  • the oscillator OS alternately activates the two monitoring circuits coupled to the protective conductors according to the invention.
  • the detector unit DT / U is activated by it over a frequency divider FT at larger time intervals, since temperature changes and a drop in the battery voltage occur only slowly.
  • the radiation monitoring and the monitoring of the upper voltage limit of the oscillator by the detectors DX, DU o and D-OSZ is permanently effective. In this way, the power consumption of the monitoring device is already reduced to the bare minimum, further savings being possible by appropriately designing the monitoring circuits for the individual detector units.
  • FIG. 2 shows the circuit arrangement for the detector unit DM for monitoring the protective conductors M1 and M2, which are not shown in FIG. 1 and which are arranged in a known manner parallel to one another in a meandering manner in the device.
  • the circuit arrangement is controlled by an asymmetrical oscillator clock OS with the pulses T1 and the intermediate and much longer pulse pauses T2.
  • the pulse duration is, for example, 80 ⁇ s with a pulse interval of 100ms, the dynamically operating monitoring circuit being activated during pulses T1 and the statically operating monitoring circuit being activated during pulse pause T2.
  • Field-effect transistors of the P-channel and N-channel enhancement types are used as switching elements V ... and S ..., and the supply voltage V C has a positive potential with respect to the counter potential GND.
  • the input circuit consists of two current branches arranged between the two potentials GND and V C , one of which in series with the switch V1 and the resistor R1 inverts the supplied oscillator clock OSZ and supplies the voltage U INV , while the second with the switches V2 and V3 and the Zener diode ZD in series inverted the inverted oscillator voltage U INV again and simultaneously stabilized, so that a stabilized control voltage U ST corresponding to the pulse / pause ratio of the oscillator voltage OSZ is obtained at the electrode S of the switch V3.
  • the switches S1 and S2 are controlled with the oscillator voltage OSZ at the gate electrodes, so that the switch S1 is used to produce a series connection of the two protective conductors M1 and M2, which is connected to the voltage U via the diode D4 during the pulse duration T1 ST is briefly applied.
  • the series circuit consisting of the resistor R6 and the capacitor C1 and, in parallel, the series circuit consisting of the resistor R7 and the capacitor R3 are connected in parallel with the series circuit consisting of the protective conductor M2 and the switching path of the switch S1, so that both capacitors C1 and C3 are charged according to the voltage drop at connection point A of the protective conductor M1.
  • the capacitor C1 resulting measuring voltage U M compared with the reference voltage U REF across the capacitor C2. If the voltage comparison reveals a difference in one direction or the other, the value of which is greater than the permissible limit value defined by the voltage U DEL , an alarm signal AL1 is triggered.
  • the voltage U DEL specifying the limit value is generated by a resistor R3, R4 and R5 existing and also tapped by the stabilized voltage U ST voltage divider.
  • the voltage comparison is carried out by a component SHC which has two comparators with a strobe input which operate according to the sample and hold principle and which provide the alarm signal AL1 if the voltage difference is too great via the diodes D A or D B.
  • the oscillator OS can also be integrated into this module, for example with the LTC 1040 module from the company LINEAR TECHNOLOGY.
  • the reference voltage U REF at the capacitor C2 is only built up after a time delay after the monitoring circuit has been switched on for the first time.
  • the switches V4 and V5 serve as control elements for this, and are each converted from the inverted voltage U INV to the conductive state during the pulse pause T2, so that a charge equalization path is established for the two capacitors C2 and C3 via one of the two switches V4 and V5 becomes.
  • These two capacitors C2 and C3 expediently have a substantially larger capacitance than the capacitor C1, so that an adaptation is possible despite the generation of an alarm signal AL1.
  • the capacitances of the capacitors C2 and C3, in conjunction with the size of the limit voltage U DEL, also determine the period of time until the signal AL1 is omitted after the monitoring circuit has come into effect in an alarm-free state. From this point on, voltage changes caused by interruptions or short circuits due to exceeding the limit voltage U DEL are then correctly recognized.
  • the monitoring circuit described is largely independent of the manufacturing tolerances of the protective conductors and of aging processes or temperature influences, since voltage changes caused by this only take place slowly and thus take place within the limit value range.
  • a capacitor CB is also charged via a diode D1 in parallel to the voltage divider R3 / R4 / R5 by the effective stabilized voltage U ST , which then during the subsequent pulse pause T2 via the diode D2
  • Protective conductor M1 is supplied with voltage in the static monitoring circuit.
  • the protective conductor M2 is then at the potential GND because of the very high resistance R12.
  • Controlling switches in the static monitoring circuit are also switches V7, V6 and V8.
  • the circuit is designed so that in the alarm-free state, the switch V6 as a P-channel type is in the blocked state and the switch V8 as an N-channel type is in the conductive state.
  • the electrode S of V8 is always at a lower potential than the electrode G.
  • the switch V7 as an N-channel type, which is then controlled by the stabilized voltage U ST and via the low-resistance resistor R11 the potential GND at the electrode S of V8 takes effect, while the stabilized one positive voltage U ST is applied to electrode G via diode D4.
  • the series connection of protective conductor M2 and diode D7 is effective instead of the switch path of V7, while electrode G of V8 is acted upon by diode D2 with the voltage across capacitor CB.
  • the switch V6 on the other hand, is blocked as long as the potential at its electrode G is not sufficiently negative with respect to the electrode S to cause the transition to the conductive state effect. This is ensured by the diodes D4 and D6 during the pulses T1, and in the pulse pauses T2 the series circuit D2, M1 and R10 fed by the capacitor CB causes this in the discharge circuit of the capacitor CB, with the resistances being appropriately dimensioned in accordance with R9 >> R10.
  • the triggering of an alarm AL2 at the connection point B of the resistors R13 and R14 has the prerequisite that the potential swing is correspondingly large.
  • the value of the resistors R12 and R13 is therefore in the range of a few MOhm compared to the resistors R11, R14 and R15 in the KOhm range.
  • the upper right part of FIG. 2 also shows the detector D-OS for monitoring the oscillator function, which is controlled by the inverted voltage U INV .
  • the capacitor C5 is very high high-resistance resistor R16 is charged very slowly, so that the capacitor voltage effective at electrode G of V9 does not control switch V9 in a conductive manner. The subsequent switch V10 of the P-channel type is therefore also blocked. If the oscillator OSZ is active, the capacitor C5 is temporarily discharged via the diode D13 during the pulses T1.
  • FIG. 3 A useful addition to the arrangement described with reference to FIG. 2 is the circuit of FIG. 3 for monitoring the upper voltage limit of the supply voltage V C to protect the existing detectors with only very low power consumption in the non-activated state.
  • This monitoring circuit consists of a field-effect transistor of the P-channel type, to the electrode G of which a reference voltage V REF is applied, while the electrode S is connected to the supply voltage V C via a Zener diode ZD1 and a silicon diode D11. Both electrodes G and S are also connected in the manner shown via a Schottkky diode D12 for stabilization, which keeps transistor V blocked even with small fluctuations in the reference voltage.
  • the transistor V becomes conductive and supplies the alarm signal AL at the electrode D.
  • FIG. 4 shows the only periodically activated detector DT / U U for monitoring the specified temperature limits and the lower voltage limit of the supply voltage V C.
  • the activation This monitoring circuit is carried out, for example, by the oscillator clock OSZ from FIG. 2, which acts via a frequency divider FT on a module SHC1 consisting of two comparators with strobe input STR, as it already does in connection with the dynamically operating monitoring circuit for the protective conductor M ... of FIG. 2 was mentioned.
  • the activation takes place, for example, at intervals of seconds, each time generating a positive voltage pulse VPP for supplying the monitoring circuit from the SHC1 module.
  • This voltage pulse works on a Zener diode ZD2, to which several voltage dividers are connected in parallel.
  • the voltage divider consisting of the resistors R21 and R22 then supplies a measuring voltage at its center tap which is added by the comparator A to the Zener voltage and thus defines the lower permissible voltage limit. If the supply voltage V C falls below this voltage limit, the comparator A triggers the alarm signal AL via the downstream diode of the Schottky double diode SDD3.
  • Two further voltage dividers are provided for temperature limit monitoring, namely one with a thermistor HL and a resistor R25 and one with a PTC thermistor KL and a resistor R26.
  • the center taps of these two voltage dividers are each led to a common measuring voltage output via a diode of a Schottky diode pair SDD2.
  • the voltage drop across the thermistor HL becomes greater than that at the PTC thermistor KL
  • the voltage drop across the PTC thermistor KL becomes greater than that at the thermistor HL.
  • the desired temperature limits can be set very precisely by the resistors R25 and R26.
  • the resulting voltage at the center output of the Schottky diode pair SDD2 is then compared by the comparator B of the component SHC1 with a reference voltage, which at the center tap of a further voltage divider consisting of the resistors R23 and R24 via one of the Diodes of a Schottky diode pair SDD1 is supplied.
  • the use of identical diode sections increases the measuring accuracy of the circuit.
  • the same load resistors R L and filter capacitors C L are also advantageously connected in parallel to the inputs of the comparator B. If the voltage of the diode pair SDD2 exceeds that of the diode pair SDD1, then the alarm signal AL is also triggered via the associated diode of the diode pair SDD3.

Abstract

The circuit protects modules using electrical protection lines (M1,M2). The lines are statically monitored for detecting line breakage and short-circuits and dynamically monitored for detecting partial short-circuits via a separate monitoring circuit. The static and dynamic monitoring circuits (CB,V6,V7,V8 ; S1,S2,V4,V5,SHC) are operated in alternation. Switching between the two protection circuits is controlled by a pulse control (OSZ). The dynamic monitoring circuit is switched to only for the duration of the measurement, while the static circuit operates during the remaining time period. A detected line breakage or short-circuit is used to activate an alarm (AL1) and/or initiate a protection function.

Description

Die Erfindung betrifft eine Schaltungsanordnung zur Sicherung elektronischer Bauteile in Geräten mit geheim zu haltenden Schaltungen und/oder Daten gemäß dem Oberbegriff des Anspruches 1.The invention relates to a circuit arrangement for securing electronic components in devices with circuits and / or data to be kept secret, according to the preamble of claim 1.

In vielen Geräten, die beispielsweise im Bankwesen oder sonstigen sicherheitsrelevanten Bereichen Verwendung finden, können Daten, z.B. Chiffrierschlüssel, gespeichert oder Algorithmen, z.B. zum Verschlüsseln, durch Schaltungsteile realisiert sein, die geheim zu halten und daher zu schützen sind. Es ist bereits eine Reihe von Lösungen zum Schutz solcher Geräte bekannt, die sich auf die unterschiedlichsten Arten des Eindringens in diese Geräte beziehen, man siehe z.B. EP-0 417 447-A2.In many devices that are used for example in banking or other security-related areas, data, e.g. Encryption key, stored or algorithms, e.g. for encryption, can be realized by circuit parts that are kept secret and are therefore to be protected. A number of solutions for protecting such devices are already known, which relate to the most diverse types of intrusion into these devices, see e.g. EP-0 417 447-A2.

Zu diesen bekannten Lösungen gehört auch die Überwachung durch Umhüllung mit Schutzleitern, beispielsweise in Form von parallel verlaufenden und mäanderförmig geführten elektrisch leitenden Drähten, die auf Unterbrechung oder Kurzschluß überwacht werden. Da die Überwachung unabhängig von einer äußeren Stromzufuhr möglich sein muß, werden die Überwachungseinrichtungen von einer Batterie gespeist. Das erfordert Überwachungseinrichtungen mit geringem Stromverbrauch bei hoher Ansprechempfindlichkeit. Eine derartige Schaltung ist z.B. aus EP 0 529 116 A1 bekannt.These known solutions also include monitoring by covering with protective conductors, for example in the form of parallel and meandering electrically conductive wires, which are monitored for interruptions or short circuits. Since the monitoring must be possible independently of an external power supply, the monitoring devices are powered by a battery. This requires monitoring devices with low power consumption and high sensitivity. Such a circuit is e.g. known from EP 0 529 116 A1.

Aufgabe der Erfindung ist eine weitere Verbesserung einer solchen Überwachungsschaltung, in dem neben Kurzschlüssen und Unterbrechungen der Schutzleiter auch partielle Kurzschlüsse an jedem Schutzleiter bei geringem Stromverbrauch und hoher Empfindlichkeit erkannt werden können.The object of the invention is a further improvement of such a monitoring circuit, in which, in addition to short circuits and interruptions in the protective conductor, partial short circuits on each protective conductor can be detected with low power consumption and high sensitivity.

Diese Aufgabe wird durch die kennzeichnenden Merkmale des Anspruches 1 gelöst.This object is achieved by the characterizing features of claim 1.

Danach werden die Schutzleiter abwechselnd von zwei unabhängigen Überwachungsschaltkreisen überwacht, von denen der eine in herkömmlicher Weise statisch arbeitet und Kurzschlüsse und Unterbrechungen erfaßt, während der andere dynamisch arbeitet, indem die Reihenschaltung der Schutzleiter mit einem periodisch wiederkehrenden Spannungsimpuls beaufschlagt und der Spannungsabfall an einem Punkt der zusammengefaßten Schutzleitern gemessen und mit dem der vorhergehenden Messung verglichen wird. Bei einer einen vorgegebenen Wert überschreitenden Spannungsdifferenz löst die Überwachungsschaltung dann ebenfalls die notwendigen Schaltfunktionen aus.Thereafter, the protective conductors are alternately monitored by two independent monitoring circuits, one of which operates in a conventional manner statically and detects short circuits and interruptions, while the other works dynamically by applying a periodically recurring voltage pulse to the series connection of the protective conductors and the voltage drop at one point summarized protective conductors measured and compared with that of the previous measurement. If the voltage difference exceeds a predetermined value, the monitoring circuit then also triggers the necessary switching functions.

Weiterbildungen der Erfindung ergeben sich aus den weiteren Ansprüchen.Further developments of the invention result from the further claims.

Einzelheiten der Erfindung seien nachfolgend an Hand eines in der Zeichnung dargestellten Ausführungsbeispieles näher erläutert. Im einzelnen zeigen

FIG 1
ein Übersichtsschaltbild eines zu überwachenden Gerätes mit einer aus mehreren Detektoreinheiten bestehenden Überwachungseinrichtung,
FIG 2
eine Schaltungsanordnung für die Detektoreinheit zur Überwachung der Schutzleiter gemäß der Erfindung,
FIG 3 und FIG 4
Schaltungsanordnungen für die Detektoreinheiten zur Überwachung der oberen Spannungsgrenze bzw. der unteren Spannungsgrenze und der zulässigen Temperaturgrenzen.
Details of the invention will be explained below with reference to an embodiment shown in the drawing. Show in detail
FIG. 1
1 shows an overview circuit diagram of a device to be monitored with a monitoring device consisting of several detector units,
FIG 2
a circuit arrangement for the detector unit for monitoring the protective conductor according to the invention,
3 and 4
Circuit arrangements for the detector units for monitoring the upper voltage limit or the lower voltage limit and the permissible temperature limits.

FIG 1 zeigt gestrichelt umrandet ein an eine Versorgungsspannung U über den Schalter EIN einschaltbares Gerät mit den zu sichernden elektronischen Teilen DEV und der aus mehreren Detektoreinheiten bestehenden Überwachungseinrichtung SENS. Die Speisung dieser Überwachungseinrichtung erfolgt bei geschlossenem Schalter EIN durch die Versorgungsspannung U in Verbindung mit einer Diode DU und einem Kondensator C, dem eine Batterie BAT mit einer Diode DBAT parallelgeschaltet ist, so daß bei offenem Schalter EIN die Batterie BAT die Speisung übernimmt.1 shows in dashed lines a device which can be switched on to a supply voltage U via the switch ON, with the electronic parts DEV to be secured and with several Detector units existing monitoring device SENS. This monitoring device is powered when the switch ON is closed by the supply voltage U in conjunction with a diode D U and a capacitor C, to which a battery BAT is connected in parallel with a diode D BAT , so that the battery BAT takes over the supply when the switch ON is open.

Die Überwachungseinrichtung SENS besteht aus mehreren Detektoren, nämlich D-X zur Bestrahlungsüberwachung, D-U zur Überwachung der oberen Spannungsgrenze der Speisespannung VC, D-T/U zur Überwachung der zulässigen Temperaturgrenzen und der unteren Spannungsgrenze von VC und D-M zur Überwachung der Schutzleiter. Die Detektoreinheit D-M ist desweiteren mit einem Oszillator OS als Taktgeber gekoppelt, der durch eine weitere Detektoreinheit D-OS überwacht wird.The monitoring device SENS consists of several detectors, namely DX for radiation monitoring, DU for monitoring the upper voltage limit of the supply voltage V C , DT / U for monitoring the permissible temperature limits and the lower voltage limit of V C and DM for monitoring the protective conductor. The detector unit DM is also coupled to an oscillator OS as a clock generator, which is monitored by a further detector unit D-OS.

Der Oszillator OS schaltet abwechselnd die mit den Schutzleitern gemäß der Erfindung gekoppelten beiden Überwachungsschaltkreise wirksam. Außerdem wird durch ihn über einen Frequenzteiler FT die Detektoreinheit D-T/U in größeren Zeitabständen wirksam geschaltet, da Temperaturänderungen und ein Absinken der Batteriespannung nur langsam erfolgen. Die Strahlungsüberwachung und die Überwachung der oberen Spannungsgrenze des Oszillators durch die Detektoren D-X, D-Uo und D-OSZ, ist dagegen dauernd wirksam. Auf diese Weise wird der Stromverbrauch der Überwachungseinrichtung bereits auf das Notwendigste reduziert, wobei weitere Einsparungen durch entsprechende Ausbildung der Überwachungsschaltkreise für die einzelnen Detektoreinheiten möglich sind.The oscillator OS alternately activates the two monitoring circuits coupled to the protective conductors according to the invention. In addition, the detector unit DT / U is activated by it over a frequency divider FT at larger time intervals, since temperature changes and a drop in the battery voltage occur only slowly. The radiation monitoring and the monitoring of the upper voltage limit of the oscillator by the detectors DX, DU o and D-OSZ, however, is permanently effective. In this way, the power consumption of the monitoring device is already reduced to the bare minimum, further savings being possible by appropriately designing the monitoring circuits for the individual detector units.

FIG 2 zeigt die Schaltungsanordnung für die Detektoreinheit D-M zur Überwachung der Schutzleiter M1 und M2, die in FIG 1 nicht näher gezeigt sind und die in bekannter Weise parallel zueinander verlaufend mäanderförmig im Gerät angeordnet sind.2 shows the circuit arrangement for the detector unit DM for monitoring the protective conductors M1 and M2, which are not shown in FIG. 1 and which are arranged in a known manner parallel to one another in a meandering manner in the device.

Die Schaltungsanordnung wird von einem asymmetrischen Oszillatortakt OS mit den Impulsen T1 und den dazwischenliegenden und wesentlich längeren Impulspausen T2 gesteuert. Die Impulsdauer beträgt z.B. 80µs bei einem Impulsabstand von 100ms, wobei während der Impulse T1 der dynamisch arbeitende Überwachungsschaltkreis und während der Impulspause T2 der statisch arbeitende Überwachungsschaltkreis wirksam geschaltet wird. Als Schaltelemente V... und S... sind dabei Feldeffekttransistoren vom P-Kanal- und N-Kanal-Anreicherungstyp verwendet, und die Speisespannung VC weist ein gegenüber dem Gegenpotential GND positives Potential auf.The circuit arrangement is controlled by an asymmetrical oscillator clock OS with the pulses T1 and the intermediate and much longer pulse pauses T2. The pulse duration is, for example, 80µs with a pulse interval of 100ms, the dynamically operating monitoring circuit being activated during pulses T1 and the statically operating monitoring circuit being activated during pulse pause T2. Field-effect transistors of the P-channel and N-channel enhancement types are used as switching elements V ... and S ..., and the supply voltage V C has a positive potential with respect to the counter potential GND.

Die Eingangsschaltung besteht aus zwei zwischen den beiden Potentialen GND und VC angeordneten Stromzweigen, von denen der eine mit dem Schalter V1 und dem Widerstand R1 in Reihe den zugeführten Oszillatortakt OSZ invertiert und die Spannung UINV liefert, während der zweite mit den Schaltern V2 und V3 und der Zenerdiode ZD in Reihe die invertierte Oszillatorspannung UINV erneut invertiert und gleichzeitig stabilisiert, so daß an der Elektrode S des Schalters V3 eine dem Impuls/Pausenverhältnis der Oszillatorspannung OSZ entsprechende stabilisierte Steuerspannung UST erhalten wird.The input circuit consists of two current branches arranged between the two potentials GND and V C , one of which in series with the switch V1 and the resistor R1 inverts the supplied oscillator clock OSZ and supplies the voltage U INV , while the second with the switches V2 and V3 and the Zener diode ZD in series inverted the inverted oscillator voltage U INV again and simultaneously stabilized, so that a stabilized control voltage U ST corresponding to the pulse / pause ratio of the oscillator voltage OSZ is obtained at the electrode S of the switch V3.

Parallel dazu werden die Schalter S1 und S2 mit der Oszillatorspannung OSZ an den Gate-Elektroden leitend gesteuert, so daß mit dem Schalter S1 eine Reihenschaltung der beiden Schutzleiter M1 und M2 hergestellt wird, die während der Impulsdauer T1 über die Diode D4 mit der Spannung UST kurzzeitig beaufschlagt wird. Mit dem gleichzeitig leitenden Schalter S2 wird außerdem die aus dem Widerstand R6 und dem Kondensator C1 bestehende Reihenschaltung und parallel dazu die aus dem Widerstand R7 und dem Kondensator R3 bestehende Reihenschaltung zu der aus dem Schutzleiter M2 und der Schaltstrecke des Schalters S1 bestehenden Reihenschaltung parallel geschaltet, so daß beide Kondensatoren C1 und C3 entsprechend dem Spannungsabfall am Anschlußpunkt A des Schutzleiters M1 aufgeladen werden. Nachfolgend wird dann die sich am Kondensator C1 ergebende Meßspannung UM mit der Referenzspannung UREF am Kondensator C2 verglichen. Ergibt der Spannungsvergleich eine Differenz in der einen oder anderen Richtung, deren Wert größer als der durch die Spannung UDEL, festgelegte zulässige Grenzwert ist, dann wird ein Alarmsignal AL1 ausgelöst.Die den Grenzwert vorgebende Spannung UDEL wird von einem aus den Widerständen R3, R4 und R5 bestehenden und gleichfalls von der stabilisierten Spannung UST beaufschlagten Spannungsteiler abgegriffen.In parallel, the switches S1 and S2 are controlled with the oscillator voltage OSZ at the gate electrodes, so that the switch S1 is used to produce a series connection of the two protective conductors M1 and M2, which is connected to the voltage U via the diode D4 during the pulse duration T1 ST is briefly applied. With the simultaneously conductive switch S2, the series circuit consisting of the resistor R6 and the capacitor C1 and, in parallel, the series circuit consisting of the resistor R7 and the capacitor R3 are connected in parallel with the series circuit consisting of the protective conductor M2 and the switching path of the switch S1, so that both capacitors C1 and C3 are charged according to the voltage drop at connection point A of the protective conductor M1. Subsequently, then the capacitor C1 resulting measuring voltage U M compared with the reference voltage U REF across the capacitor C2. If the voltage comparison reveals a difference in one direction or the other, the value of which is greater than the permissible limit value defined by the voltage U DEL , an alarm signal AL1 is triggered. The voltage U DEL specifying the limit value is generated by a resistor R3, R4 and R5 existing and also tapped by the stabilized voltage U ST voltage divider.

Der Spannungsvergleich wird beim Ausführungsbeispiel von einem Baustein SHC ausgeführt, der zwei nach dem Sample & Hold-Prinzip arbeitende Komparatoren mit Strobeeingang aufweist, die bei zu großer Spannungsdifferenz über die Dioden DA bzw. DB das Alarmsignal AL1 liefern. In diesen Baustein kann auch zugleich der Oszillator OS integriert sein, wie beispielsweise beim Baustein LTC 1040 der Firma.LINEAR TECHNOLOGY.In the exemplary embodiment, the voltage comparison is carried out by a component SHC which has two comparators with a strobe input which operate according to the sample and hold principle and which provide the alarm signal AL1 if the voltage difference is too great via the diodes D A or D B. The oscillator OS can also be integrated into this module, for example with the LTC 1040 module from the company LINEAR TECHNOLOGY.

Die Referenzspannung UREF am Kondensator C2 wird nach dem erstmaligen Einschalten des Überwachungsschaltkreises erst mit einer zeitlichen Verzögerung aufgebaut. Als Steuerelemente dafür dienen die Schalter V4 und V5, die jeweils während der Impulspause T2 von der invertierten Spannung UINV in den leitenden Zustand überführt werden, so daß für die beiden Kondensatoren C2 und C3 ein Ladungsausgleichspfad über einen der beiden Schalter V4 bzw. V5 hergestellt wird. Diese beiden Kondensatoren C2 und C3 haben zweckmäßig eine wesentlich größere Kapazität als der Kondensator C1, so daß trotz der Erzeugung eines Alarmsignals AL1 eine Anpassung möglich ist. Auch bestimmen die Kapazitäten der Kondensatoren C2 und C3 in Verbindung mit der Größe der Grenzspannung UDEL die Zeitdauer, bis nach dem Wirksamschalten des Überwachungsschaltkreises bei alarmfreiem Zustand das Signal AL1 entfällt. Von diesem Zeitpunkt an werden dann durch Unterbrechungen oder Kurzschlüsse verursachte Spannungsänderungen wegen Überschreiten der Grenzspannung UDEL einwandfrei erkannt.The reference voltage U REF at the capacitor C2 is only built up after a time delay after the monitoring circuit has been switched on for the first time. The switches V4 and V5 serve as control elements for this, and are each converted from the inverted voltage U INV to the conductive state during the pulse pause T2, so that a charge equalization path is established for the two capacitors C2 and C3 via one of the two switches V4 and V5 becomes. These two capacitors C2 and C3 expediently have a substantially larger capacitance than the capacitor C1, so that an adaptation is possible despite the generation of an alarm signal AL1. The capacitances of the capacitors C2 and C3, in conjunction with the size of the limit voltage U DEL, also determine the period of time until the signal AL1 is omitted after the monitoring circuit has come into effect in an alarm-free state. From this point on, voltage changes caused by interruptions or short circuits due to exceeding the limit voltage U DEL are then correctly recognized.

Der beschriebene Überwachungsschaltkreis ist dabei von den Fertigungstoleranzen der Schutzleiter und von Alterungsprozessen oder Temperatureinflüssen weitgehend unabhängig, da dadurch bedingte Spannungsänderungen nur langsam erfolgen und sich damit innerhalb des Grenzwertbereiches vollziehen.The monitoring circuit described is largely independent of the manufacturing tolerances of the protective conductors and of aging processes or temperature influences, since voltage changes caused by this only take place slowly and thus take place within the limit value range.

Zeitgleich mit der Durchführung der dynamischen Überprüfung während der Impulse T1 wird außerdem ein Kondensator CB über eine Diode D1 parallel zum Spannungsteiler R3/R4/R5 durch die wirksame stabilisierte Spannung UST aufgeladen, der dann während der jeweils nachfolgenden Impulspause T2 über die Diode D2 den Schutzleiter M1 im statisch arbeitenden Überwachungsschaltkreis mit Spannung beaufschlagt. Der Schutzleiter M2 liegt dann wegen des sehr hochohmigen Widerstandes R12 auf dem Potential GND.Simultaneously with the execution of the dynamic check during the pulses T1, a capacitor CB is also charged via a diode D1 in parallel to the voltage divider R3 / R4 / R5 by the effective stabilized voltage U ST , which then during the subsequent pulse pause T2 via the diode D2 Protective conductor M1 is supplied with voltage in the static monitoring circuit. The protective conductor M2 is then at the potential GND because of the very high resistance R12.

Steuernde Schalter im statisch arbeitenden Überwachungsschaltkreis sind desweiteren die Schalter V7, V6 und V8. Der Schaltkreis ist dabei so gestaltet, daß im alarmfreien Zustand der Schalter V6 als P-Kanal-Typ sich im gesperrten und der Schalter V8 als N-Kanal-Typ sich im leitenden Zustand befindet. Letzteres setzt voraus, daß die Elektrode S von V8 immer auf niedrigerem Potential gegenüber der Elektrode G liegt. Während der Impulse T1 stellt dies der Schalter V7 als N-Kanal-Typ sicher, der dann von der stabilisierten Spannung UST leitend gesteuert wird und über den niederohmigen Widerstand R11 das Potential GND an der Elektrode S von V8 wirksam werden läßt, während die stabilisierte positive Spannung UST über die Diode D4 an der Elektrode G anliegt. Während der Impulspausen T2 ist dagegen die Reihenschaltung von Schutzleiter M2 und der Diode D7 anstelle der Schalterstrecke von V7 wirksam, während die Elektrode G von V8 über die Diode D2 mit der Spannung am Kondensator CB beaufschlagt wird.Controlling switches in the static monitoring circuit are also switches V7, V6 and V8. The circuit is designed so that in the alarm-free state, the switch V6 as a P-channel type is in the blocked state and the switch V8 as an N-channel type is in the conductive state. The latter assumes that the electrode S of V8 is always at a lower potential than the electrode G. During the pulses T1, this is ensured by the switch V7 as an N-channel type, which is then controlled by the stabilized voltage U ST and via the low-resistance resistor R11 the potential GND at the electrode S of V8 takes effect, while the stabilized one positive voltage U ST is applied to electrode G via diode D4. In contrast, during the pulse pauses T2, the series connection of protective conductor M2 and diode D7 is effective instead of the switch path of V7, while electrode G of V8 is acted upon by diode D2 with the voltage across capacitor CB.

Der Schalter V6 ist dagegen gesperrt, so lange das Potential an dessen Elektrode G nicht ausreichend negativ gegenüber der Elektrode S ist, um den Übergang in den leitenden Zustand zu bewirken. Während der Impulse T1 stellen das die Dioden D4 und D6 sicher, und in den Impulspausen T2 bewirkt das die vom Kondensator CB gespeiste Reihenschaltung D2, M1 und R10 im Entladestromkreis des Kondensators CB bei entsprechender Bemessung der Widerstände gemäß R9>>R10.The switch V6, on the other hand, is blocked as long as the potential at its electrode G is not sufficiently negative with respect to the electrode S to cause the transition to the conductive state effect. This is ensured by the diodes D4 and D6 during the pulses T1, and in the pulse pauses T2 the series circuit D2, M1 and R10 fed by the capacitor CB causes this in the discharge circuit of the capacitor CB, with the resistances being appropriately dimensioned in accordance with R9 >> R10.

Das Auslösen eines Alarms AL2 am Verbindungspunkt B der Widerstände R13 und R14 hat zur Voraussetzung, daß der Potentialhub entsprechend groß ist. Der Wert der Widerstände R12 und R13 liegt daher im Bereich von einigen MOhm im Vergleich zu den Widerständen R11, R14 und R15 im KOhm-Bereich.The triggering of an alarm AL2 at the connection point B of the resistors R13 and R14 has the prerequisite that the potential swing is correspondingly large. The value of the resistors R12 and R13 is therefore in the range of a few MOhm compared to the resistors R11, R14 and R15 in the KOhm range.

Wird der Schutzleiter M1 unterbrochen und damit die Reihenschaltung aus Diode D2, Schutzleiter M1 und Widerstand R10 unterbrochen, dann wird das Potential an der Elektrode G von V6 über den Widerstand R9 erheblich abgesenkt und damit V6 in den leitenden Zustand gesteuert, so daß das Potential der Elektrode D stark angehobenund dadurch über den Widerstand R14 das Alarmsignal AL2 ausgelöst wird.If the protective conductor M1 is interrupted and the series circuit of diode D2, protective conductor M1 and resistor R10 is interrupted, then the potential at the electrode G is significantly reduced by V6 via resistor R9 and thus V6 is controlled to the conductive state, so that the potential of the Electrode D is raised sharply and alarm signal AL2 is triggered via resistor R14.

Bei Unterbrechung des Schutzleiters M2 steigt das Potential an der Elektrode S von V8 über den Widerstand R12 so stark an, daß V8 gesperrt und über den Widerstand R13 das Alarmsignal AL2 ausgelöst wird.If the protective conductor M2 is interrupted, the potential at the electrode S of V8 increases so much via the resistor R12 that V8 is blocked and the alarm signal AL2 is triggered via the resistor R13.

Beim Kurzschluß zwischen beiden Schutzleitern M1 und M2 liegen entweder die Elektroden S und G von V8 auf annähernd gleichem Potential, so daß V8 gesperrt wird, oder aber über den Widerstand R10 wird das Potential an der Elektrode G von V6 gegenüber der Elektrode S so weit abgesenkt, daß dieser Schalter vom gesperrten in den leitenden Zustand übergeht. In beiden Fällen wird ebenfalls das Alarmsignal AL2 ausgelöst.In the event of a short circuit between the two protective conductors M1 and M2, either the electrodes S and G of V8 are at approximately the same potential, so that V8 is blocked, or else via the resistor R10 the potential at the electrode G of V6 is lowered as far as the electrode S. that this switch changes from the locked to the conductive state. In both cases, the alarm signal AL2 is also triggered.

Im rechten oberen Teil von FIG 2 ist auch der Detektor D-OS zur Überwachung der Oszillatorfunktion dargestellt, der von der invertierten Spannung UINV gesteuert wird. Während der Impulspausen T2 wird der Kondensator C5 über den sehr hochohmigen Widerstand R16 nur sehr langsam aufgeladen, so daß die an der Elektrode G von V9 wirksame Kondensatorspannung den Schalter V9 nicht leitend steuert. Der nachfolgende Schalter V10 vom P-Kanal-Typ ist daher ebenfalls gesperrt. Ist der Oszillator OSZ wirksam, dann erfolgt jeweils während der Impulse T1 eine zwischenzeitliche Entladung des Kondensators C5 über die Diode D13. Unterbleibt dagegen die periodische Entladung, dann führt die zunehmende Kondensatorspannung zum Leitendwerden des Schalters V9 und damit auch des Schalters V10, so daß durch den Spannungshub am Widerstand R13 das Alarmsignal AL3 wirksam wird. Alle drei Alarmsignale können in an sich bekannter Weise zu einem Signal AL zusammengefaßt werden.The upper right part of FIG. 2 also shows the detector D-OS for monitoring the oscillator function, which is controlled by the inverted voltage U INV . During the pulse pauses T2, the capacitor C5 is very high high-resistance resistor R16 is charged very slowly, so that the capacitor voltage effective at electrode G of V9 does not control switch V9 in a conductive manner. The subsequent switch V10 of the P-channel type is therefore also blocked. If the oscillator OSZ is active, the capacitor C5 is temporarily discharged via the diode D13 during the pulses T1. If, on the other hand, the periodic discharge does not occur, the increasing capacitor voltage leads to the switch V9 and thus also the switch V10 becoming conductive, so that the alarm signal AL3 becomes effective due to the voltage swing across the resistor R13. All three alarm signals can be combined into a signal AL in a manner known per se.

Eine zweckmäßige Ergänzung der an Hand von FIG 2 beschriebenen Anordnung bildet die Schaltung von FIG 3 zur Überwachung der oberen Spannungsgrenze der Speisespannung VC zum Schutz der vorhandenen Detektoren bei nur sehr geringem Stromverbrauch im nichtaktivierten Zustand. Dieser Überwachungsschaltkreis besteht aus einem Feldeffekttransistor vom P-Kanal-Typ, an dessen Elektrode G eine Referenzspannung VREF anliegt, während die Elektrode S über eine Zenerdiode ZD1 und eine Siliziumdiode D11 mit der Speisespannung VC verbunden ist. Beide Elektroden G und S sind außerdem in der dargestellten Weise über eine Schottkky-Diode D12 zur Stabilisierung miteinander verbunden, die den Transistor V auch bei kleinen Schwankungen der Referenzspannung gesperrt hält.A useful addition to the arrangement described with reference to FIG. 2 is the circuit of FIG. 3 for monitoring the upper voltage limit of the supply voltage V C to protect the existing detectors with only very low power consumption in the non-activated state. This monitoring circuit consists of a field-effect transistor of the P-channel type, to the electrode G of which a reference voltage V REF is applied, while the electrode S is connected to the supply voltage V C via a Zener diode ZD1 and a silicon diode D11. Both electrodes G and S are also connected in the manner shown via a Schottkky diode D12 for stabilization, which keeps transistor V blocked even with small fluctuations in the reference voltage.

Übersteigt die Speisespannung VC die Summe aus Referenzspannung VREF, Schwellenspannung des Transistors V, Vorwärtsspannung an der Diode D11 und Zenerspannung, dann wird der Transistor V leitend und liefert an der Elektrode D das Alarmsignal AL.If the supply voltage V C exceeds the sum of the reference voltage V REF , the threshold voltage of the transistor V, the forward voltage at the diode D11 and the Zener voltage, then the transistor V becomes conductive and supplies the alarm signal AL at the electrode D.

FIG 4 zeigt dagegen den nur periodisch aktivierten Dektektor D-T/U U zur Überwachung der vorgegebenen Temperaturgrenzen und der unteren Spannungsgrenze der Speisespannung VC. Die Aktivierung dieses Überwachhungsschaltkreises erfolgt beispielsweise durch den Oszillatortakt OSZ von FIG 2, der über einen Frequenzteiler FT auf einen aus zwei Komparatoren mit Strobeeingang STR bestehenden Baustein SHC1 einwirkt, wie er bereits in Verbindung mit dem dynamisch arbeitenden Überwachungsschaltkreis für die Schutzleiter M... von FIG 2 erwähnt wurde. Die Aktivierung erfolgt beispielsweise im Sekundenabstand, wobei jedesmal ein positiver Spannungsimpuls VPP zur Speisung des Überwachungsschaltkreises vom Baustein SHC1 erzeugt wird. Dieser Spannungsimpuls arbeitet auf eine Zenerdiode ZD2, der mehrere Spannungsteiler parallel geschaltet sind. Der aus dem Widerstand R21 und R22 bestehende Spannungsteiler liefert dann an seinem Mittenabgriff eine Meßspannung, die vom Komparator A zu der Zenerspannung addiert und damit die untere zulässige Spannungsgrenze festlegt. Wird diese Spannungsgrenze von der Speisespannung VC unterschritten, löst der Komparator A über die nachgeschaltete Diode der Schottky-Doppeldiode SDD3 das Alarmsignal AL aus.FIG. 4, on the other hand, shows the only periodically activated detector DT / U U for monitoring the specified temperature limits and the lower voltage limit of the supply voltage V C. The activation This monitoring circuit is carried out, for example, by the oscillator clock OSZ from FIG. 2, which acts via a frequency divider FT on a module SHC1 consisting of two comparators with strobe input STR, as it already does in connection with the dynamically operating monitoring circuit for the protective conductor M ... of FIG. 2 was mentioned. The activation takes place, for example, at intervals of seconds, each time generating a positive voltage pulse VPP for supplying the monitoring circuit from the SHC1 module. This voltage pulse works on a Zener diode ZD2, to which several voltage dividers are connected in parallel. The voltage divider consisting of the resistors R21 and R22 then supplies a measuring voltage at its center tap which is added by the comparator A to the Zener voltage and thus defines the lower permissible voltage limit. If the supply voltage V C falls below this voltage limit, the comparator A triggers the alarm signal AL via the downstream diode of the Schottky double diode SDD3.

Für die Temperaturgrenzenüberwachung sind zwei weitere Spannuungsteiler vorgesehen, nämlich einer mit einem Heißleiter HL und einem Widerstand R25 und einer mit einem Kaltleiter KL und einem Widerstand R26. Die Mittenabgriffe dieser beiden Spannungsteiler sind über jeweils eine Diode eines Schottky-Diodenpaares SDD2 an einen gemeinsamen Meßspannungsausgang geführt. Bei tiefen Temperaturen wird die am Heißleiter HL abfallende Spannung größer als die am Kaltleiter KL, und umgekehrt wird bei hohen Temperaturen der Spannungsabfall am Kaltleiter KL größer als der am Heißleiter HL. Durch den exponentiellen Anstieg der Widerstandswerte von HL und KL abhängig von der Temperatur, sind die gewünschten Temperaturgrenzen durch die Widerstände R25 bzw. R26 sehr genau einstellbar. Die am Mittenausgang des Schottky-Diodenpaares SDD2 sich ergebende resultierende Spannung wird dann vom Komparator B des Bausteines SHC1 mit einer Referenzspannung verglichen, die am Mittenabgriff eines weiteren, aus den Widerständen R23 und R24 bestehenden Spannungsteilers über eine der Dioden eines Schottky-Diodenpaares SDD1 geliefert wird. Die Verwendung baugleicher Diodenstrecken erhöht dabei die Meßgenauigkeit der Schaltung. Auch werden den Eingängen des Komparators B zweckmäßig gleiche Lastwiderstände RL und Filterkondensatoren CL parallelgeschaltet. Überschreitet die Spannung vom Diodenpaar SDD2 die vom Diodenpaar SDD1, dann wird gleichfalls über die zugehörige Diode des Diodenpaares SDD3 das Alarmsignal AL ausgelöst.Two further voltage dividers are provided for temperature limit monitoring, namely one with a thermistor HL and a resistor R25 and one with a PTC thermistor KL and a resistor R26. The center taps of these two voltage dividers are each led to a common measuring voltage output via a diode of a Schottky diode pair SDD2. At low temperatures, the voltage drop across the thermistor HL becomes greater than that at the PTC thermistor KL, and conversely, at high temperatures, the voltage drop across the PTC thermistor KL becomes greater than that at the thermistor HL. Due to the exponential increase in the resistance values of HL and KL depending on the temperature, the desired temperature limits can be set very precisely by the resistors R25 and R26. The resulting voltage at the center output of the Schottky diode pair SDD2 is then compared by the comparator B of the component SHC1 with a reference voltage, which at the center tap of a further voltage divider consisting of the resistors R23 and R24 via one of the Diodes of a Schottky diode pair SDD1 is supplied. The use of identical diode sections increases the measuring accuracy of the circuit. The same load resistors R L and filter capacitors C L are also advantageously connected in parallel to the inputs of the comparator B. If the voltage of the diode pair SDD2 exceeds that of the diode pair SDD1, then the alarm signal AL is also triggered via the associated diode of the diode pair SDD3.

Claims (9)

Schaltungsanordnung zur Sicherung elektronischer Bauteile in Geräten mit geheim zu haltenden Schaltungen und/oder Daten, bestehend aus wenigstens einem batteriegespeisten Detektor zur Überwachung von gegen mechanisches Eindringen vorgesehenen parallelen Schutzleitern auf Unterbrechung und Kurzschluß,
dadurch gekennzeichnet,
daß die beiden Schutzleiter (M1,M2) mit zwei unabhängigen Überwachungsschaltkreisen gekoppelt sind, die abwechselnd wirksam geschaltet werden,
daß ein erster, statisch arbeitender Überwachungsschaltkreis (CB,V6,V7,V8) in herkömlicher Weise Unterbrechungen und Kurzschlüsse und ein zweiter, dynamisch arbeitender (S1,S2,V4,V5,SHC) neben Unterbrechungen auch partielle Kurzschlüsse an jedem Schutzleiter (M1,M2) überwacht, indem bei einer mit Spannung (UST) beaufschlagten Reihenschaltung beider Schutzleiter (M1,M2) die Spannung (UM) an einem Punkt (A) der in Reihe geschalteten Schutzleiter gemessen und mit der (UREF) der vorhergehenden Messung verglichen wird, und
daß bei einer einen vorgegebenen Wert (UDEL) überschreitenden Spannungsdifferenz Alarm (AL1) und/oder die zur Sicherung notwendige Schaltfunktion ausgelöst wird.
Circuit arrangement for securing electronic components in devices with circuits and / or data to be kept secret, consisting of at least one battery-fed detector for monitoring parallel protective conductors provided against mechanical intrusion for interruptions and short circuits,
characterized,
that the two protective conductors (M1, M2) are coupled to two independent monitoring circuits, which are activated alternately,
that a first, statically operating monitoring circuit (CB, V6, V7, V8) traditionally interruptions and short circuits and a second, dynamically operating (S1, S2, V4, V5, SHC) in addition to interruptions also partial short circuits on each protective conductor (M1, M2) is monitored by measuring the voltage (U M ) at a point (A) of the protective conductors connected in series and with the (U REF ) of the previous measurement when the two protective conductors (M1, M2) are connected in series with voltage (U ST ) is compared, and
that an alarm (AL1) and / or the switching function necessary for securing is triggered when the voltage difference exceeds a predetermined value (U DEL ).
Schaltungsanordnung nach Anspruch 1,
dadurch gekennzeichnet,
daß die Umschaltung zwischen den beiden Überwachungsschaltkreisen durch eine Taktimpulssteuerung (OSZ) erfolgt, wobei die Umschaltung auf den dynamisch arbeitenden Überwachungsschaltkreis jeweils nur kurzzeitig für eine die Durchführung der Messung erforderliche Dauer (T1) periodisch wiederkehrend vorgenommen wird, während in der übrigen Zeit (T2) jeweils der statisch arbeitende Überwachungsschaltkreis wirksam geschaltet ist.
Circuit arrangement according to claim 1,
characterized,
that the switchover between the two monitoring circuits is carried out by a clock pulse control (OSZ), the switchover to the dynamically operating monitoring circuit being carried out periodically for a period (T1) required to carry out the measurement, while the rest of the time (T2) the statically operating monitoring circuit is activated.
Schaltungsanordnung nach Anspruch 2,
dadurch gekennzeichnet,
daß die Prüfspannung (UST) für die Reihenschaltung der Schutzleiter (M1,M2) im dynamisch arbeitenden Überwachungsschaltkreis von den die Aktivierung bewirkenden Taktimpulsen (T1) abgeleitet wird.
Circuit arrangement according to claim 2,
characterized,
that the test voltage (U ST ) for the series connection of the protective conductors (M1, M2) in the dynamically operating monitoring circuit is derived from the clock pulses (T1) causing the activation.
Schaltungsanordnung nach Anspruch 3,
dadurch gekennzeichnet,
daß die Prüfspannung (UST) stabilisiert wird (z.B. durch Zenerdiode ZD).
Circuit arrangement according to claim 3,
characterized,
that the test voltage (U ST ) is stabilized (eg by Zener diode ZD).
Schaltungsanordnung nach Anspruch 4,
dadurch gekennzeichnet,
daß parallel zum die Reihenschaltung der beiden Schutzleiter (M1,M2) herstellenden Schalter (S1) und dem einen mit dem Gegenpotential (GND) zur Prüfspannung (UST) verbundenen Schutzleiter (M2) ein erster Kondensatorladekreis (R6,C1) durch einen weiteren Schalter (S2) wirksam geschaltet wird.
Circuit arrangement according to claim 4,
characterized,
that in parallel with the series connection of the two protective conductors (M1, M2) producing switch (S1) and the one with the opposite potential (GND) to the test voltage (U ST ) connected to the protective conductor (M2) a first capacitor charging circuit (R6, C1) by a further switch (S2) is activated.
Schaltungsanordnung nach Anspruch 5,
dadurch gekennzeichnet,
daß parallel zum ersten Kondensatorladekreis (R6,C1) ein zweiter Kondensatorladekreis (R7,C3) vorgesehen ist, daß der Kondensator (C3) des zweiten Kondensatorladekreises (R7,C3) über einen, einen bidirektionalen Ladungsaustausch ermöglichenden Steuerschaltkreis (V4,V5) mit einem weiteren Kondensator (C2) koppelbar ist, so daß dessen Ladespannung jeweils in den Pausen (T2) zwischen den steuernden Taktimpulsen (T1) an die des Kondensators (C3) im zweiten Kondensatorladekreis anpaßbar ist und während der jeweils nachfolgenden Aktivierung des Überwachungsschaltkreises die der jeweils vorhergehenden Messung entsprechende Bezugsspannung (UREF) liefert.
Circuit arrangement according to claim 5,
characterized,
that a second capacitor charging circuit (R7, C3) is provided in parallel to the first capacitor charging circuit (R6, C1), that the capacitor (C3) of the second capacitor charging circuit (R7, C3) has a control circuit (V4, V5) which enables bidirectional charge exchange Another capacitor (C2) can be coupled, so that its charging voltage can be adapted in the pauses (T2) between the controlling clock pulses (T1) to that of the capacitor (C3) in the second capacitor charging circuit and during the subsequent activation of the monitoring circuit that of the previous one Measurement provides the corresponding reference voltage (U REF ).
Schaltungsanordnung nach Anspruch 6,
dadurch gekennzeichnet,
daß die Prüfspannung (UST) weiterhin einen Spannungsteiler (R3,R4,R5) speist, der von einem Abgriff eine Grenzspannung (UDEL) liefert,
daß jeweils nach ausreichender Verzögerung die Differenz zwischen der jeweiligen Meßspannung (UM) am Kondensator (C1) im ersten Kondensatorladekreis und der Bezugsspannung (UREF) am weiteren Kondensator (C2) gebildet und mit der Grenzspannung (UDEL) verglichen wird.
Circuit arrangement according to claim 6,
characterized,
that the test voltage (U ST ) continues to feed a voltage divider (R3, R4, R5) which supplies a limit voltage (U DEL ) from one tap,
that after a sufficient delay, the difference between the respective measuring voltage (U M ) across the capacitor (C1) in the first capacitor charging circuit and the reference voltage (U REF ) across the further capacitor (C2) is formed and compared with the limit voltage (U DEL ).
Schaltungsanordnung nach einem der Ansprüche 2 bis 7,
dadurch gekennzeichnet,
daß das Wirksamsein der Taktimpulssteuerung (OSZ) für die wiederkehrende Umschaltung zwischen den beiden Überwachungsschaltkreisen ständig überwacht und bei deren Unwirksamwerden ebenfalls ein Alarmsignal (AL3) ausgelöst wird.
Circuit arrangement according to one of claims 2 to 7,
characterized,
that the effectiveness of the clock pulse control (OSZ) for the recurring switching between the two monitoring circuits is constantly monitored and when they become ineffective, an alarm signal (AL3) is also triggered.
Schaltungsanordnung nach einem der Ansprüche 2 bis 8,
dadurch gekennzeichnet,
daß die Taktimpulssteuerung (OSZ) auch für das überlappungsfreie Wirksamschalten weiterer Detektoreinheiten (D-T/UU) zur Überwachung sich von langsam ändernden Größen in größeren Zeitabständen verwendet wird, deren Ansteuerung über einen Frequenzteiler (FT) erfolgt.
Circuit arrangement according to one of claims 2 to 8,
characterized,
that the clock pulse control (OSZ) is also used for the overlap-free activation of further detector units (DT / U U ) for monitoring slowly changing quantities at greater intervals, which are controlled via a frequency divider (FT).
EP96114000A 1995-09-29 1996-08-30 Circuit for securing electronic components Expired - Lifetime EP0766213B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19536477A DE19536477C2 (en) 1995-09-29 1995-09-29 Circuit arrangement for securing electronic components
DE19536477 1995-09-29

Publications (2)

Publication Number Publication Date
EP0766213A1 true EP0766213A1 (en) 1997-04-02
EP0766213B1 EP0766213B1 (en) 2001-11-07

Family

ID=7773678

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96114000A Expired - Lifetime EP0766213B1 (en) 1995-09-29 1996-08-30 Circuit for securing electronic components

Country Status (3)

Country Link
EP (1) EP0766213B1 (en)
AT (1) ATE208521T1 (en)
DE (2) DE19536477C2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102021111472A1 (en) 2021-05-04 2022-11-10 Markus Geiger Tamper-proof device for protecting an electronic memory element against being read out

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641547A (en) * 1970-05-25 1972-02-08 Alarmtronics Eng Inc Line security system
DE2809596A1 (en) * 1978-03-06 1979-09-20 Merk Gmbh Telefonbau Fried Circuit detecting earth faults in two=wire signal line - has resistor connected to each battery terminal and earthed in turns
US4593384A (en) * 1984-12-21 1986-06-03 Ncr Corporation Security device for the secure storage of sensitive data
EP0268142A2 (en) * 1986-11-05 1988-05-25 International Business Machines Corporation Tamper-resistant packaging for protection of information stored in electronic circuitry
EP0347209A2 (en) * 1988-06-17 1989-12-20 W.L. Gore & Associates, Inc. Security enclosure
EP0529116A1 (en) * 1991-08-22 1993-03-03 Siemens Nixdorf Informationssysteme Aktiengesellschaft Monitoring circuit for two protective conductors wrapped around a device
US5387899A (en) * 1993-07-29 1995-02-07 At&T Corp. Alarm system with monitoring circuit for detecting a cut or short in a pair of wires

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027397A (en) * 1989-09-12 1991-06-25 International Business Machines Corporation Data protection by detection of intrusion into electronic assemblies
DE4115703C1 (en) * 1991-05-14 1992-08-27 Siemens Nixdorf Informationssysteme Ag, 4790 Paderborn, De

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641547A (en) * 1970-05-25 1972-02-08 Alarmtronics Eng Inc Line security system
DE2809596A1 (en) * 1978-03-06 1979-09-20 Merk Gmbh Telefonbau Fried Circuit detecting earth faults in two=wire signal line - has resistor connected to each battery terminal and earthed in turns
US4593384A (en) * 1984-12-21 1986-06-03 Ncr Corporation Security device for the secure storage of sensitive data
EP0268142A2 (en) * 1986-11-05 1988-05-25 International Business Machines Corporation Tamper-resistant packaging for protection of information stored in electronic circuitry
EP0347209A2 (en) * 1988-06-17 1989-12-20 W.L. Gore & Associates, Inc. Security enclosure
EP0529116A1 (en) * 1991-08-22 1993-03-03 Siemens Nixdorf Informationssysteme Aktiengesellschaft Monitoring circuit for two protective conductors wrapped around a device
US5387899A (en) * 1993-07-29 1995-02-07 At&T Corp. Alarm system with monitoring circuit for detecting a cut or short in a pair of wires

Also Published As

Publication number Publication date
DE19536477C2 (en) 1997-10-23
EP0766213B1 (en) 2001-11-07
ATE208521T1 (en) 2001-11-15
DE59608129D1 (en) 2001-12-13
DE19536477A1 (en) 1997-04-03

Similar Documents

Publication Publication Date Title
EP0870646B1 (en) Electronic blinker
DE102007031494A1 (en) Power supply controller for use in vehicle, has short circuit error detector outputting short circuit anomaly signal if one of signals from respective determining circuits is output during receipt of OFF-signal
DE10356259B4 (en) Method and circuit arrangement for increasing a functional range in a device supplied with energy from an electromagnetic field
DE3429060A1 (en) MONITORING DEVICE WITH SEVERAL SWITCHES
DE2701614A1 (en) DISPLAY SYSTEM
DE2528812B2 (en) Anti-bounce circuit
EP0116701A1 (en) Anti-theft device
DE19810826A1 (en) Measurement device for digital detection of analog measurement signals
DE3722335C2 (en)
EP0766213B1 (en) Circuit for securing electronic components
EP1047582A1 (en) Circuit for monitoring the ignition system for a safety device in an automobile
EP0308766B1 (en) Proximity switch with testing and evaluating circuits
EP0190547A1 (en) Device for monitoring and counting the response of a non-spark gap overvoltage arrester
DE10006526A1 (en) Temperature-protected semiconductor circuit arrangement
DE4301530C1 (en) Inductive switch-on sensor for battery operated coin validators
DE3714630A1 (en) DEVICE FOR MONITORING ELECTRONIC DEVICES
DE19904608C2 (en) Device for testing an electrolytic capacitor and method for testing an electrolytic capacitor
DE19518752A1 (en) Theft prevention system for department store
DE102020131060A1 (en) INTELLIGENT ELECTRONIC SWITCH
DE102008057725A1 (en) System for adjusting, adjusting and / or programming electronic devices, in particular measuring devices, which have sensors, and circuit arrangements for adjusting, setting or programming electronic elements, such as digital potentiometers
DE2713280B2 (en) Fire alarm system with at least one two-wire alarm line for ionization fire alarms supplied with DC voltage
DE2227741A1 (en) Method and circuit arrangement for the precise measurement of the frequency of an electronic signal. . Note: Honeywell Information Systems Inc., Waltham, Mass. (V.StA.)
DE19717811A1 (en) Monitoring circuit for at least one supply voltage
DE2639971C2 (en) Switching amplifier for a control computer
DE19524616C2 (en) Method for testing overtemperature detection in an integrated circuit

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE ES FR GB IT LI NL SE

17P Request for examination filed

Effective date: 19970421

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 20001011

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: FUJITSU SIEMENS COMPUTERS GMBH

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE ES FR GB IT LI NL SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20011107

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT

Effective date: 20011107

Ref country code: GB

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20011107

Ref country code: FR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20011107

REF Corresponds to:

Ref document number: 208521

Country of ref document: AT

Date of ref document: 20011115

Kind code of ref document: T

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: CH

Ref legal event code: NV

Representative=s name: E. BLUM & CO. PATENTANWAELTE

REF Corresponds to:

Ref document number: 59608129

Country of ref document: DE

Date of ref document: 20011213

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20020207

NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
GBV Gb: ep patent (uk) treated as always having been void in accordance with gb section 77(7)/1977 [no translation filed]

Effective date: 20011107

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20020530

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020830

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020831

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020831

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020831

EN Fr: translation not filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
BERE Be: lapsed

Owner name: *FUJITSU SIEMENS COMPUTERS G.M.B.H.

Effective date: 20020831

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030301

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL