DE19848540A1 - Circuit layout and method for operating a single- or multiphase current inverter connects an AC voltage output to a primary winding and current and a working resistance to a transformer's secondary winding and current. - Google Patents

Circuit layout and method for operating a single- or multiphase current inverter connects an AC voltage output to a primary winding and current and a working resistance to a transformer's secondary winding and current.

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DE19848540A1
DE19848540A1 DE19848540A DE19848540A DE19848540A1 DE 19848540 A1 DE19848540 A1 DE 19848540A1 DE 19848540 A DE19848540 A DE 19848540A DE 19848540 A DE19848540 A DE 19848540A DE 19848540 A1 DE19848540 A1 DE 19848540A1
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control
voltage
output
current
input
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Reinhard Kalfhaus
Christoph Schiller
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0003Details of control, feedback or regulation circuits
    • H02M1/0009Devices or circuits for detecting current in a converter

Abstract

A circuit layout (10) operates a single- or multiphase current inverter (12) with its AC voltage output connected to a primary winding (15) carrying a primary current (IP). A working resistance can be connected to a secondary winding (60,62) in a transformer carrying a secondary current (IS), including a regulating circuit (78) and a triggering unit (40) for triggering pulse in power semiconductors (T1-T4) in the current converter.

Description

Die Erfindung bezieht sich auf eine Schaltungsanordung zum Betreiben eines ein- oder mehrphasigen Wechselsrichters, dessen Wechselspannungsausgang mit einer einen Primär­ strom IP führenden Primärwicklung eines Transformators verbunden ist, wobei an zumindest einer einen Sekundärstrom IS führenden Sekundärwicklung des Transformators eine Last anschließbar ist und wobei die Schaltungsanordnung einen Regelkreis und eine Ansteuer­ einheit zur Pulsansteuerung von Leistungshalbleiterschaltern des Wechselrichters umfasst.The invention relates to a circuit arrangement for operating a single-phase or multi-phase inverter, the alternating voltage output of which is connected to a primary winding of a transformer carrying a primary current I P, a load being connectable to at least one secondary winding of the transformer carrying a secondary current I S , and wherein the circuit arrangement comprises a control circuit and a control unit for pulse control of power semiconductor switches of the inverter.

Derartige Wechselrichter sind aus dem Stand der Technik bekannt und werden vorwiegend in der Bahn-, Schiffs- und Automobiltechnik eingesetzt um aus einer durch das Bordnetz vorgegebenen Gleichspannung eine Wechselspannung bestimmter Frequenz und Amplitude zum Antrieb eines Wechselspannungsverbrauchers zu erzeugen.Such inverters are known from the prior art and are predominantly used in rail, ship and automotive technology to create one through the electrical system predetermined DC voltage an AC voltage of certain frequency and amplitude to drive an AC voltage consumer.

Um die Ausgangswechselspannung des Wechselrichters anzupassen (vergrößern bzw. ver­ kleinern) wird dem Ausgang des Wechselrichters ein Transformator nachgeschaltet, der die Ausgangswechselspannung des Wechselrichters auf einen angepaßten (höheren bzw. kleine­ ren) Spannungswert transformiert.To adjust the output AC voltage of the inverter (enlarge or ver smaller), a transformer is connected downstream of the output of the inverter Output AC voltage of the inverter to an adapted (higher or small ren) voltage value transformed.

Die Eingangsspannung liegt üblicherweise im Bereich von 24 bis 750 VDC und kann auf Ausgangsspannungen im Bereich vom 220 bis 1500 VAC mit Frequenzen vom 16 2/3, 50 bis 400 Hz eingestellt werden.The input voltage is usually in the range from 24 to 750 VDC and can be set to  Output voltages in the range from 220 to 1500 VAC with frequencies from 16 2/3, 50 to 400 Hz can be set.

Insbesondere bei einer geringen Eingangsgleichspannung von ca. 24 VDC und einer Gesamt­ leistung des Wechselrichters von ca. 1 kW und mehr können Primärströme IP von 100 A und mehr fließen, die einen Gleichanteil aufweisen und den nachgeschalteten Transformator in die Sättigung treiben. Durch die Sättigung zeigt der Transformator ein unsymmetrisches Verhal­ ten, das insgesamt den Wirkungsgrad des Wechselrichters erheblich verschlechtert und stören­ de Netzrückwirkungen verursacht.In particular with a low DC input voltage of approx. 24 VDC and a total power of the inverter of approx. 1 kW and more, primary currents I P of 100 A and more can flow, which have a DC component and drive the downstream transformer into saturation. Due to the saturation, the transformer exhibits an asymmetrical behavior, which overall considerably reduces the efficiency of the inverter and causes disturbing grid effects.

Zur Ansteuerung eines Wechselrichters ist das Pulsweitenmodulationsverfahren (PWM-Ver­ fahren) bekannt. Dabei ist zur Erzeugung einer Steuerspannung ein Vergleicher vorgesehen, dem ein Ist-Wert der ausgangsseitigen Wechselspannung und ein vorgegebener Soll-Wert eines Wechselspannungsverlaufs zum Vergleich zugeführt wird und dessen Ausgang mit einem Komparator verbunden ist, in dem die Steuerspannung mit einer sägezahnförmigen oder dreieckförmigen Vergleichsspannung zur Erzeugung von Ansteuersignalen für die Leistungshalbleiterschalter des Wechselrichters verglichen wird.To control an inverter, the pulse width modulation method (PWM ver drive) known. A comparator is provided to generate a control voltage, which is an actual value of the AC voltage on the output side and a predetermined target value an AC voltage curve is supplied for comparison and its output with a comparator is connected in which the control voltage with a sawtooth or triangular reference voltage for generating control signals for the Power semiconductor switch of the inverter is compared.

Überschreitet jedoch die ermittelte Steuerspannung die sägezahn- oder dreieckförmige Ver­ gleichsspannung, werden keine Ansteuersignale erzeugt, was zu einer Übermodulation führt und sich nachteilig auf den Stromflusswinkel bzw. Verlauf von Ausgangsspannung und/oder -strom auswirkt.However, the determined control voltage exceeds the sawtooth or triangular Ver DC voltage, no control signals are generated, which leads to overmodulation and adversely affect the current flow angle or the course of the output voltage and / or -current affects.

Der vorliegenden Erfindung liegt das Problem zugrunde, eine Schaltungsanordnung und ein Verfahren zum Betreiben eines Wechselrichters derart weiterzubilden, so dass bei weitem Eingangsspannungsbereich und hohen Belastungen einerseits ein hoher Wirkungsgrad und andererseits ein stabiles Regelverhalten gewährleistet wird. Insbesondere soll ein am Ausgang des Wechselrichters liegender Transformator symmetrisch betrieben werden und die Schaltung soll beliebige Stromflusswinkel erfüllen.The present invention is based on the problem of a circuit arrangement and a Develop methods of operating an inverter such that by far Input voltage range and high loads on the one hand high efficiency and on the other hand, a stable control behavior is guaranteed. In particular, one should be at the exit of the inverter lying transformer can be operated symmetrically and the circuit should meet any current flow angle.

Das Problem wird durch eine Schaltungsanordnung einerseits dadurch gelöst, dass ein erstes Messelement zur Erfassung des Primärstroms IP und zweites Messelement zur Erfassung des Sekundärstrom IS vorgesehen ist, dass eine Regeldifferenz aus Primärstrom IP und Sekundär­ strom IS einer überlagerten Spannungsregeleinrichtung zugeführt wird, dass ein Ausgang der Spannungsregeleinrichtung mit einem Vergleicher einer unterlagerten Stromregeleinrichtung verbunden ist, dass dem Vergleicher der Primärstrom IP als Strom-Istwert IPIST zugeführt wird und dass ein Ausgang der Stromregeleinrichtung mit einem Eingang der Ansteuereinheit verbunden ist.The problem is solved on the one hand by a circuit arrangement in that a first measuring element for detecting the primary current I P and a second measuring element for detecting the secondary current I S is provided, and a control difference between the primary current I P and the secondary current I S is fed to a superimposed voltage control device, that an output of the voltage control device is connected to a comparator of a subordinate current control device, that the primary current I P is supplied to the comparator as actual current value I PIST and that an output of the current control device is connected to an input of the control unit.

Andererseits wird das Problem dadurch gelöst, dass dass ein erstes Messelement zur Erfas­ sung des Primärstromes IP und ein zweites Messelement zur Erfassung des Sekundärstroms IS vorgesehen ist, dass eine Regeldifferenz aus Primärstrom IP und Sekundärstrom IS einer überlagerten Spannungsregeleinrichtung zugeführt wird, dass eine Ausgangsgröße der Spannungsregeleinrichtung einer unterlagerten Stromregeleinrichtung zugeführt und mit dem Primärstrom IP als Strom-Istwert IPIST zur Anpassung an dessen Kurvenform verglichen wird, wobei beliebige Phasenwinkel ϕ und Kurvenformen des Ausgangsstromes bzw. Sekundär­ stromes IS zur Ausgangsspannung UA regelbar sind und dass ein Ausgang der Stromregelein­ richtung mit einem Eingang der Ansteuereinheit verbunden ist.On the other hand, the problem is solved in that a first measuring element for detecting the primary current I P and a second measuring element for detecting the secondary current I S is provided in that a control difference between the primary current I P and the secondary current I S is fed to a superimposed voltage control device that an output variable of the voltage regulating device is fed to a subordinate current regulating device and compared with the primary current I P as the actual current value I PIST for adaptation to its curve shape, any phase angle ϕ and curve forms of the output current or secondary current I S to the output voltage U A being controllable and that an output of the current control device is connected to an input of the control unit.

Durch die Erfassung der pimär- und sekundärseitigen Ströme IP, Is des Transformators kann eine Information über die symmetrische Auslastung des Transformators abgeleitet werden. Die Stromwerte werden wie beschrieben einer Regeleinrichtung zugeführt und als Stör­ größenaufschaltung dem eingangsseitigen ersten Vergleicher zugeführt. Auf diese Weise wird eine dem Spannungsregler zuzuführende Regelabweichung beeinflusst, so dass eine in dem Transformator auftretende Unsymmetrie ausgeregelt wird. Ergänzend ist ein unterlagerter Stromregelkreis vorgesehen, dem der Primärstrom IP des Transformators als Ist-Wert und die Ausgangsgröße der ersten Regeleinrichtung als Soll-Wert zugeführt wird. Durch die erfin­ dungsgemäße Anordnung können Unsymmetrien der Transformatorbelastung ausgeregelt werden. Durch den unterlagerten Stromregelkreis wird insgesamt eine stabile Regelung erreicht. Durch die Unterlagerung des Stromregelkreises kann die verstärkte Fehlerdifferenz des Spannungsregelkreises einer Kurvenform des Stromistwertes IPIST des Primärstroms angepasst werden. Der Primärstrom IPIST ist über dem Übersetzungsverhältnis ü des Tans­ formators mit dem Sekundärstrom IS und damit auch mit dem Ausgangsstrom verknüpft. Ins­ besondere müssen Ausgangsstrom und -spannung nicht in Phase liegen, so dass die Schaltung mit einem bliebigen Stromflusswinkel im Bereich von 0 ≦ cos ϕ ≦ ±1 betrieben werden kann. Es können beliebige Phasenwinkel ϕ und Kurvenformen des Ausgangsstromes zur Ausgangs­ spannung erfüllt werden.By detecting the primary and secondary currents I P , Is of the transformer, information about the symmetrical utilization of the transformer can be derived. As described, the current values are fed to a control device and fed to the input-side first comparator as a disturbance variable feed-in. In this way, a control deviation to be supplied to the voltage regulator is influenced, so that an asymmetry occurring in the transformer is corrected. In addition, a subordinate current control circuit is provided, to which the primary current I P of the transformer is supplied as the actual value and the output variable of the first control device as the target value. As a result of the arrangement according to the invention, asymmetries in the transformer load can be corrected. Overall, stable regulation is achieved by the subordinate current control loop. By superimposing the current control loop, the amplified error difference of the voltage control loop can be adapted to a curve shape of the actual current value I PIST of the primary current. The primary current I PIST is linked via the transmission ratio ü of the transformer with the secondary current I S and thus also with the output current. In particular, the output current and voltage do not have to be in phase, so that the circuit can be operated with a constant current flow angle in the range of 0 ≦ cos ϕ ≦ ± 1. Any phase angle ϕ and waveforms of the output current to the output voltage can be fulfilled.

Zur weiteren Verbesserung des Regelverhaltens ist vorgesehen, dass der Spannungsregler zur Begrenzung seines Ausgangssignal ein Rückkoppelglied aufweist, dessen Eingang mit dem Ausgang des Spannungsreglers und dessen Ausgang mit dem ersten Vergleicher verbunden ist. Das Ausgangssignal des Spannungsreglers dient als Soll-Wert für den nachgeschalteten Stromregler und wird mit dem Ist-Wert des Primärstroms IP verglichen. Die Begrenzung ist einstellbar.To further improve the control behavior, it is provided that the voltage regulator has a feedback element to limit its output signal, the input of which is connected to the output of the voltage regulator and the output of which is connected to the first comparator. The output signal of the voltage regulator serves as the target value for the downstream current regulator and is compared with the actual value of the primary current I P. The limitation is adjustable.

Um insbesondere im Leerlauffall einen stabilen Regelkreis zu erhalten, ist vorgesehen, dass dem Stromregler zur Resonanzdämpfung ein Rückkoppelglied, vorzugsweise ein LC-Filter zugeordnet ist.In order to maintain a stable control loop, especially when idling, it is provided that the current regulator for resonance damping a feedback element, preferably an LC filter assigned.

Bei einer bevorzugten Ausführungsform ist vorgesehen, dass die Messelemente zur Erfassung der Ströme IP und IS mit Eingängen eines zweiten Vergleichers verbunden sind und dass ein Ausgang des zweiten Vergleichers über einen Regler, vorzugsweise PI-Regler mit dem ersten Vergleicher des Spannungsreglers verbunden ist.In a preferred embodiment it is provided that the measuring elements for detecting the currents I P and I S are connected to inputs of a second comparator and that an output of the second comparator is connected to the first comparator of the voltage regulator via a regulator, preferably a PI regulator.

Zur Filterung der Ausgangsspannung des Wechselrichters wird vorgeschlagen, dass der Primärwicklung des Transformators zumindest eine Drosselspule in Reihe geschaltet ist, wobei die zumindest eine Drosselspule vorzugsweise integraler Bestandteil des Transforma­ tors ist. Auf diese Weise werden Anschlussklemmen eingespart, da mehrere Bauteile in einem vereinigt sind. Bei einer besonders bevorzugten Ausführungsform ist vorgesehen, dass der Primärwicklung des Transformators eine erste Drosselspule vorgeschaltet und eine zweite Drosselspule nachgeschaltet ist. Beide Drosselspulen sind dabei integraler Bestandteil des Transformators. To filter the output voltage of the inverter, it is proposed that the Primary winding of the transformer at least one choke coil is connected in series, wherein the at least one choke coil is preferably an integral part of the transforma tors is. In this way, terminals are saved, since several components in one are united. In a particularly preferred embodiment it is provided that the Primary winding of the transformer upstream of a first choke coil and a second Choke coil is connected downstream. Both choke coils are an integral part of the Transformer.  

Vorzugsweise ist ein weiterer Kondensator als Filterelement vorgesehen, der parallel zu zu­ mindest einer Sekundärwicklung angeschlossen ist. Hierzu ist anzumerken, dass dieser Kondensator nach dem Stand der Technik zwischen der zumindest einen Drosselspule und den Anschlüssen der Primärwicklung angeordnet ist. Durch die Verlagerung des Kondensators in den Senkundärstromkreis werden eine Vielzahl von Vorteilen erreicht. Insbesondere wird neben der Stabilisierung des Regelkreises das CV-Produkt verbessert wodurch ein Kon­ densator kleinerer Baugröße eingesetzt werden kann.A further capacitor is preferably provided as a filter element, which is parallel to at least one secondary winding is connected. It should be noted that this State of the art capacitor between the at least one choke coil and the connections of the primary winding is arranged. By moving the capacitor A number of advantages are achieved in the secondary circuit. In particular In addition to the stabilization of the control loop, the CV product is improved, whereby a con Smaller size capacitor can be used.

Ferner bezieht sich die Erfindung auf ein Verfahren zum Betreiben eines Wechselrichtes, dessen Ausgangsspannung durch einen Transformator transformiert wird, wobei der Trans­ formator eingangsseitig einen Primärstrom IP und ausgangsseitig einen Sekundärstrom IS führt, wobei ein Ausganggsspannungs-Ist-Wert des Transformators gemessen und zur Bildung einer Regelabweichung mit einem Ausgangsspannungs-Soll-Wert verglichen wird und wobei die Regelabweichung verstärkt und als Steuerspannung zur Erzeugung von pulsmodullierten Ansteuersignalen verwendet wird.The invention further relates to a method for operating an inverter, the output voltage of which is transformed by a transformer, the transformer carrying a primary current I P on the input side and a secondary current I S on the output side, an actual output voltage value of the transformer being measured and used Formation of a control deviation is compared with an output voltage target value and the control deviation is amplified and used as a control voltage for generating pulse-modulated control signals.

Das erfindungsgemäße Verfahren ist dadurch gekennzeichnet, dass der Primärstrom IP und der Sekundärstrom IS zur Bildung einer Störgröße gemessen, miteinander verglichen und mit der eingangsseitigen Regelabweichung verknüpft werden, dass die so gebildete Größe verstärkt und als Primärstrom-Soll-Wert IPSOLL zur Bildung einer Regelabweichung mit dem Primär­ strom-Ist-Wert IPIST verknüpft und zur Bildung der Steuerspannung verknüpft wird.The method according to the invention is characterized in that the primary current I P and the secondary current I S are measured to form a disturbance variable, compared with one another and linked to the control deviation on the input side, that the quantity formed in this way is amplified and as the primary current target value I PSOLL for formation a control deviation is linked to the primary current actual value I PIST and is linked to form the control voltage.

Bei dem erfindungsgemäßen Verfahren wird ausgenutzt, dass die Differenz zwischen Primär­ strom-Ist-Wert IPIST und Sekundärstrom-Ist-Wert ISIST ein Maß für die Unsymmetrie des Transformators ist. Durch die eingangsseitige Beaufschlagung des Regelkreises erfolgt eine Störgrößenaufschaltung der an dem Transformator auftretenden Spannungszeitflächen - Unsymmetrie, wodurch das Steuersignal zur Erzeugung der pulsweitenmodullierten Ansteuer­ signale der Leistungsschalter entsprechend verändert wird.In the method according to the invention, use is made of the fact that the difference between the actual primary current value I PIST and the secondary current actual value I SIST is a measure of the asymmetry of the transformer. By applying the control circuit on the input side, a disturbance variable is applied to the voltage time areas occurring on the transformer - asymmetry, as a result of which the control signal for generating the pulse-width-modulated control signals of the circuit breakers is changed accordingly.

Um zu verhindern, dass der Primärstrom IP einen vorgegebenen Wert überschreitet, ist vorgesehen, dass die den Primärstrom-Soll-Wert bildende Ausgangsgröße des eingangsseitigen Spannungsreglers begrenzt wird. Dazu wird das Ausgangssignal gemessen und über ein Rückkoppelglied zurückgeführt.In order to prevent the primary current I P from exceeding a predetermined value, it is provided that the output variable of the voltage regulator on the input side that forms the primary current target value is limited. For this purpose, the output signal is measured and fed back via a feedback element.

Durch die unterlagerte Stromregelung des Primärstroms IP kann der Regelkreis insgesamt stabilisiert werden. Auch wird der Vorteil erreicht, dass beliebige Stromflusswinkel 0 ≦ cos ϕ ≦ ±1 beherrschbar sind.The control circuit as a whole can be stabilized by the subordinate current control of the primary current I P. The advantage is also achieved that any current flow angle 0 ≦ cos ϕ ≦ ± 1 can be controlled.

Die Leistungsschalter des Wechselrichters werden nach dem Pulsweitenmodulationsverfahren (PWM-Verfahren) angesteuert. In diesem Zusammenhang ist besonders auf eine neuartige PWM-Steuerung mit symmetrischer Pulsweitenmodulation hinzuweisen, die einen eigen­ ständigen erfinderischen Charakter aufweist.The circuit breakers of the inverter are based on the pulse width modulation method (PWM process). In this context, special attention is paid to a novel PWM control with symmetrical pulse width modulation to point out that own has a constant inventive character.

Aus dem Stand der Technik sind PWM-Steuerungen bekannt, die einen ersten Komparator zum Vergleich einer Steuerspannung mit einer Vergleichsspannung und einen zweiten Koparator zum Vergleich einer inversen Steuerspannung mit der Vergleichsspannung auf­ weisen, wobei an den Ausgängen der Komparatoren jeweils Steuersignale zur Ansteuerung von Leistungschaltern abgreifbar sind. Die hier beschriebene PWM-Steuerung ist dadurch gekennzeichnet, dass zur Ansteuerung von Leistungsschaltern zumindest eines Brücken­ zweiges zumindest eine Kippschaltung, mit einem Setzeingang und einem Rücksetzeingang vorgesehen ist, wobei ein Ausgang des ersten Komparators über zumindest ein UND-Gatter mit dem Rücksetzeingang und ein Ausgang des zweiten Komparators über zumindest ein UND-Gatter mit dem Setzeingang verbunden ist und wobei das dem Setzeingang zugeordnete UND-Gatter über einen Inverter und das dem Rücksetzeingang zugeordnete UND-Gatter direkt mit einem Ausgang einer Zählschaltung verbunden ist, an dem ein digitales Signal "H" anliegt, das mit der halben Frequenz der Vergleichsspannung schwingt.PWM controls are known from the prior art, which have a first comparator to compare a control voltage with a reference voltage and a second one Coparator for comparing an inverse control voltage with the reference voltage have, wherein at the outputs of the comparators control signals for control can be tapped from circuit breakers. This is the PWM control described here characterized in that for controlling circuit breakers at least one bridge branch at least one flip-flop, with a set input and a reset input is provided, with an output of the first comparator via at least one AND gate with the reset input and an output of the second comparator via at least one AND gate is connected to the set input and the associated with the set input AND gate via an inverter and the AND gate assigned to the reset input is directly connected to an output of a counter circuit at which a digital signal "H" is applied, which vibrates at half the frequency of the reference voltage.

Um Pulsaussetzer für den Fall auszuschließen, wenn die Steuerspannung die Vergleichs­ spannung überschreitet, ist vorgesehen, dass die Ausgänge der Komparatoren über einen Inverter jeweils mit einem Eingang eines UND-Gatters verbunden sind, dessen Ausgang mit jeweils einem Eingang eines ODER-Gatters verbunden ist, wobei ein Ausgang des dem ersten Komparator zugeordneten ODER-Gatters mit einem Eingang des dem Rücksetzeingang zugeordneten UND-Gatters der ersten Kippschaltung und mit einem Eingang eines dem Setzeingang der zweiten Kippschaltung zugeordneten UND-Gatters verbunden ist und wobei ein Ausgang des dem zweiten Komparators zugeordneten ODER-Gatters mit einem Eingang des dem Setzeingang der ersten Kippschaltung zugeordneten UND-Gatters und mit einem Eingang eines dem Rücksetzeingang der zweiten Kippschaltung zugeordneten UND-Gatters verbunden ist.To rule out pulse dropouts in the event when the control voltage compares voltage exceeds, it is provided that the outputs of the comparators via a Inverters are each connected to an input of an AND gate, the output of which each connected to an input of an OR gate, an output of the first  Comparator associated OR gate with an input of the reset input assigned AND gate of the first trigger circuit and with an input of the Set input of the second flip-flop associated AND gate is connected and wherein an output of the OR gate assigned to the second comparator with one input of the AND gate assigned to the set input of the first trigger circuit and with a Input of an AND gate assigned to the reset input of the second trigger circuit connected is.

Dabei sind die UND-Gatter mit einem Ausgang der Zählschaltung verbunden, an dem ein digitales Signal "MIN" anliegt, das bei einem vorgebbaren minimalen Zählerstand den logischen Pegel "LOW" einnimmt und wobei ein Eingang des ODER-Gatters mit einem Ausgang der Zählschaltung verbunden ist, an dem ein digitales Signal "MAX" anliegt, das bei einem vorgebbaren maximalen Zählerstand den logischen Pegel "HIGH" einnimmt.The AND gates are connected to an output of the counter circuit at which one digital signal "MIN" is present, which with a predeterminable minimum counter reading logic level "LOW" and where an input of the OR gate with a Output of the counter circuit is connected to which a digital signal "MAX" is present, which at a logical maximum "HIGH" level.

Des Weiteren ist vorgesehen, dass ein Ausgang der Zählschaltung mit einem Steuereingang des Spannungsgenerators zum Setzen und Rücksetzen der sägezahnförmigen Vergleichs­ spannung verbunden ist.Furthermore, it is provided that an output of the counter circuit with a control input of the voltage generator for setting and resetting the sawtooth comparison voltage is connected.

Dabei ist vorgesehen, dass die Zählschaltung vorzugsweise als 8-Bit-Zähler ausgebildet ist, um eine ausreichende Auflösung zu erhalten.It is provided that the counter circuit is preferably designed as an 8-bit counter, to get a sufficient resolution.

Auch bezieht sich die Erfindung auf ein Verfahren zur Erzeugung von pulsweitenmodullierten Signalen zur Ansteuerung von Leistungsschaltern zumindest eines Brückenzweiges eines Puls­ wechselrichters, wobei eine sägezahnförmige Vergleichsspannung mit einer Steuerspannung und einer inversen Steuerspannung zur Erzeugung von Ansteuerimpulsen verglichen wird und wobei erste Ansteuerimpulse erzeugt werden, wenn die Vergleichsspannung betragsmäßig größer als die Steuerspannung ist und zweite Ansteuerimpulse erzeugt werden, wenn die Vergleichsspannung betragsmäßig größer als die inverse Steuerspannung ist.The invention also relates to a method for generating pulse-width-modulated Signals for controlling circuit breakers of at least one bridge branch of a pulse inverter, with a sawtooth reference voltage with a control voltage and an inverse control voltage for generating drive pulses is compared and wherein first drive pulses are generated when the comparison voltage is absolute is greater than the control voltage and second drive pulses are generated when the Comparative voltage is greater in magnitude than the inverse control voltage.

Dabei ist erfindungsgemäß vorgesehen, dass die Leistungsschalter simultan angesteuert werden, wobei das Setzen eines ersten Leistungsschalters das Rücksetzen eines zweiten Leistungsschalters bewirkt und wobei das Setzen der Leistungsschalter über eine ansteigende Flanke des ersten Impulses und das Rücksetzen über eine ansteigende Flanke des zweiten Impulses erfolgt. Durch das erfindungsgemäße Ansteuerverfahren wird der Vorteil erreicht, dass eine symmetrische Ansteuerung der Leistungsschalter ermöglicht wird. Insbesondere wird sowohl die Einschalt- als auch Ausschaltflanke der Leistungsschalter bei Veränderung des Spannungswertes der Steuerspannung variiert.It is provided according to the invention that the circuit breakers are activated simultaneously be, the setting of a first circuit breaker resetting a second  Circuit breaker causes and the setting of the circuit breaker via a rising Edge of the first pulse and resetting via a rising edge of the second Impulse occurs. The control method according to the invention achieves the advantage that that a symmetrical control of the circuit breaker is made possible. In particular both the switch-on and switch-off edges of the circuit breakers when changed the voltage value of the control voltage varies.

Um zu erreichen, dass bei einer Brückenschaltung die Leistungsschalter eines Brückenzweigs nach jeder zweiten Periode der Vergleichsspannung umgeschaltet werden, ist vorgesehen, dass die von den Komparatoren erzeugten Ansteuerimpulse mit einem digitalen Signal "H" der halben Frequenz der Vergleichsspannung logisch UND-verknüpft werden, wobei ein dem positiven Pol einer Brückenschaltung zugeordneter Leistungsschalter nur dann gesetzt werden kann, wenn das Signal "H" den logischen Pegel "LOW" aufweist und ein dem negativen Pol der Brückenschaltung zugeordneter Leistungsschalter nur dann gesetzt werden kann, wenn das Signal "H" den logischen Pegel "HIGH" aufweist.To achieve that the circuit breakers of a bridge branch in a bridge circuit are switched after every second period of the reference voltage, it is provided that the drive pulses generated by the comparators with a digital signal "H" half frequency of the reference voltage are logically AND-linked, one of which only then positive circuit breaker assigned to a bridge circuit can be set can if the signal "H" has the logic level "LOW" and a negative pole the circuit breaker associated circuit breaker can only be set if that Signal "H" has the logic level "HIGH".

Insgesamt werden die Leistungsschalter mit einer Frequenz angesteuert, die der Hälfte der Frequenz der Vergleichsspannung entspricht. Auf diese Weise können die Schaltverluste reduziert werden. Auch ergeben sich Vorteile bezüglich der durch die Schaltvorgänge erzeug­ ten Oberwellen.Overall, the circuit breakers are controlled with a frequency that is half the Frequency corresponds to the reference voltage. In this way, the switching losses be reduced. There are also advantages with regard to those generated by the switching operations th harmonics.

Um Schaltaussetzer bei hohen, d. h. die Vergleichsspannung überschreitenden Steuerspannun­ gen zu verhindern, wird bei einem vorgebbaren minimalen Zählerstand ein logisches Signal "MIN" erzeugt, dass mit den Ansteuersignalen logisch UND-verknüpft wird und bei einem vorgebbaren maximalen Zählerstand ein logisches Signal "MAX" erzeugt, das mit den An­ steuersignalen ODER-verknüpft wird.To avoid misfires at high, d. H. control voltage exceeding the reference voltage a logical signal at a predeterminable minimum counter reading "MIN" generates that the control signals are logically AND-linked and at one Predeterminable maximum counter reading generates a logical signal "MAX", which with the An control signals OR-linked.

Weitere Einzelheiten, Vorteile und Merkmale der Erfindung ergeben sich nicht nur aus den Ansprüchen, den diesen zu entnehmenden Merkmalen - für sich und/oder in Kombination -, sondern auch aus der nachfolgenden Beschreibung eines den Zeichnungen zu entnehmenden bevorzugten Ausführungsbeispiels. Further details, advantages and features of the invention result not only from the Claims, the features to be extracted from these - individually and / or in combination -, but also from the following description of one of the drawings preferred embodiment.  

Es zeigen:Show it:

Fig. 1 einen Wechselrichter mit zugehörigem Regelkreis, Fig. 1 is an inverter with an associated control circuit,

Fig. 2 ein Blockschaltbild einer PWM-Steuerung und Fig. 2 is a block diagram of a PWM controller and

Fig. 3 Signalverläufe von logischen Signalen der PWM-Steuerung gemäß Fig. 2. Fig. 3 waveforms of logic signals of the PWM control in accordance with FIG. 2.

In Fig. 1 ist eine Schaltungsanordnung 10 zum Betreiben eines Wechselrichters 12 mit nachgeschaltetem Transformator 14 dargestellt.In Fig. 1, a circuit arrangement 10 is shown for the operation of an inverter 12 having a downstream transformer 14.

Der Wechselrichter 12 ist in dem hier dargestellten Ausführungsbeispiel als Brückenschaltung ausgebildet und weist einen ersten Brückenzweig 16 mit Leistungsschaltern T1, T2 und einen zweiten Brückenzweig 18 mit Leistungsschaltern T3, T4 auf. Die Leistungsschalter T1-T4 sind als NPN-Transistoren wie z. B. FET's oder IGBT's ausgebildet, wobei die Leistungs­ schalter T1, T3 mit ihrem Kollektor an einem positiven Pol 20 einer die Eingangsspannung UE liefernden Spannungsquelle und die Leistungsschalter T2, T4 jeweils mit ihrem Emitter­ anschluss mit einem negativen Pol 22 der Spannungsquelle verbunden sind. Parallel zu den Leistungsschaltern T1-T4 ist jeweils eine Freilaufdiode 24, 26, 28, 30 bezogen auf die Leitstrecke der Transistoren T1-T4 antiparallel geschaltet. Ferner weisen die Leistungs­ schalter T1-T4 Steuereingänge 32, 34, 36, 38 auf, die mit Ausgängen einer PWM-Steuerung 40 verbunden sind.In the exemplary embodiment shown here, the inverter 12 is designed as a bridge circuit and has a first bridge branch 16 with circuit breakers T1, T2 and a second bridge branch 18 with circuit breakers T3, T4. The circuit breakers T1-T4 are as NPN transistors such. B. FET's or IGBT's are formed, the power switches T1, T3 with their collector on a positive pole 20 of an input voltage U E supplying voltage source and the power switches T2, T4 each having their emitter connection with a negative pole 22 of the voltage source. In parallel with the circuit breakers T1-T4, a free-wheeling diode 24 , 26 , 28 , 30 is connected antiparallel with respect to the routing of the transistors T1-T4. Furthermore, the power switches T1-T4 have control inputs 32 , 34 , 36 , 38 , which are connected to outputs of a PWM controller 40 .

Zur Glättung der Eingangsspannung UE ist zwischen dem positiven Pol 20 und dem negativen Pol 22 der Spannungsquelle ein Kondensator 42 angeordnet.A capacitor 42 is arranged between the positive pole 20 and the negative pole 22 of the voltage source to smooth the input voltage U E.

Eine Mittelanzapfung 44 zwischen dem Leistungsschalter T1 und dem Leistungsschalter T2 bildet einen ersten Ausgang des Wechselrichters 12, der über eine Drosselspule 46 mit einem ersten Anschluss 48 einer Primärwicklung 50 des Transformators 14 verbunden ist. Eine Mittelanzapfung 52 zwischen dem Leistungsschalter T3 und dem Leistungsschalter T4 bildet einen zweiten Ausgang des Wechselrichters 12, der über eine zweite Drosselspule 54 mit einem zweiten Anschluss 56 der Primärwicklung 50 des Transformators 14 verbunden ist. Zur Erfassung des durch die Primärwicklung 50 fließenden Primärstroms IP ist ein Messelement 58 vorgesehen.A center tap 44 between the circuit breaker T1 and the circuit breaker T2 forms a first output of the inverter 12 , which is connected via a choke coil 46 to a first connection 48 of a primary winding 50 of the transformer 14 . A center tap 52 between the circuit breaker T3 and the circuit breaker T4 forms a second output of the inverter 12 , which is connected via a second choke coil 54 to a second connection 56 of the primary winding 50 of the transformer 14 . A measuring element 58 is provided to detect the primary current I P flowing through the primary winding 50 .

Der Transformator 14 weist in dem hier dargestellten Ausführungsbeispiel zwei Sekundär­ wicklungen 60, 62 auf, die über eine Verbindung 64 zu einer einzigen Sekundärwicklung verbunden sind. Es kann auch eine einzige Sekundärwicklung vorgesehen sein. Ein erster An­ schluss 66 der Sekundärwicklung 60 bildet einen ersten Pol 68 und ein weiterer Anschluss 70 der Senkundärwicklung 62 bildet einen zweiten Pol 72 der Ausgangsspannung UA. Parallel zu der Reihenschaltung aus Senkundärwicklung 60 und Senkundärwicklung 62 ist ein Kon­ densator 74 angeordnet, der zusammen mit den Drosselspulen 46, 54 einen Filter bildet. Zur Erfassung des Senkundärstroms IS ist ein Messelement 76 vorgesehen.In the exemplary embodiment shown here, the transformer 14 has two secondary windings 60 , 62 which are connected via a connection 64 to a single secondary winding. A single secondary winding can also be provided. A first connection 66 of the secondary winding 60 forms a first pole 68 and a further connection 70 of the secondary winding 62 forms a second pole 72 of the output voltage U A. In parallel to the series connection of secondary winding 60 and secondary winding 62 , a capacitor 74 is arranged, which together with the choke coils 46 , 54 forms a filter. A measuring element 76 is provided to detect the secondary current I S.

Die Schaltungsanordnung 10 zum Betreiben des Wechselrichters 12 mit zugeordnetem Trans­ formator 14 besteht aus einem Regelkreis 78 und der oben erwähnten PWM-Steuerung 40. Erfindungsgemäß weist der Regelkreis 78 eine überlagerte Spannungsregeleinrichtung 80 auf, die aus einem Vergleicher 82 und einem Spannungsregler 84 besteht. Dem Vergleicher 82 wird ein Ausgangsspannungs-Soll-Wert UASOLL sowie ein Ausgangsspannungs-Ist-Wert UAIST zugeführt. Ferner ist der Vergleicher 82 mit dem Ausgang einer Stromregeleinrichtung 86 verbunden, in der aus dem gemessenen Primärstrom-Ist-Wert IPIST und Sekundärstrom-Ist- Wert ISIST eine Regeldifferenz als Störgröße ermittelt wird. Die Stromregeleinrichtung 86 besteht aus einem mit den Messelementen 58 und 76 verbundenen zweiten Vergleicher 88 und einem Stromregler 90.The circuit arrangement 10 for operating the inverter 12 with an associated transformer 14 consists of a control circuit 78 and the above-mentioned PWM controller 40 . According to the invention, the control circuit 78 has a superimposed voltage control device 80 , which consists of a comparator 82 and a voltage regulator 84 . An output voltage setpoint value U ASOLL and an actual output voltage value U AIST are fed to the comparator 82 . Furthermore, the comparator 82 is connected to the output of a current control device 86 , in which a control difference is determined as a disturbance variable from the measured primary current actual value I PIST and secondary current actual value I SIST . The current control device 86 consists of a second comparator 88 connected to the measuring elements 58 and 76 and a current controller 90 .

Ein Ausgang 92 des Spannungsreglers 84 ist über ein Rückkoppelglied 94 mit dem Ver­ gleicher 82 verbunden. Dadurch wird eine Begrenzung eines am Ausgang anliegenden Ausgangssignals, das einen Soll-Wert für den Primärstrom IP bildet, begrenzt.An output 92 of the voltage regulator 84 is connected via a feedback element 94 to the comparator 82 . This limits the limitation of an output signal present at the output, which forms a target value for the primary current I P.

Der überlagerten Spannungsregeleinrichtung 80 ist eine unterlagerte Stromregeleinrichtung 96 nachgeschaltet, die aus einem Vergleicher 98 und einem Stromregler 100 besteht. Der Ver­ gleicher 98 ist mit dem Ausgang 92 des Spannungsreglers 84 verbunden. Ferner wird dem Vergleicher 98 der Primärstrom-Ist-Wert IPIST zugeführt. Der Ausgang des Stromreglers 100 ist über ein Rückkoppelglied 102, das vorzugsweise als Filter zur Resonanzdämpfung ausgebildet ist, mit dem Vergleicher 98 und mit einem Steuereingang der PWM-Steuerung 40 verbunden.The superimposed voltage control device 80 is followed by a subordinate current control device 96 , which consists of a comparator 98 and a current controller 100 . The comparator 98 is connected to the output 92 of the voltage regulator 84 . Furthermore, the primary current actual value I PIST is fed to the comparator 98 . The output of the current regulator 100 is connected to the comparator 98 and to a control input of the PWM controller 40 via a feedback element 102 , which is preferably designed as a filter for resonance damping.

Die beschriebene Schaltungsanordnung 10 zeichnet sich durch die Messelemente 58, 76 zur Erfassung des Primärstroms IP und des Sekundärstroms IS aus, wobei aus den ermittelten Messgrößen eine Regelabweichung berechnet und im Stromregler 90 verstärkt wird, die dem Vergleicher 88 als Störgrößenaufschaltung zugeführt wird. Die auf diese Art ermittelte Störgröße ist ein Maß für die unsymmetrische Auslastung des Transformators 14. Zusammen mit dem Ausgangsspannungs-Soll-Wert UASOLL und dem Ausgangsspannungs-Ist-Wert UAIST wird eine Regelabweichung zur Verfügung gestellt, die von dem Spannungsregler 84 verstärkt wird. Damit die verstärkte Regeldifferenz einen bestimmten Wert nicht überschreitet, ist die Begrenzung 94 in Form eines Rückkoppelgliedes vorgesehen. Der Wert der Begrenzung kann vorzugsweise eingestellt werden. Die so ermittelte Größe IPSOLL dient als Soll-Wert für den Primärstrom IP und wird in dem Vergleicher 98 mit dem Primärstrom-Ist-Wert IPIST Zur Bildung einer Regeldifferenz verknüpft. Die so gebildete Regeldifferenz wird dem Stromreg­ ler 100 zur Verstärkung zugeführt und zur Regelkreisstabilisierung über den Filter 102 auf den Vergleicher 98 zurückgeführt. Am Ausgang 101 des Stromreglers 100 ist eine im wesent­ lichen sinusförmige Steuerspannung als PWM-Steuersignal abgreifbar.The circuit arrangement 10 described is characterized by the measuring elements 58 , 76 for detecting the primary current I P and the secondary current I S , a control deviation being calculated from the measured variables determined and amplified in the current controller 90 , which is fed to the comparator 88 as a disturbance variable application. The disturbance variable determined in this way is a measure of the asymmetrical utilization of the transformer 14 . Together with the output voltage target value U ASOLL and the output voltage actual value U AIST , a control deviation is made available, which is amplified by the voltage regulator 84 . So that the amplified control difference does not exceed a certain value, the limit 94 is provided in the form of a feedback element. The value of the limitation can preferably be set. The quantity I PSOLL determined in this way serves as the target value for the primary current I P and is linked in the comparator 98 with the primary current actual value I PIST in order to form a control difference. The control difference thus formed is fed to the Stromreg controller 100 for amplification and fed back to the comparator 98 via the filter 102 for stabilizing the control loop. At the output 101 of the current regulator 100 , a sinusoidal control voltage can be tapped as a PWM control signal.

Die am Ausgang 101 der Regeleinrichtung 96 anliegende Steuerspannung kann mit unsym­ metrischen Schwankungen behaftet sein. Bei herkömmlichen PWM-Steuerungen führen diese Spannungsschwankungen dazu, dass die Leistungsschalter T1-T4 fehlerhaft bzw. nicht ange­ steuert werden. Dies führt zu unerwünschten Netzrückwirkungen und verschlechtert den Wir­ kungsgrad des Wechselrichters.The control voltage applied to the output 101 of the control device 96 can be subject to asymmetrical fluctuations. In conventional PWM controls, these voltage fluctuations cause the circuit breakers T1-T4 to be activated incorrectly or not. This leads to undesirable grid repercussions and deteriorates the efficiency of the inverter.

Daher wird erfindungsgemäß eine PWM-Steuerung 40 mit symmetrischer Pulsweitenmodula­ tion vorgeschlagen. Der Aufbau der erfindungsgemäßen PWM-Steuerung 40 wird anhand von Fig. 2 näher erläutert. A PWM controller 40 with symmetrical pulse width modulation is therefore proposed according to the invention. The structure of the PWM controller 40 according to the invention is explained in more detail with reference to FIG. 2.

Die PWM-Steuerung 40 umfasst im wesentlichen einen ersten Komparator 104, einen zweiten Komparator 106, einer Ansteuereinheit 108 für die Leistungsschalter T1 und T2, eine An­ steuereinheit 110 für die Leistungsschalter T3 und T4, einen Spannungsgenerator 112 zur Erzeugung einer Vergleichsspannung sowie eine Signalgeberschaltung 114 mit zugehörigem Taktgenerator 116.The PWM controller 40 essentially comprises a first comparator 104 , a second comparator 106 , a control unit 108 for the circuit breakers T1 and T2, a control unit 110 for the circuit breakers T3 and T4, a voltage generator 112 for generating a comparison voltage, and a signal generator circuit 114 with associated clock generator 116 .

Ein positiver Eingang 118 des ersten Komparators 104 bildet den Eingang der PWM-Steue­ rung 40 und ist unmittelbar mit dem Ausgang 101 verbunden, an dem die Steuerspannung USTEUER anliegt. Ein positiver Eingang 120 des zweiten Komparators 106 ist über eine Inver­ terschaltung 122 mit der Steuerspannung verbunden, so dass an dem Eingang 120 die invertierte Steuerspannung /USTEUER anliegt (/wird im folgenden als Negationszeichen verwendet). Ein Ausgang 123 des Spannungsgenerators 112 liegt über einem Kondensator 124 zur Tiefpassfilterung jeweils an einem negativen Eingang 126, 128 der Komperatoren 104, 106. Des Weiteren ist zur Tiefpassfilterung ein Widerstand 130 vorgesehen, der die negativen Eingänge 126, 128 mit Massepotential verbindet. Zum Setzen und Rücksetzen einer generierten Sägezahnspannung ist der Spannungsgenerator 112 mit einem Ausgang 132 der Zählschaltung 114 verbunden.A positive input 118 of the first comparator 104 forms the input of the PWM controller 40 and is directly connected to the output 101 , at which the control voltage U CONTROL is applied. A positive input 120 of the second comparator 106 is connected to the control voltage via an inverter circuit 122 , so that the inverted control voltage / U CONTROL is present at the input 120 (/ is used in the following as a negative sign ). An output 123 of the voltage generator 112 is connected to a negative input 126 , 128 of the comparators 104 , 106 via a capacitor 124 for low-pass filtering. Furthermore, a resistor 130 is provided for low-pass filtering, which connects the negative inputs 126 , 128 to ground potential. To set and reset a generated sawtooth voltage, the voltage generator 112 is connected to an output 132 of the counter circuit 114 .

Die Komparatoren 104, 106 weisen jeweils einen Ausgang 134, 136 auf, der über jeweils ein Invertergatter 138, 140 mit einem Eingang 142, 144 eines Und-Gatters 146, 148 verbunden ist. Ein weiterer Eingang 150, 152 des Und-Gatters 146, 148 ist mit einem Ausgang 154 der Signalgeberschaltung 114 verbunden. An dem Ausgang 154 liegt ein digitales Signal "MIN" an, das einen Pegel "HIGH" annimmt, wenn ein in die Signalgeberschaltung integrierter Zähler einen Mindestwert überschritten hat. Ein Ausgang 156, 158 des Und-Gatters 146, 148 ist mit einem Eingang 160, 162 eines Oder-Gatters 164, 166 verbunden. Ein weiterer Eingang 168, 170 des Oder-Gatters 164, 166 ist mit einem Ausgang 172 der Signalgeberschaltung ver­ bunden, an dem ein digitales Signal "MAX" anliegt, das dann den Pegel "HIGH" einnimmt, wenn ein bestimmter maximaler Zählerstand errreicht ist. Das Signal "MAX" wird am Ende einer Periode der Vergleichsspannung zurückgesetzt.The comparators 104 , 106 each have an output 134 , 136 , which is connected via an inverter gate 138 , 140 to an input 142 , 144 of an AND gate 146 , 148 . Another input 150 , 152 of the AND gate 146 , 148 is connected to an output 154 of the signal generator circuit 114 . A digital signal "MIN" is present at output 154 , which assumes a "HIGH" level when a counter integrated in the signal transmitter circuit has exceeded a minimum value. An output 156 , 158 of the AND gate 146 , 148 is connected to an input 160 , 162 of an OR gate 164 , 166 . Another input 168 , 170 of the OR gate 164 , 166 is connected to an output 172 of the signal generator circuit, to which a digital signal "MAX" is present, which then assumes the level "HIGH" when a certain maximum counter reading has been reached. The signal "MAX" is reset at the end of a period of the reference voltage.

Ein Ausgang 174 des Oder-Gatters 164 ist mit einem Eingang 176 eines Und-Gatters 178 verbunden, dessen Ausgang mit einem Rücksetzeingang 180 der Ansteuereinheit 108 für die Leistungsschalter T1 und T2 verbunden ist. Ein weiterer Eingang 182 des Und-Gatters 178 ist mit einem Ausgang 184 verbunden, an dem ein digitales Signal "H" anliegt, das die halbe Frequenz der Vergleichssägezahnspannung aufweist. Des Weiteren ist der Ausgang 174 des Oder-Gatters 164 mit einem Eingang 186 eines Und-Gatters 188 verbunden, dessen Ausgang mit dem Rücksetzeingang 190 der Ansteuereinheit 110 für die Leistungsschalter T3 und T4 verbunden ist.An output 174 of the OR gate 164 is connected to an input 176 of an AND gate 178 , the output of which is connected to a reset input 180 of the control unit 108 for the circuit breakers T1 and T2. Another input 182 of the AND gate 178 is connected to an output 184 , to which a digital signal "H" is present, which has half the frequency of the comparative sawtooth voltage. Furthermore, the output 174 of the OR gate 164 is connected to an input 186 of an AND gate 188 , the output of which is connected to the reset input 190 of the control unit 110 for the circuit breakers T3 and T4.

Ein Ausgang 192 des Oder-Gatters 166 ist einerseits mit einem Eingang 194 eines Und- Gatters 196 verbunden, dessen Ausgang mit einem Rücksetzeingang 198 der Ansteuerschal­ tung 110 verbunden ist. Andererseits liegt der Ausgang 192 des Oder-Gatters 166 an einem Eingang 200 eines Und-Gatters 202, dessen Ausgang mit einem Setzeingang 204 der An­ steuereinheit 108 für die Leistungsschalter T1 und T2 verbunden ist. Ein weiterer Eingang 206 des Und-Gatters 202 ist über einen Inverter 208 mit dem Ausgang 184 verbunden. Gleiches gilt für einen Ausgang 210 des Und-Gatters 188, der über einen Inverter 212 mit dem Ausgang 184 verbunden ist. Ferner ist ein Eingang 214 des Und-Gatters 196 mit dem Ausgang 184 verbunden.An output 192 of the OR gate 166 is connected on the one hand to an input 194 of an AND gate 196 , the output of which is connected to a reset input 198 of the control circuit 110 . On the other hand, the output 192 of the OR gate 166 is connected to an input 200 of an AND gate 202 , the output of which is connected to a set input 204 of the control unit 108 for the circuit breakers T1 and T2. Another input 206 of the AND gate 202 is connected to the output 184 via an inverter 208 . The same applies to an output 210 of the AND gate 188 , which is connected to the output 184 via an inverter 212 . Furthermore, an input 214 of the AND gate 196 is connected to the output 184 .

Die Funktionsweise der PWM-Steuerung 40 gemäß Fig. 2 soll unter Bezugnahme auf die in Fig. 3 dargestellten Signalverläufe erläutert werden.The mode of operation of the PWM controller 40 according to FIG. 2 will be explained with reference to the signal profiles shown in FIG. 3.

In Fig. 3a ist der Verlauf des Signals "H" dargestellt, das an dem Ausgang 184 der Signal­ schaltung 114 abgreifbar ist. In dem hier dargestellten Ausführungsbeispiel ist die Signal­ schaltung 114 als 8-Bit-Zähler ausgebildet, wobei das Signal "H" den Pegel des Bits mit der höchsten Wertigkeit darstellt.In Fig. 3a, the course of the signal "H" is shown, which can be tapped at the output 184 of the signal circuit 114 . In the embodiment shown here, the signal circuit 114 is designed as an 8-bit counter, the signal "H" representing the level of the bit with the highest significance.

In Fig. 3b ist einerseits der Verlauf der sägezahnförmigen Vergleichsspannung UVERGL und andererseits sind die Verläufe von Steuerspannung USTEUER und der inversen Steuerspannung /USTEUER dargestellt. FIG. 3b shows on the one hand the course of the sawtooth-shaped comparison voltage U VERGL and on the other hand the courses of the control voltage U CONTROL and the inverse control voltage / U CONTROL .

Übersteigt der Wert der Vergleichsspannung UVERGL den Wert der Steuerspannung USTEUER, ändert sich der Ausgangspegel am Ausgang des ersten Komparators 104, der von dem Inverter 138 invertiert wird. Ein entsprechender Signalverlauf /KOMP1 ist in Fig. 3c darge­ stellt.If the value of the comparison voltage U VERGL exceeds the value of the control voltage U CONTROL , the output level at the output of the first comparator 104 changes , which is inverted by the inverter 138 . A corresponding signal curve / KOMP1 is shown in Fig. 3c Darge.

Überschreitet die Vergleichsspannung UVERGL die inverse Steuerspannung /USTEUER, so ändert sich das Ausgangssignal des zweiten Komparators 106, das ebenfalls durch den Inverter 140 invertiert wird und als Signal /KOMP 2 in Fig. 3d dargestellt ist.If the comparison voltage U VERGL exceeds the inverse control voltage / U CONTROL , the output signal of the second comparator 106 changes , which is also inverted by the inverter 140 and is shown as the signal / COMP 2 in FIG. 3d.

Die Signale /KOMP1 und /KOMP2 dienen zur symmetrischen Ansteuerung der Leistungs­ schalter T1-T4 des Wechselrichters 12. Dabei ist vorgesehen, dass eine ansteigende Flanke des Signals /KOMP1 einen ersten Umschaltvorgang in dem Brückenzweig 16 mit den Lei­ stungsschaltern T1 und T2 auslöst und dass eine ansteigende Flanke des Signals /KOMP2 einen zweiten Umschaltvorgang der Leistungsschalter T1 und T2 in dem Brückenzweig 16 auslöst. Um zu erreichen, dass bei einer Vollbrückenschaltung ein Umschaltvorgang eines Brückenzweiges bei jeder zweiten Periode der Vergleichsspannung UWRGL erzeugt wird, ist vorgesehen, dass die Signale /KOMP1 und /KOMP2 mit dem Signal "H" logisch verknüpft werden. So wird z. B. ein Ausschaltvorgang des Leistungsschalters T 1 des Brückenzweigs 16 nur dann eingeleitet, wenn bei ansteigender Flanke des Signals /KOMP1 das Signal "H" den logischen Pegel "HIGH" aufweist. In einer folgenden Periode erfolgt ein Umschaltvorgang in den Leistungsschalter T3, T4 des Brückenzweigs 18, wobei bei einer ansteigenden Flanke des Signals /KOMP1 und bei einem logischen Pegel "LOW" des Signals "H" ein Einschalt­ vorgang des Leitungsschalters T4 eingeleitet wird.The signals / KOMP1 and / KOMP2 serve for the symmetrical control of the circuit breakers T1-T4 of the inverter 12 . It is provided that a rising edge of the signal / KOMP1 triggers a first switching process in the bridge branch 16 with the circuit breakers T1 and T2 and that a rising edge of the signal / KOMP2 triggers a second switching process of the circuit breakers T1 and T2 in the bridge branch 16 . In order to ensure that a switching operation of a bridge arm is generated every other period of the comparison voltage UWRGL in a full bridge circuit, it is provided that the signals / KOMP1 and / KOMP2 are logically combined with the signal "H". So z. B. initiated a turn-off of the circuit breaker T 1 of the bridge branch 16 only when the signal "H" has the logic level "HIGH" on a rising edge of the signal / KOMP1. In a subsequent period, a switchover occurs in the circuit breaker T3, T4 of the bridge branch 18 , with a switch-on operation of the line switch T4 being initiated on a rising edge of the signal / KOMP1 and at a logic level "LOW" of the signal "H".

Dieses Ansteuerverfahren zeichnet sich besonders dadurch aus, dass beide Flanken der Umschaltvorgänge der Leistungsschalter eines Brückenzweiges durch Veränderung der Steuerspannung USTEUER im wesentlichen symmetrisch bezogen auf eine abfallende Flanke der sägezahnförmigen Vergleichsspannung variiert werden. Dieser Effekt kann insbesondere bei hohen Steuerspannungen ausgenutzt werden.This control method is characterized in particular by the fact that both edges of the switching operations of the circuit breakers of a bridge arm are varied essentially symmetrically with respect to a falling edge of the sawtooth-shaped reference voltage by changing the control voltage U CONTROL . This effect can be exploited in particular at high control voltages.

Überschreitet die Steuerspannung USTEUER zum Beispiel den maximalen Wert der Vergleichs­ spannung UVERGL, werden von den Komperatoren 104 bzw. 106 keine Signale erzeugt, so dass eine Ansteuerung der Leistungsschalter nicht erfolgt, was zu Pulsaussetzern führt.If the control voltage U CONTROL exceeds, for example, the maximum value of the comparison voltage U COMP , no signals are generated by the comparators 104 or 106 , so that the circuit breakers are not activated, which leads to pulse dropouts.

Um derartige Pulsaussetzer beim Überschreiten der Steuerspannung über den Wert der Vergleichsspannung zu verhindern, wird kurz vor dem Rücksetzen der Vergleichsspannung ein digitales Signal "MAX" gemäß Fig. 3e erzeugt. Des Weiteren wird kurz nach dem Setzen der Vergleichsspannung ein digitales Signal "MIN" erzeugt. Dabei ist vorgesehen, dass das digitale Signal "MIN" jeweils mit den Signalen /KOMP1 und /KOMP2 über ein logisches UND-Gatter 146, 148 verknüpft wird. Ein am Ausgang des UND-Gatters 146, 148 liegendes Signal wird sodann mit dem digitalen Signal "MAX" logisch ODER-verknpüft, so dass auf diese Art und Weise sichergestellt ist, dass ein erster Umschaltvorgang in einem Brücken­ zweig dann eingeleitet wird, wenn entweder das Signal /KOMP1 oder das Signal "MAX" eine aufsteigende Flanke erzeugen.In order to prevent such pulse misfires when the control voltage exceeds the value of the comparison voltage, a digital signal "MAX" according to FIG. 3e is generated shortly before the comparison voltage is reset. Furthermore, a digital signal "MIN" is generated shortly after the comparison voltage is set. It is provided that the digital signal "MIN" is combined with the signals / KOMP1 and / KOMP2 via a logical AND gate 146 , 148 . A signal at the output of the AND gate 146 , 148 is then logically OR-linked with the digital signal "MAX", so that it is ensured in this way that a first switching operation in a bridge branch is initiated when either the signal / KOMP1 or the signal "MAX" generate a rising edge.

Der zweite Umschaltvorgang wird sodann von der ansteigenden Flanke des Signals "MIN" übernommen, wobei das Signal "MIN" mit dem Signal /KOMP2 logisch UND-verknüpft wird.The second switching process is then triggered by the rising edge of the "MIN" signal. taken over, whereby the signal "MIN" with the signal / KOMP2 logically AND-linked becomes.

Dadurch ist eine Mindestimpulsbreite festgelegt, die einerseits über die Impulsbreite des Signals "MAX" und andererseits über die Impulsbreite des Signals "MIN" definiert ist. Durch logische Verknüpfung mit dem Signal "H" wird eine Auswahl getroffen, welcher Brücken­ zweig zu schalten ist.As a result, a minimum pulse width is defined, which is on the one hand over the pulse width of the Signal "MAX" and the other hand is defined by the pulse width of the signal "MIN". By Logical connection with the signal "H" makes a selection of which bridges to switch branch.

Die Dauer der Signale "MIN" und "MAX" werden wie folgt festgelegt: Da es sich bei der Signalgeberschaltung 114 um einen 8-Bit-Zähler handelt, verbleibt das Signal "H" während der Zählimpulse 0-126 auf dem logischen Pegel "LOW" und während der Zählimpulse 127-­ 256 auf dem logischen Pegel "HIGH". Ferner ist vorgesehen, dass bei dem Zählerstand 126 am Ausgang 132 ein Entladesignal gesetzt wird, das bei dem Zählerstand 1 wieder zurückge­ setzt wird, so dass die aufsteigende Rampe der Vergleichsspannung erzeugt wird. Das Signal "MIN" wird während der Zählerstände 2-4 von dem logischen Pegel "HIGH" auf den logischen Pegel "LOW" geschaltet. Andererseits wird das Signal "MAX" während der Zählerstände 123-125 auf den logischen Pegel "HIGH" geschaltet.The duration of the signals "MIN" and "MAX" are determined as follows: Since the signal generator circuit 114 is an 8-bit counter, the signal "H" remains at the logic level "LOW" during the counting pulses 0-126 "and during the counts 127-256 at the logic level" HIGH ". It is further provided that a discharge signal is set at the counter reading 126 at the output 132 , which is reset again at the counter reading 1, so that the ascending ramp of the reference voltage is generated. The signal "MIN" is switched from the logic level "HIGH" to the logic level "LOW" during the counts 2-4. On the other hand, the signal "MAX" is switched to the logic level "HIGH" during the counter readings 123-125 .

Insgesamt dienen die Signale "MIN" und "MAX" dazu, die Pulsweitenmodulation in ihrer minimalen und maximalen Ansteuerung zu begrenzen. Insgesamt wird durch die erfindungs­ gemäße PWM-Steuerung eine symmetrische Pulsweitenmodulation für einen Wechselrichter zur Verfügung gestellt, wodurch insbesondere beim Einschaltverhalten und im Leerlauffall das Regelverhalten der Schaltungsanordnung zum Betreiben des Wechselrichtes verbessert wird.Overall, the signals "MIN" and "MAX" serve to change the pulse width modulation in their limit minimum and maximum control. Overall, the invention PWM control according to a symmetrical pulse width modulation for an inverter provided, which makes it particularly useful when switching on and when idling improves the control behavior of the circuit arrangement for operating the inverter becomes.

Claims (21)

1. Schaltungsanordnung (10) zum Betreiben eines ein- oder mehrphasigen Wechselrich­ ters (12), dessen Wechselspannungsausgang mit einer einen Primärstrom IP führenden Primärwicklung (15) eines Transformators (14) verbunden ist, wobei an zumindest einer einen Sekundärstrom IS führenden Sekundärwicklung (60, 62) des Transforma­ tors (14) eine Last anschließbar ist, umfassend einen Regelkreis (78) und eine An­ steuereinheit (40) zur Pulsansteuerung von Leistungshalbleitern T1-T4 des Wechsel­ richters (12), dadurch gekennzeichnet, dass ein erstes Messelement (58) zur Erfassung des Primärstromes IP und ein zweites Messelement zur Erfassung des Sekundärstroms IS vorgesehen ist, dass eine Regeldif­ ferenz aus Primärstrom IP und Sekundärstrom IS einer überlagerten Spannungsregel­ einrichtung (80) zugeführt wird, dass ein Ausgang (92) der Spannungsregeleinrichtung (80) mit einem Vergleicher (98) einer unterlagerten Stromregeleinrichtung (96) verbunden ist, dass dem Vergleicher (98) der Primärstrom IP als Strom-Istwert IPIST zugeführt wird und dass ein Ausgang (101) der Stromregeleinrichtung (96) mit einem Eingang der Ansteuereinheit (40) verbunden ist. 1. Circuit arrangement ( 10 ) for operating a single-phase or multi-phase inverter ( 12 ), the AC voltage output of which is connected to a primary winding ( 15 ) carrying a primary current I P of a transformer ( 14 ), with at least one secondary winding carrying a secondary current I S ( 60 , 62 ) of the transformer ( 14 ) a load can be connected, comprising a control circuit ( 78 ) and a control unit ( 40 ) for pulse control of power semiconductors T1-T4 of the inverter ( 12 ), characterized in that a first measuring element ( 58 ) for detecting the primary current I P and a second measuring element for detecting the secondary current I S is provided that a control difference of primary current I P and secondary current I S is fed to a superimposed voltage control device ( 80 ) that an output ( 92 ) the voltage regulating device ( 80 ) is connected to a comparator ( 98 ) of a subordinate current regulating device ( 96 ) n is that the primary current I P is supplied to the comparator ( 98 ) as the actual current value I PIST and that an output ( 101 ) of the current control device ( 96 ) is connected to an input of the control unit ( 40 ). 2. Schaltungsanordnung (10) zum Betreiben eines ein- oder mehrphasigen Wechselrich­ ters (12), dessen Wechselspannungsausgang mit einer einen Primärstrom IP führenden Primärwicklung (15) eines Transformators (14) verbunden ist, wobei an zumindest einer einen Sekundärstrom IS führenden Sekundärwicklung (60, 62) des Transforma­ tors (14) eine Last anschließbar ist, umfassend einen Regelkreis (78) und eine An­ steuereinheit (40) zur Pulsansteuerung von Leistungshalbleitern T1-T4 des Wechsel­ richters (12), dadurch gekennzeichnet, dass ein erstes Messelement (58) zur Erfassung des Primärstromes IP und ein zweites Messelement zur Erfassung des Sekundärstroms IS vorgesehen ist, dass eine Regeldif­ ferenz aus Primärstrom IP und Sekundärstrom IS einer überlagerten Spannungsregel­ einrichtung (80) zugeführt wird, dass eine Ausgangsgröße der Spannungsregeleinrich­ tung (80) einer unterlagerten Stromregeleinrichtung (96) zugeführt und mit dem Primärstrom IP als Strom-Istwert IPIST zur Anpassung an dessen Kurvenform ver­ glichen wird, wobei beliebige Phasenwinkel ϕ und Kurvenformen des Ausgangsstro­ mes bzw. Sekundärstromes IS zur Ausgangsspannung UA regelbar sind und dass ein Ausgang (101) der Stromregeleinrichtung (96) mit einem Eingang der Ansteuereinheit (40) verbunden ist.2. Circuit arrangement ( 10 ) for operating a single-phase or multi-phase inverter ( 12 ), the AC voltage output of which is connected to a primary winding ( 15 ) carrying a primary current I P of a transformer ( 14 ), with at least one secondary winding carrying a secondary current I S ( 60 , 62 ) of the transformer ( 14 ) a load can be connected, comprising a control circuit ( 78 ) and a control unit ( 40 ) for pulse control of power semiconductors T1-T4 of the inverter ( 12 ), characterized in that a first measuring element ( 58 ) for detecting the primary current I P and a second measuring element for detecting the secondary current I S is provided that a control difference of primary current I P and secondary current I S is fed to a superimposed voltage control device ( 80 ) that an output variable of the voltage control device ( 80 ) a subordinate current control device ( 96 ) and supplied with the primary current I P is compared as actual current value I PIST for adaptation to its curve shape, any phase angle ϕ and curve shapes of the output current or secondary current I S to the output voltage U A being controllable and that an output ( 101 ) of the current control device ( 96 ) with an input of the control unit ( 40 ) is connected. 3. Schaltungsanordnung nach Anspruch 1 oder 2 dadurch gekennzeichnet, dass die Messelemente (58, 76) über eine zweite Stromregeleinrichtung (86) mit einem Vergleicher (82) der Spannungsregeleinrichtung verbunden sind.3. Circuit arrangement according to claim 1 or 2, characterized in that the measuring elements ( 58 , 76 ) are connected via a second current control device ( 86 ) to a comparator ( 82 ) of the voltage control device. 4. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der Spannungsregler (84) zur Begrenzung seines Ausgangssignals ein Rückkop­ pelglied (94) aufweist, dessen Eingang mit dem Ausgang (92) des Spannungsreglers (84) und dessen Ausgang mit dem ersten Vergleicher (82) verbunden ist. 4. Circuit arrangement according to one of the preceding claims, characterized in that the voltage regulator ( 84 ) to limit its output signal has a Rückkop pellied ( 94 ), whose input with the output ( 92 ) of the voltage regulator ( 84 ) and whose output with the first comparator ( 82 ) is connected. 5. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass dem Stromregler (100) zur Resonanzdämpfung ein Rückkoppelglied (102), vor­ zugsweise ein aktives Filter wie z. B. ein LC-Filter, zugeordnet ist.5. Circuit arrangement according to one of the preceding claims, characterized in that the current regulator ( 100 ) for resonance damping a feedback element ( 102 ), preferably before an active filter such. B. an LC filter is assigned. 6. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Messelemente (58, 76) zur Erfassung der Ströme IP und IS mit Eingängen eines zweiten Vergleichers (88) verbunden sind und dass ein Ausgang des zweiten Vergleichers über einen Regler (90), vorzugsweise ein PI-Regler mit dem ersten Vergleicher (82) des Spannungsreglers (84) verbunden ist.6. Circuit arrangement according to one of the preceding claims, characterized in that the measuring elements ( 58 , 76 ) for detecting the currents I P and I S are connected to inputs of a second comparator ( 88 ) and that an output of the second comparator is connected via a controller ( 90 ), preferably a PI regulator, is connected to the first comparator ( 82 ) of the voltage regulator ( 84 ). 7. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der Primärwicklung (50) des Transformators (14) zumindest eine Drosselspule (46, 54) in Reihe geschaltet ist, wobei die zumindest eine Drosselspule (46, 54) integraler Bestandteil des Transformators (14) ist.7. Circuit arrangement according to one of the preceding claims, characterized in that the primary winding ( 50 ) of the transformer ( 14 ) has at least one choke coil ( 46 , 54 ) connected in series, the at least one choke coil ( 46 , 54 ) being an integral part of the transformer ( 14 ) is. 8. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der Primärwicklung (50) des Transformators (14) eine erste Drosselspule (46) vorgeschaltet und eine zweite Drosselspule (54) nachgeschaltet ist, wobei beide Drosselspulen (46, 54) integraler Bestandteil des Transformators (14) sind.8. Circuit arrangement according to one of the preceding claims, characterized in that the primary winding ( 50 ) of the transformer ( 14 ) upstream of a first choke coil ( 46 ) and a second choke coil ( 54 ) is connected, both choke coils ( 46 , 54 ) being an integral part of the transformer ( 14 ). 9. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass ein Kondensator (74) vorgesehen ist, der parallel zu zumindest einer Sekundär­ wicklung (60, 62) des Transformators (14) angeschlossen ist.9. Circuit arrangement according to one of the preceding claims, characterized in that a capacitor ( 74 ) is provided which is connected in parallel to at least one secondary winding ( 60 , 62 ) of the transformer ( 14 ). 10. Schaltungsanordnung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Pulssteuerung (40) als PWM-Steuerung mit symmetrischer Pulsweiten­ modulation ausgebildet ist.10. Circuit arrangement according to one of the preceding claims, characterized in that the pulse control ( 40 ) is designed as a PWM control with symmetrical pulse width modulation. 11. PWM-Steuerung, insbesondere nach Anspruch 9, umfassend einen ersten Komparator (104) zum Vergleich einer Steuerspannung USTEUER mit einer sägezahnförmigen Ver­ gleichsspannung UVERGL und einem zweiten Komparator zum Vergleich einer inneren Steuerspannung USTEUER mit der Vergleichsspannung, wobei an den Ausgängen der Komperatoren jeweils Steuersignale zur Ansteuerung von Leistungsschaltern abgreif­ bar sind, dadurch gekennzeichnet, dass zur Ansteuerung von Leistungsschaltern T1-T4 zumindest eines Brückenzweiges (16, 18) zumindest eine Ansteuereinheit (108, 110) mit einem ersten Steuereingang (204, 190) und einem zweiten Steuereingang (180, 198) vorgesehen ist, wobei ein Ausgang des ersten Komparators über zumindest ein UND-Gatter (178) mit dem zweiten Steuereingang (180) und ein Ausgang des zweiten Koparators über zumindest ein UND-Gatter (202) mit dem ersten Steuereingang (204) verbunden ist und wobei das dem erstem Steuereingang zugeordnete UND-Gatter (202, 188) über einen Inverter (208, 212) und dass dem zweiten Steuereingang zugeordnete UND-Gatter (178, 196) direkt mit einem Ausgang einer Signalgeberschaltung (114) verbunden ist, an dem ein digitales Signal "H" anliegt, das mit der halben Frequenz der Vergleichsspannung schwingt.11. PWM control, in particular according to claim 9, comprising a first comparator ( 104 ) for comparing a control voltage U STEUER with a sawtooth comparison voltage U VERGL and a second comparator for comparing an inner control voltage U STEUER with the reference voltage, at the outputs the comparators each have control signals for controlling circuit breakers, characterized in that for controlling circuit breakers T1-T4 at least one bridge branch ( 16 , 18 ) at least one control unit ( 108 , 110 ) with a first control input ( 204 , 190 ) and one second control input ( 180 , 198 ) is provided, an output of the first comparator via at least one AND gate ( 178 ) with the second control input ( 180 ) and an output of the second comparator via at least one AND gate ( 202 ) with the first Control input ( 204 ) is connected and the AND gate assigned to the first control input ( 202 , 188 ) via an inverter ( 208 , 212 ) and that the AND control ( 178 , 196 ) assigned to the second control input is connected directly to an output of a signal generator circuit ( 114 ), to which a digital signal "H" is present, which vibrates at half the frequency of the reference voltage. 12. PWM-Steuerung nach Anspruch 9 und 10, dadurch gekennzeichnet, dass die Ausgänge (134, 136) der Komparatoren (104, 106) jeweils über einen Inverter (138, 140) mit einem Eingang eines UND-Gatters (146, 148) verbunden sind, dessen Ausgang mit jeweils einem Eingang eines ODER-Gatters (164, 166) verbunden ist, wobei ein Ausgang des dem ersten Komparator (104) zugeordneten ODER-Gatters (164) mit einem Eingang des dem zweiten Steuereingang (180) zugeordneten UND- Gatters (178) und mit einem Eingang eines dem ersten Steuereingang der zweiten Ansteuereinheit (110) zugeordneten UND-Gatters (188) verbunden ist und wobei ein Ausgang des dem zweiten Komparator zugeordneten ODER-Gatters (166) mit einem Eingang des dem Eingang (204) der ersten Ansteuereinheit (108) zugeordneten UND- Gatters (202) und mit einem Eingang eines dem zweiten Steuereingang (198) der zweiten Ansteuereinheit (110) zugeordneten UND-Gatters (196) verbunden ist.12. PWM control according to claim 9 and 10, characterized in that the outputs ( 134 , 136 ) of the comparators ( 104 , 106 ) each via an inverter ( 138 , 140 ) with an input of an AND gate ( 146 , 148 ) are connected, the output of each being connected to an input of an OR gate ( 164 , 166 ), an output of the OR gate ( 164 ) assigned to the first comparator ( 104 ) being connected to an input of the AND assigned to the second control input ( 180 ) - Gate ( 178 ) and is connected to an input of an AND gate ( 188 ) assigned to the first control input of the second control unit ( 110 ) and an output of the OR gate ( 166 ) assigned to the second comparator having an input of the input ( 204 ) assigned to the first control unit ( 108 ) AND gate ( 202 ) and to an input of an AND gate ( 196 ) assigned to the second control input ( 198 ) of the second control unit ( 110 ). 13. PWM-Steuerung nach einem der Ansprüche 9 bis 11, dadurch gekennzeichnet, dass die dem Inverter (138, 140) nachgeordneten UND-Gatter (146, 148) eingangs­ seitig mit einem Ausgang (154) der Signalgeberschaltung (114) verbunden sind, an dem ein digitales Signal "MIN" anliegt, das bei einem vorgebbaren minimalen Zähler­ stand den logischen Pegel "LOW" einnimmt" und dass ein Eingang des ODER-Gatters (164, 166) mit einem Ausgang (172) der Zählschaltung (114) verbunden ist, an dem ein digitales Signal "MAX" anliegt, das bei einem vorgebbaren maximalen Zähler­ stand den logischen Pegel "HIGH" einnimmt.13. PWM control according to one of claims 9 to 11, characterized in that the AND gates ( 146 , 148 ) arranged downstream of the inverter ( 138 , 140 ) are connected on the input side to an output ( 154 ) of the signal generator circuit ( 114 ), to which a digital signal "MIN" is present, which was at a predeterminable minimum counter, the logic level "LOW" and "that an input of the OR gate ( 164 , 166 ) connected to an output ( 172 ) of the counter circuit ( 114 ) is to which a digital signal "MAX" is present, which stood at a predetermined maximum counter, the logical level "HIGH". 14. PWM-Steuerung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass ein Ausgang (132) der Signalgeberschaltung (114) mit einem Steuereingang des Spannungsgenerators (112) zum Setzen und Rücksetzen der sägezahnförmigen Ver­ gleichsspannung UVERGL verbunden ist.14. PWM control according to one of the preceding claims, characterized in that an output ( 132 ) of the signal generator circuit ( 114 ) is connected to a control input of the voltage generator ( 112 ) for setting and resetting the sawtooth-shaped comparison voltage U VERGL . 15. PWM-Steuerung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Signalgeberschaltung (114) als 8-Bit-Zähler ausgebildet ist.15. PWM control according to one of the preceding claims, characterized in that the signal generator circuit ( 114 ) is designed as an 8-bit counter. 16. PWM-Steuerung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Ansteuerschaltung (108, 110) als Kippschaltung, vorzugsweise als Flip-Flop ausgebildet ist. 16. PWM control according to one of the preceding claims, characterized in that the control circuit ( 108 , 110 ) is designed as a flip-flop, preferably as a flip-flop. 17. PWM-Steuerung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass ein Ausgang (122) des Spannungsgenerators (112) über ein aus Kondensator (124) und Widerstand (130) bestehendes Hochpassfilter mit einem negativen Eingang (126, 128) der Komperatoren (104, 106) verbunden ist.17. PWM control according to one of the preceding claims, characterized in that an output ( 122 ) of the voltage generator ( 112 ) via a capacitor ( 124 ) and resistor ( 130 ) existing high-pass filter with a negative input ( 126 , 128 ) of the comparators ( 104 , 106 ) is connected. 18. PWM-Steuerung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Steuerspannung USTEUER direkt mit einem positiven Eingang (118) des ersten Komparators (104) und über eine Inverter-Schaltung (122) mit einem positiven Ein­ gang (120) des zweiten Komparators (106) verbunden ist.18. PWM control according to one of the preceding claims, characterized in that the control voltage U CONTROL directly with a positive input ( 118 ) of the first comparator ( 104 ) and via an inverter circuit ( 122 ) with a positive input ( 120 ) of the second comparator ( 106 ) is connected. 19. Verfahren zur Erzeugung von pulsweitenmodulierten Signalen zur Ansteuerung von Leistungsschaltern T1-T4 eines Pulswechselrichters, wobei eine sägezahnförmige Vergleichsspannung UVERGL mit einer Steuerspannung USTEUER und einer inversen Steuerspannung /USTEUER zur Erzeugung von Ansteuersignalen /KOMP1, /KOMP2 ver­ glichen wird und wobei erste Ansteuerimpulse (216) erzeugt werden, wenn die Ver­ gleichsspanmung UVERGL betragsmäßig größer als die Steuerspannung USTEUER wird und zweite Ansteuerimpulse (218) erzeugt werden, wenn die Vergleichsspannung UVERGL betragsmäßig größer als die inverse Steuerspannung /USTEUER wird, dadurch gekennzeichnet, dass die Ansteuersignale (216, 218) symmetrisch oder im wesentlichen symmetrisch zu einer abfallenden Flanke der sägezahnförmigen Vergleichsspannung erzeugt werden, wobei die Leistungsschalter (T1, T2, T3, T4) zumindest eines Brücken­ zweiges (16, 18) durch eine ansteigende Flanke des ersten Ansteuerimpulses (216) von einem ersten stabilen Zustand in einen zweiten stabilen Zustand geschaltet werden und durch eine ansteigende Flanke des zweiten Ansteuerimpulses von dem zweiten stabilen Zustand in den ersten stabilen Zustand geschaltet werden. 19. A method of generating pulse width modulated signals to control power switches T1-T4 of a pulse-controlled inverter, wherein a saw-tooth reference voltage U COMP with a control voltage U CONTROL and an inverse control voltage / U DUTY to generate control signals / KOMP1 / KOMP2 ver aligned and wherein are generated first drive pulses (216) when the Ver equal span mung U COMP greater magnitude is used as the control voltage U cONTROL and second drive pulses (218) generated when the comparison voltage U COMP magnitude is greater is defined as the inverse control voltage / U dUTY, characterized in that that the control signals ( 216 , 218 ) are generated symmetrically or substantially symmetrically to a falling edge of the sawtooth-shaped reference voltage, the circuit breakers (T1, T2, T3, T4) of at least one bridge branch ( 16 , 18 ) by a rising edge of the first Control pulse ( 216 ) vo n are switched to a second stable state in a first stable state and are switched from the second stable state to the first stable state by a rising edge of the second drive pulse. 20. Verfahren nach zumindest einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die von den Komparatoren (104, 105) erzeugten Ansteuersignale /KOMP1, KOMP2 mit einem digitalen Signal "H" der halben Frequnz der Vergleichsspannung UVERGL logisch UND-verknüpft werden, wobei ein dem positiven Pol der Brücken­ schaltung zugeordneter Leistungsschalter T1, T3 nur dann eingeschaltet wird, wenn das logische Signal "H" den logischen Pegel "LOW" aufweist und ein dem negativen Pol der Brückenschaltung zugeordneter Leistungsschalter T2, T4 nur dann eingeschal­ tet wird, wenn das logische Signal "H" den logischen Pegel "HIGH" aufweist.20. The method according to at least one of the preceding claims, characterized in that the control signals / KOMP1, KOMP2 generated by the comparators ( 104 , 105 ) are logically AND-linked with a digital signal "H" of half the frequency of the comparison voltage U VERGL , wherein a power switch T1, T3 assigned to the positive pole of the bridge circuit is only switched on when the logic signal "H" has the logic level "LOW" and a power switch T2, T4 assigned to the negative pole of the bridge circuit is only switched on when the logic signal "H" has the logic level "HIGH". 21. Verfahren nach zumindest einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass bei einem vorgebbaren minimalen Zählerstand ein logische Signal "MIN" erzeugt wird, das mit den Ansteuersignal /KOMP1, /KOMP2 logisch UND-verknüpft wird und dass bei einem vorgebbaren maximalen Zählerstand ein logisches Signal "MAX" erzeugt wird, das mit den Ansteuersignalen /KOMP1 und KOMP2 logisch ODER­ verknüpft wird.21. The method according to at least one of the preceding claims, characterized, that generates a logic signal "MIN" at a predeterminable minimum counter reading which is logically AND-linked with the control signal / KOMP1, / KOMP2 and that at a predeterminable maximum counter reading a logic signal "MAX" is generated, which is logical with the control signals / KOMP1 and KOMP2 is linked.
DE19848540A 1998-10-21 1998-10-21 Circuit layout and method for operating a single- or multiphase current inverter connects an AC voltage output to a primary winding and current and a working resistance to a transformer's secondary winding and current. Withdrawn DE19848540A1 (en)

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