DE10214739A1 - Multiple operating system computer has a base clock unit and a time controller unit that allocates time slices to the different operating systems loaded in the computer system memory - Google Patents

Abstract

Method for quasi-simultaneous running of a multiplicity of operating systems on the same computer has the following steps: selection of a given program (APS1) or operating system from a multiplicity of programs; restoration of stored processor states (PZ1) for the given program into the processor (100); continuation of processing using the given program using the restored processor states; and interruption of processing of the given program and storage of the processor states in memory; repetition of the preceding steps for another program. An Independent claim is made for a device for quasi-simultaneous running of a number of operating systems on the same computer with said device including a clock unit (6) for generation of a base clock signal and a time controller unit (7) for allocation of time slices to the different operating systems and programs running on the computer.

Description

The present invention relates to a device and a method for performing a quasi-simultaneous Variety of operating systems or programs with Operating system components and in particular to an exchange with a management group to implement a multi Tasking operability of programs with Operating system components.

Fig. 1 shows a simplified block diagram of a telecommunication network according to the state in which a switching network SN (Switching Network) is used for an actual connection establishment the art. Accordingly, a switching center has a central switching unit ZVE with the switching network SN, a signaling system network control SSNC (Signaling System Network Control) for processing signaling data and a coordination processor CP (Coordination Processor) for controlling both the signaling system network control SSNC and the switching network SN. Operation and maintenance of the central switching unit ZVE is made possible via the coordination processor CP, while the signaling system network control SSNC is connected to further switching centers or signaling nodes, for example, via CCSNo.7 high-speed channels of the central signaling system number 7 (Common Channel Signaling System Number 7 ) can. To connect respective subscriber lines, the switching center has a large number of line groups LTG (Line / Trunk Group), which are connected, for example, to digital line units DLU (Digital Line Unit) or transmit CCSNo.7 signaling data. 1, the actual subscriber terminals TE are connected to the digital line units DLU of FIG. Connected, the respective data channels are conveyed in the form of voice or data information from the central office.

As an alternative to the direct connection of the subscriber terminals TE via the digital line units DLU and the associated Switching groups LTG can also do this via remote switching units RSU (Remote Switching Unit) done by the central office be remotely controlled. Such a connection takes place in the Rule via so-called remote control interfaces HTI (Host Time Slot interchange). The LTG management groups point to the Usually a microprocessor or a central unit and one Interface unit for realizing an interface to the digital power unit DLU and to the coupling network SN on, being a special program with application and Operating system components APS (system program system) is processed by the central switching unit CVE is uploaded.

In particular, the rapid progress in microprocessor development is forcing the hardware of existing products (e.g. LTG line group) to be continuously adapted to new generations of microprocessors, since components of older processor generations are being discontinued by their manufacturers in ever shorter periods of time. The line groups LTG shown in FIG. 1, on the other hand, with their performance features must be available to the customer for a much longer time for the new and expansion of his switching systems.

The advancement in microprocessor technology enforces consequently the constant revision of the hardware for example a line group LTG of the Siemens switching system EWSD using current, i.e. H. newer and more powerful processors or central processing units.

However, these fast development cycles of the hardware can especially in the area of switching systems Software development usually for reasons of effort and Do not follow security aspects. On the one hand, this is because for example, one that was processed in the LTG management group Operating system a development effort of approximately 10,000 Includes man-years and, in addition, any and instabilities caused by the software Endanger customer confidence and significantly damage product reputation can. As a result, the software packages and in particular such switching operating systems are not adapted because this is a change to the basic software concept of this Programs and the associated development tools means.

Here under an operating system (Operating System) Programs of a digital computer understood that in Mainly management of resources such as B. RAM, CPU time, peripherals, etc., the Manage files, perform I / O operations and Enable error handling. It is usually modular built up so that only the ones currently needed Programs of the operating system in a working memory are located. As a result, operating systems are programs digital computing system, which together with the properties of a Systems the basis of the possible operating modes of the digital Form computing system or switching system and in particular the execution of higher-level programs (so-called Control and monitor application programs).

In the area of mini computers, for example, the operating systems OS / 400®, AS / 400® from IBM or OS / 8® from DEC are known. In the PC and workstation area, Linux®, Nextstep®, OS / 2® or the Microsoft operating systems Windows CE®, Windows NT® and Windows 95 ® are known.

That in a management group LTG the Siemens switching system EWSD used switching program that both Has application and operating system program components, has the internal name APS (system program system).

In addition to the high level of development during a changeover or new development of such an operating system a very high risk also for imported and stability tried and tested product versions are created by new ones Processors offered options in terms of costs, Power loss and space requirements for the product such as B. the Possibility of operating a multiple number of Subscriber terminals TE in the so-called group processor Leadership group thus not used.

Fig. 2 is a simplified block diagram showing a line group LTG according to the prior art, which comprises essentially of a central processing unit 1, an operating system storage unit 2, and an interface unit 3 for implementing an interface with the digital line units DLU and to the switching network SN. The central unit 1 is, for example, an older processor type such as B. Intel 80486, with which the line group operating system APS stored in the operating system memory 2 can be processed for, for example, 1000 subscriber terminals TE.

Fig. 3 shows a simplified block diagram of a conventional implementation option for the above-described case where a previously used type of processor by the manufacturer is no longer manufactured and is replaced by a newer and more powerful processor type (CPU *). According to FIG. 3, the more powerful central processing unit 100 has, for example, four times the performance of the older central processing unit 1 according to FIG. 2, but replacing this processor with the software-compatible successor type CPU * does not take advantage of the given higher performance and again only the existing and unmodified one Program with APS application and operating system components, for example for 1000 subscriber terminals. Although no increase in the performance of the line group LTG is made possible by the use of the more powerful central unit 100 according to FIG. 3, redesigns to adapt to e.g. B. changed operating voltages etc. costs.

Fig. 4 shows a simplified eighth block diagram of a theoretically possible implementation for a more efficient line group LTG * where now storage unit operating system 200 is a specially adapted to the higher efficiency of the more powerful CPU 100 program APS * is stored for example, 4000 subscriber terminals TE in an enlarged and thus a More powerful interface unit 300 for 4000 subscriber terminals can also be connected via digital line units DLU and a corresponding coupling network SN. According to FIG. 4, an outdated central processing unit 1 (CPU) in the line group LTG * is replaced by the more powerful and software-compatible successor type CPU *, with an adaptation of the operating system or program with application and operating system components APS * to the performance of the new processor CPU * enables the control of, for example, 4000 subscriber terminals per central unit. However, the very high development costs and the extraordinarily high test effort are disadvantageous, whereby the risk of a compatible guarantee of the performance features within a generation of switching systems, for example, cannot be guaranteed. Since a development effort for such a more powerful APS * program must again be estimated at around 10,000 man-years and also includes the risk of malfunctions or failures in the switching system, the solution shown in FIG. 4 is only a theoretical possibility.

The current market situation in particular of Switching systems, however, require quick and effective Exploiting the potential of newer processors or Central units to reduce manufacturing costs and to advantage of the customer, such as B. less space and less Electricity consumption in switching systems.

Operating systems are also included in the prior art a so-called multi-tasking operability, where a large number of application programs quasi-simultaneously be processed. The disadvantage here, however, is that a such an approach is not transferable to Operating systems or programs that form the basis of the possible Form operating modes of a digital computing system and processing control and monitor application programs.

The invention is therefore based on the object Device and a method for quasi-simultaneous execution a variety of operating systems to create which one is simple and inexpensive to implement.

According to the invention, this object is achieved with regard to Device by the features of claim 1 and with regard to the method by the scope of claim 7 solved.

The device preferably consists of quasi-simultaneous Run a variety of operating systems from one Processor state storage unit for storing Processor states for a respective processing state of the Variety of operating systems and one Operating system memory timing unit for performing an operating system Time control, being in a first time range predetermined operating system is selected and saved Processor states for an interrupted processing state of the predetermined operating system in the central unit be restored in a second time period of the predetermined operating system on the interrupted Processing state continues and in a third Time range the execution of the predetermined operating system is interrupted again and the associated processor states again in the processor state storage unit can be saved. This way you get with minimal Hardware effort a multi-tasking operability for the first time Operating systems, increasing the performance of Processors or central processing units without the modification of Operating systems can be used.

The central unit can be, for example Interrupt processing for automatic storage of processor states on a specified via an interrupt address line Have storage location and the operating system or Processor state storage unit a plurality of memory areas for the variety of operating systems and related Have processor states, which is an essential Simplify an operating system memory timer results. This then only has to come from an address decoder and additional address lines for additional addressing of the Operating system and processor state memory areas in Have dependency on the timing performed. In this way, the new processors Interrupt routines available, preferably for one Power management are thought of in a particularly advantageous manner and way for multi-tasking operability of Operating systems used.

Preferably, the Operating system memory timing unit further includes a timing memory area in which a timing program for performing the above described timing control is stored.

Furthermore, an input / output unit for input / output of Data and a real-time signal adjustment unit for adjustment of data to be input / output in real time to that of the Operating system memory timing unit timed Work through the multitude of operating systems, which processing necessary especially in management groups external data or interfaces can.

The real-time signal adaptation unit preferably consists of a compression level for temporal compression and one Intermediate storage level for intermediate storage of the data to be input / output, with a synchronization level in Dependency on the operating system memory control unit the data synchronized and customized data generated.

The further claims show further advantageous Embodiments of the invention.

The invention is based on Exemplary embodiments described with reference to the drawing.

Show it:

Figure 1 is a simplified block diagram of a telecommunications network according to the prior art.

Fig. 2 is a simplified block diagram of a line group in accordance with the prior art;

Fig. 3 is a simplified block diagram of a line group with a powerful central processing unit according to the prior art;

Fig. 4 is a simplified block diagram of a line group with a powerful CPU and adjusted operating system;

Fig. 5 is a simplified block diagram of a device for quasi-simultaneously performing a plurality of operating systems according to a first embodiment;

Fig. 6 is a simplified block diagram of a device for quasi-simultaneously performing a plurality of operating systems according to a second embodiment;

FIG. 7 is a detailed block diagram of part of the device according to FIG. 6;

FIG. 8 shows a simplified block diagram of a real-time signal adaptation unit according to FIG. 6;

Fig. 9 is a simplified graph to illustrate process flows according to the prior art;

Fig. 10 to 15 simplified graphs illustrating process flows in accordance with the present invention;

FIG. 16 is a simplified graph showing a program divided into a storage area; and

Fig. 17 is a simplified graph showing a program division into an I / O area.

Fig. 5 is a simplified block diagram of a device for quasi-simultaneously performing a plurality of operating systems, such as may be used for example in a modified line group LTG '.

In FIG. 5, reference numeral 100 denotes a powerful central processing unit (CPU *), such as is available, for example, as an Intel Pentium® processor and has a more than four-fold increase in performance compared to an earlier processor generation (e.g. Intel 80486®). An operating system memory unit 2 is used to store a large number of programs, hereinafter referred to as operating systems, with application and operating system components APS0 to APS3. The operating systems APS0 to APS3 stored in the operating system memory unit 2 are preferably identical to one another and correspond to a conventional operating system APS (system program system of the EWSD switching system), as is used in the prior art according to FIGS. 2 and 3. For input / output of data to be processed or already processed, an input / output unit 9 is provided which, together with an interface unit 300, realizes an external interface to external units such as a digital line unit DLU and a coupling network SN in the case of a switching system.

Referring to FIG. 5, the operating system storage unit 2 is divided into a plurality of operating system storage areas 20 to 23, in each of the operating systems are to APS0 APS3. In the same way, to implement the external interface, the input / output unit 9 and the interface unit 300 can be modularly divided into input / output areas 90 to 93 and interface areas 30 to 33 , whereby essentially already known or existing structures from conventional systems or can be taken over from a conventional line group LTG, for example according to FIG. 1.

In order to implement a so-called multi-tasking operability for operating systems or for the quasi-simultaneous implementation of a large number of operating systems by a common central unit, the modified line group LTG 'now has an operating system memory time control unit 7 for performing a predetermined operating system time control and a processor state memory unit 4 for storing processor states PZ0 to PZ3 for a respective processing state of the plurality of operating systems APS0 to APS3. More specifically, the operating system memory time control unit connects the central processing unit 100 (CPU *) with its increased performance alternately to either the bus system B2 of the processor state storage unit 4 or the bus system B0 to B3 of a predetermined operating system memory area 20 to 23 , in which the increased performance a respective operating system lies. The processor state storage unit 4 is also divided into a plurality of processor state memory areas 40 to 43 corresponding to the plurality of operating systems, in which respective processor states for the respective processing states of a respective operating system can be stored. A clock unit 6 essentially serves to generate a basic clock both for the central unit 100 , but in particular also for the operating system memory time control unit 7 .

Switching or selecting the respective operating system memory areas 20 to 23 and the processor state memory areas 40 to 43 takes place here according to the following scheme. Provided that an initialization phase has already been completed and all operating systems have been processed at least once at least in part, a predetermined operating system, for example APS1, is selected in a first time period, with previously associated processor states PZ1 stored in the processor state memory area 41 which become an earlier processor state correspond to the respective processing state, be restored or restored in the central unit 100 . After this preparation phase for the central processing unit 100 for processing the operating system APS1, the actual switching or selection of the operating system memory area 21 now takes place, as a result of which the selected operating system APS1 now continues in a second time range at the point of its interruption or from the central unit 100 below Processing of the associated processor status data is further processed. This processing continues until a clock signal generated by the clock unit 6 initializes a third time range, in which the processing of the selected operating system APS1 is again interrupted, a connection is established between the central processing unit 100 and the processor status memory, and in the processor status memory area 41, the last processor states PZ1 (ie at the time of the interruption or the interrupted processing state) are stored. This cycle is then carried out again for a further selected operating system, with a cyclical jumping or selection of operating systems, ie APS1 → APS2 → APS3 → APS0 → APS1 etc., preferably being carried out. However, any selection of operating system memory areas and associated operating systems can also be carried out, if this is necessary in individual cases. As a result of the increased clock rate or processing speed of a more powerful central unit 100, an increased number of operating systems corresponding to this increase in performance can be processed in parallel without the need to modify the originally existing operating systems. This can improve both the cost and the reliability of a correspondingly expanded system.

Since in particular in a line group not only an increase in performance is desired, but also a large number of real-time signals of various interfaces have to be processed, the device according to FIG. 5 also has a real-time signal adaptation unit 8 for adapting data to be input / output in real time to that of the operating system memory time control unit 7 timed execution of the plurality of operating systems APS0 to APS1. More precisely, the real-time signal adaptation unit 8 is used for intermediate storage, compression and synchronization of an external data stream LTG0ED to LTG3ED, which usually has to meet real-time requirements, to an adapted internal data stream LTG0AD to LTG3AD, which corresponds to the processing procedures available in each case of the large number of operating systems. Since in the case of cyclical processing of the four operating systems present in the exemplary embodiment, the external data can only be passed on to the processing of the operating system in a period of R of the total time, the occurring or pending real-time signal data must be collected in the remaining period of x of the total cycle time , compressed to the available time range (R of the cycle time) and fed (synchronized) to the associated input / output unit 9 for processing by the operating system at the right time. In this way, an increase in performance for, for example, a connection of now 4000 subscriber terminals can now be realized for the first time without the need for reprogramming for a more powerful operating system. Since the input / output units and the interface unit 300 are essentially unchanged and have been expanded in a modular manner, the hardware expenditure for such an implementation is relatively low, and is of great advantage in particular in the case of very complex operating systems (several 1000 man-years) which place high demands on reliability.

FIG. 6 shows a simplified block diagram of a device for the quasi-simultaneous implementation of a plurality of operating systems according to a second exemplary embodiment, the same reference symbols denoting identical or corresponding components and a repeated description being omitted below.

According to FIG. 6, there is essentially only one bus system B, which is connected to all the memory areas 2 and 4 , the input / output unit 9 and the central unit 100 via the operating system memory control unit 7 . Accordingly, there is no switchover to a large number of bus systems B0 to B3 and B2 in the operating system memory control unit 7 , but only time-controlled address decoding for addressing the various input / output areas 90 to 93 and an already existing central input / output area 99 . These input / output areas or I / O areas of the input / output unit 9 are, for example, in an address space of 0 to 64 kilobytes.

In the same way, the operating system memory areas 20 to 23 of the operating system memory unit 2 and the processor state memory areas 40 to 43 of the processor state memory unit 4 can be located in a common address space of, for example, 0 gigabytes to 4 gigabytes. For example, V24, HDLC signals, etc. are provided as real-time signal data LTG0ED to LTG3ED, which are passed on by the interface unit 300 to the real-time signal adaptation unit 8 for intermediate storage, compression and synchronization.

FIG. 7 shows a detailed block diagram for illustrating a part of the device according to FIG. 6, the same reference symbols denoting identical or corresponding elements and again a repeated description being dispensed with.

The CPU multiplexer for data, address and control lines or the operating system memory control unit 7 shown in FIG. 6 is greatly simplified here using additional performance features of the new processor generations or central unit 100 . Accordingly, the central processing unit 100 has an interrupt processing which is actually only intended for power management and is referred to in Intel Pentium® processors as a system management mode interrupt SMI. When a corresponding clock or interrupt signal 71 is present at a corresponding input SMI, the central unit 100 outputs all internal states of the processor, with addressing at a predetermined memory location via an additional address line 72 to indicate an active system management mode interrupt (SMIACT) is possible.

According to Fig. 7 therefore this address line 72 is used so that the operating system storage unit 2 is disabled and the processor state storage unit 4 is activated. Thus, for example, when a clock signal 71 arrives when the operating system APS0 is being processed, the associated processor states can be stored directly in the processor state memory area 40 and then a time control program SMI-C (SMI code) stored in a time control memory area 75 to implement the remaining time control be carried out. All that is required for this is an additional address decoder 73 and additional address lines 74 , as a result of which the operating system memory areas 20 to 23 and the processor state memory areas 40 to 43 can be addressed or selected as a function of the time control carried out. Specifically, such a time control program SMI-C would switch to the address of the memory area 21 , for example, so that after the SMI interrupt processing has been completed and the processor states from the processor state memory 41 have been restored, processing of the operating system APS1 in the operating system memory area continues 21 is carried out. In this way, all operating system memory areas 20 to 23 and associated processor status memory areas 40 to 43 are selected or addressed in sequence and processing of the unchanged operating systems APS0 to APS3 is carried out.

With a suitable arrangement of the operating systems APS0 to APS3 respective positions in a corresponding address space therefore all operating systems via associated address decoders can be jumped on individually. A modification of addresses within the operating systems it is therefore not necessary which is why you can increase performance on particularly simple and inexpensive way.

FIG. 8 shows a simplified block diagram for realizing a real-time signal adaptation unit 8 according to FIG. 6, the mode of operation being explained by way of example only on an input data stream.

According to FIG. 8, for example, an incoming real-time signal data stream LTGxED, which contains, for example, V24 or HDLC data, is temporally compressed in a compression stage 81 if the time range of the external or real signal data is greater than a time range in which an associated operating system is being processed can be. Subsequently, this data is temporarily stored in an intermediate storage stage 82 in order to then offer it as adapted data LTGxAD at a predetermined point in time in synchronism with a processing of a respective operating system carried out by the central unit 100 of the input / output unit. This synchronization takes place here through a synchronization stage 83 and as a function of a synchronization signal Sync, which is output by the operating system memory control unit 7 . In this way, the real-time signal data LTGxED arriving at any time can be correlated with a respective processing time range of a respective operating system.

Referring to FIG. 8, the intermediate storage stage 82 was placed after the compression level 81st However, it can also be arranged in the same way before this stage. In the same way, this real-time signal adaptation unit 8 can also be implemented for an output data stream.

FIG. 9 shows a graphical representation to illustrate a method sequence according to the prior art, the same reference numerals describing the same or corresponding elements as in FIGS. 1 to 8 and a repeated description being omitted below.

According to Fig. 9 of the art is in a line group LTG prior only accessible to an operating system storage unit 2 with an operating system, which via an interface unit 3 periphery Message Channel controller (MCH), Signal Buffer Controller (SIB), Interrupt controller, I / O ports etc. can be controlled. The central unit 1 here consists of an older processor, for example an Intel 80486® processor with a 25 MHz operating frequency. In this way, 128 MB of RAM (DRAM, FLASH) and line group-specific peripheral functions for processing 1000 subscriber terminals TE can be implemented.

FIG. 10 shows a simplified graphical illustration to illustrate method sequences according to the invention, the same reference numerals again designating identical or similar elements and a repeated description being omitted below.

Referring to FIG. 10, the peripheral functions and the interface areas of the conventional line group to be quadrupled, and also connected via quadrupled operating memory areas to the central unit 100 having improved performance (CPU *). The complete functions of a previous LTG line group are located in each district, but only a quarter of the central unit 100 is available to each line group quarter LTG0 to LTG4. Since the central unit 100 cannot be spatially divided while maintaining its function, it is divided in time. For this purpose, for example, the operating system clock of the group processor software in the central switching unit ZVE with 4 milliseconds offers itself. Each newly created "virtual line group" LTG0 to LTG4 is thus processed by the common central unit 100 only for the duration of 1 millisecond over a total cycle time of 4 milliseconds. During the remaining 3 milliseconds, the CPU for the operating system memory 2 and the peripheral or interface unit 300 or 30 to 33 is virtually absent.

In order to maintain the performance of a line group LTG 'modified in this way, the central unit 100 must now process as many commands in a time range of one millisecond as a less powerful central unit 1 in a time range of four milliseconds, ie it must be at least 4 times more powerful. For example, the processor successor Intel Pentium®, which is 10 times faster and has a working frequency of 163 MHz, is selected. Despite the quartering, this results in an increase in the performance of the individual virtual line groups LTG0 to LTG3.

The system management mode interrupt (SMI) of the Pentium CPU, which is actually only intended for power management but is used today for reasons of energy saving, is preferably used to switch off the central unit 100 from one virtual line group and connect it to the next. When it enters, it saves all internal states of the processor in an external memory, and until it exits (SMI-RET) it restores all internal states of the processor by re-reading them from the external memory. The operating system memory time control unit 7 now generates SMI interrupts for the central processing unit 100 at intervals of, for example, one millisecond and thus brings about the storage of respective processor states in an associated processor state area, the restoration of new processor states and the processing of an operating system belonging to the new processor states.

The real-time signal adaptation unit 8 causes the loss of incentives (interrupts) and data by synchronization of external incentives and buffering of external data. For example, interrupts LTG0-I1 and LTG0-I2 for the virtual line group LTG0 occurring during the processing phase of the virtual line group LTG1 are shifted into the processing phase of the virtual line group LTG0 by the real-time signal adaptation unit 8 and can therefore be used there as adapted interrupts LTG0-I1 'and LTG0-I2 'are processed.

Figs. 11 to 15 are simplified graphical representations for illustrating the respective process sequences in an implementation according to Fig. 10, wherein like reference numerals again refer to like or corresponding elements and will be omitted below a repeated description.

Referring to FIG. 11, the timing program or SMI code IC (I-handler) is shown in the circle center. The associated variable and input / output memory area (I / O) is located in the next shell located further out. Before and after this memory area of this shell, for example, 512 byte processor state memories for entering and exiting the line group or for storing the processor state data PZ0 to PZ3 are shown. The shells located further outside show code and data, I / O memory areas of the respective virtual line groups LTG0 to LTG3, the operating systems APS0 to APS3 described above being in the code area.

If you imagine a clockwise rotating pointer, it shows the sequence of the operating system memory time control unit 7 . SIB1 denotes, for example, the 4 millisecond interrupt of the signal buffer unit of the virtual line group LTG1. A sequence of this interrupt SIB1 is preferably positioned in the virtual line group LTG1 such that the 4 millisecond interrupt of the LTG1 occurs at the beginning of the processing time of the virtual line group LTG1. The interrupts (not shown) of the signal buffer unit for the virtual line groups LTG2, LTG3 and LTG4 are positioned in the same way, as a result of which an incentive loss or interrupt loss, in particular in a configuration of line groups, is avoided by means of a simple synchronization.

According to FIG. 11, the interrupt processing described above is triggered by the occurrence of an SMI interrupt in a time interval of one millisecond and the processor states PZ0 are loaded into the associated processor state area (time area III) via the SMIACT line. A predetermined operating system (for example APS1) is then selected in a first time period I, with associated processor states PZ1 being restored into the central unit. With the return (SMI-RET) from the interrupt processing SMI-C, the method enters a second time range 11 in which the processing of the operating system APS1 is now resumed in an interrupted processing state using the restored processor states PZ1. Finally, the processing of the predetermined operating system APS1 is interrupted again in a third time period III, triggered again by the one millisecond SMI interrupt, and the associated processor states PZ1 are stored in the associated processor state memory area.

According to Fig. 12 to 14, the operation of the real-time signal-adjustment unit 8 will be explained using the example of the message channel controller (MCH).

In the outer shell, the reception of message bytes with and without zero bit insertion Z is represented at 64 kbit / second on an MCH input of the virtual line group LTG1 in HDLC format. Within a 4 millisecond period, the tail of a message, two complete messages and a header of a message are received and written to a buffer or buffer. According to FIGS. 13 and 14 of the intermediate memory during the active working phase of the virtual circuit group LTG1 or the associated operating system APS1 in the next 4 milliseconds by operation of the HDLC controller is now completely empty the line group to the 8-fold frequency (512 kbit / second), whereby the interrupts occurring at the end of the message thus occur completely during a processing phase of the virtual line group LTG1. In the sending direction, the same mechanism is only used in reverse. For this purpose, the HDLC controllers of the line group are operated with a fast clock burst instead of a uniform clock. Since these are designed up to a clock rate of one megabit / second anyway, they do not have to be changed. The real-time signal adaptation unit can thus be partially or completely adapted to all peripheral units of the line group by simple measures, as a result of which the external units of the processed software or the operating system present themselves 100% compatible.

Fig. 15 shows an implementation of the so-called time supervision or watchdog functions of each virtual line groups. Each virtual line group LTG0 to LTG3 triggers its watchdog or time monitoring WD-0 to WD-3 in the usual way. Does the time monitoring of a line group expire, e.g. B. because of an infinite loop in the operating system, then the watchdog does not trigger a direct CPU reset in contrast to previously, but reports this to the SMI interrupt service via I / O register. This SMI interrupt processing SMI-C reads out the I / O register before each exit. If an expired time monitoring (watchdog) of a virtual line group is detected there, it does not restore the previous processor state of this virtual line group, but the reset state of the processor or the central unit 100 . As a result, a time monitoring reset R acts exactly as before within a line group.

For security reasons, the SMI interrupt processing SMI-C itself a new time monitoring WD-IC, which in Switched operation the regular execution of the SMI code or Time control program monitors. A reset takes place at the end IR after a so-called preboot comparable to a Power-up reset. This is also a time monitor in such a modified line group LTG ' fully implemented.

Fig. 16 shows a simplified representation of a program division in an address space for addressing a memory area for a conventional and a line group according to the invention.

Referring to FIG. 16, a memory area of a conventional line group LTG and is shown a storage area in the inventive extended line group LTG 'with their virtual line groups LTG0 to LZG3 and the address space for the SMI interrupt processing in the right five columns in the left column. Furthermore, a column is shown to illustrate a memory division of the extended line group LTG 'according to the invention in a linear mode, ie without an activated SMI switching mechanism.

The memory area of the conventional LTG line group consists of 256 megabytes of RAM (with the APS operating system) at the beginning of the memory and 512 kilobytes of FLASH at the end of the memory. In linear mode, there are 1 gigabyte of RAM at the beginning, of which 256 megabytes are assigned to one of the virtual line groups LTG0 to LTG3. There are also 512 kilobytes of FLASH at the end of the memory. In quadruple MUX operation after activation of the SMI switchover mechanism, 256 megabytes of RAM are displayed at the beginning of the memory by the address decoding described above or special ASIC hardware during their active processing phases, in which the actual operating system (APS0 to APS3) located. The SMI memory area is displayed in a switchover phase (SMIACT is active), with 16 kilobytes of RAM starting at address 38000H, divided into an area for code and data for SMI interrupt processing and a further 8 areas for saving and restoring the processor states of the respective leadership groups. For initialization purposes, the 16 kilobyte memory is shown in linear mode from 1 gigabyte. All memory fades in and out are implemented in the address decoder of the operating system memory control unit, preferably by means of ASICs.

The former boot code of the conventional line group with 128 kilobytes in size is in linear operation extended management group LTG 'not quite at the end of the Storage area. Rather, here is the so-called pressoot code and before that the SMI code together with the boot code for the individual line groups in a 512 kilobyte FLASH Storage area housed.

After a reset, the central unit first runs the press-boot Code. This copies the SMI code into the 16 kilobytes Mirror (RAM Mirror) and thus prepares the SMI memory area for the later execution of the SMI interrupt or of the timing program. Furthermore, in the 16th Kilobyte memory area (not explicitly four) 512 byte processor state memory areas according to the processor state after reset. After that he copies the boot code to the top of each 256 Megabytes of storage space. Because the top end of 256 megabytes large storage in the extended line group LTG ' has not been used, this is software compatible conventional line groups. The press boot is then activated 4-way MUX operation by enabling the SMI interrupt. When entering the virtual line group LTG1 The SMI interrupt now restores the processor state as immediately after reset that Operating system memory timer hides the memory areas for the virtual Line group LTG1 and the central unit keeps the boot code as with the conventional LTG line group at the top Out of memory. After a millisecond, the SMI Interrupt the central unit again, save the Processor status of line group LTG1 in the corresponding 512 Byte processor state memory area, restored again the processor reset state from the second 512 bytes Processor state memory area and boots the virtual one Line group LTG2, which is now switched or addressed by the operating system memory control unit only its memory sees. Then the line groups LTG3 and LTG0 in same way.

While switching from one line group to the next the central unit runs the time control program or SMI interrupt processing by. This can be too Control purposes access to all 256 megabyte areas of the virtual Line groups from the first gigabyte and up to the 512th Obtain kilobyte FLASH at the end of the memory by this memory area through the operating system memory Control unit displayed accordingly during this time becomes. In this way, e.g. B. Routine checks of the boot Codes within a line group memory with the Original FLASH. A leadership group only reaches their associated DRAM Storage and thus encapsulates itself from the others Leadership groups safely. However, the FLASH memory is Term of each line group from the first gigabyte faded in to enable FLASH updates, of course from one leadership group at a time by communicating with the higher-level control of the coordination processor CP can be executed. By communicating with the SMI Code can be re-programmed after successfully reprogramming the FLASH then a reset and a restart with press boot are triggered.

Fig. 17 shows in the same way the distribution of the I / O area of a conventional line group LTG and according to the invention extended line group LTG '. Again, there is one kilobyte in the conventional input / output area with a total address space from zero to 64 kilobytes at the beginning of the memory, another two kilobytes from the address 4000 H and one kilobyte at the end of the memory. When I / O address allocation in linear operation of the extended line group LTG 'there are four kilobyte I / O addresses at the beginning of the memory, one kilobyte each of which is assigned to one of the line groups LTG0 to LTG3. The I / O area from address 4000 H and at the end of the memory is quadrupled in the same way. The next five columns show the address space of the I / O area in four-fold MUX mode after activation of the SMI switchover mechanism. Each virtual line group LTG0 to LTG3 shows its I / O areas corresponding to the conventional line group LTG during its active phase, so that in the switchover phase (SMIACT is active) the I / O area corresponds to the division in the virtual line groups of the conventional line group. In addition to the I / O areas of the conventional line group, a new I / O area (1 kilobyte) with registers for switching on and controlling the SMI switching mechanism is implemented. This is shown at the same address in linear mode and during SMI service. All I / O register fades in and out are implemented in an address decoder of the operating system memory control unit.

The invention was based on a 4-way switched operating system for a line group in one Switching system described. However, she is not on it limited and in the same way includes a device and a method for performing a quasi-simultaneous any number of operating systems in any Environment system. Furthermore, the use of a Variety of the same operating systems proposed. In However, different operating systems are the same for processing by a central unit by the proposed device allows.

Claims (14)

1. Device for quasi-simultaneous execution of a plurality of programs with operating system components with an operating system storage unit ( 2 ) for storing the plurality of programs (APS0 to APS3);
a clock unit ( 6 ) for generating a basic clock;
a central processing unit ( 100 ) for processing the programs (APS0 to APS3) stored in the operating system storage unit ( 2 ) depending on the basic clock; and
a bus for connecting the operating system memory unit ( 2 ) to the central unit ( 100 ),
marked by
a processor state storage unit ( 4 ) for storing processor states (PZ0 to PZ3) for a respective processing state of the plurality of programs (APS0 to APS3); and
an operating system memory time control unit ( 7 ) for carrying out an operating system time control in such a way that a predetermined program (APS1) is selected in a first time range (I) and stored processor states (PZ1) for an interrupted processing state of the predetermined program (APS1) from the processor state - Storage unit ( 4 ) in the central unit ( 100 ) are restored,
in a second area (II) the processing of the predetermined program (APS1) is continued by the central unit ( 100 ) at the interrupted processing state, and
in a third time period (III) the processing of the predetermined program (APS1) is interrupted again and the associated processor states (PZ1) from the central unit ( 100 ) are stored in the processor state memory unit ( 4 ). 2. Device according to claim 1, characterized in that the central unit ( 100 ) has an interrupt processing (SMI) for the automatic storage of processor states at a memory location defined via an interrupt address line (SMIACT),
the operating system storage unit ( 2 ) has a multiplicity of operating system storage areas ( 20 to 23 ) for the multiplicity of programs (APS0 to APS3),
the processor status storage unit ( 4 ) has a plurality of processor status storage areas ( 40 to 43 ) for the plurality of programs (APS0 to APS3), and
the operating system memory time control unit ( 7 ) has an address decoder ( 73 ) and additional address lines ( 74 ) for additional addressing of the operating system memory areas ( 20 to 23 ) and the processor state memory areas ( 40 to 43 ) depending on the time control carried out. 3. Device according to claim 1 or 2, characterized in that the operating system memory time control unit ( 7 ) has a time control memory area (75) in which a time control program (SMI-C) for performing the time control is stored. 4. Device according to one of the claims 1 to 3, characterized by
an input / output unit ( 9 ) for input / output of data for the plurality of programs (APS0 to APS3) and
a real-time signal adaptation unit ( 8 ) for adapting data to be input / output in real time for the plurality of programs (APS0 to APS3) to the processing of the plurality of programs (APS0 to APS1) by the operating system memory timing control unit ( 7 ) Central unit ( 100 ). 5. The device according to claim 4, characterized in that the real-time signal adaptation unit ( 8 )
a compression stage ( 81 ) for temporal compression and a buffer stage ( 82 ) for temporarily storing the real-time data to be input / output (LTG0ED to LTG3ED) and for generating adapted data (LTG0AD to LTG3AD), and
has a synchronization stage ( 83 ) for synchronizing the adapted data (LTG0AD to LTG3AD) to associated programs as a function of the operating system memory control unit ( 7 ). 6. Device according to one of the claims 1 to 5, characterized in that they are a Line group (LTG) in a switching center. 7. Method for quasi-simultaneous execution of a large number of programs with operating system components with the steps: a) selecting a predetermined program (APS1) from the plurality of programs; b) restoring stored processor states (PZ1) for the predetermined program (APS1) in a central unit ( 100 ); c) continuing execution of the predetermined program (APS1) using the stored processor states by the central unit ( 100 ); and d) interrupting the processing of the predetermined program (APS1) and storing associated processor states (PZ1) from the central unit ( 100 ). 8. The method according to claim 7, characterized in that the Steps a) to d) for all programs (APS0 to APS3) be carried out repeatedly. 9. The method according to claim 8 or 9, characterized in that step d) is realized by an SMI interrupt processing. 10. The method according to any one of claims 7 to 9, characterized in that the Select in step a) in a predetermined or any Order is carried out. 11. The method according to any one of claims 7 to 10, characterized by the further steps: a) receiving real time data (LTG1ED) for a predetermined program (APS1); and b) generating adapted input data (LTG1AD) for the predetermined program as a function of the received real-time data (LTG1ED). 12. The method according to claim 11, characterized in that in step a) the next steps 1. compressing the real time data (LTG1ED) into a time range which is smaller than a time range for step c); 2. buffering the received and / or compressed data to generate adapted input data (LTG1AD); and 3. Synchronize the adapted input data (LTG1AD) with the continued execution of the predetermined program (APS1) in step c). 13. The method according to any one of claims 7 to 12, characterized in that in step a) a time monitoring (WD-1) is carried out to prevent undefined states in the predetermined program (APS1). 14. The method according to any one of claims 7 to 12, characterized in that in the Steps a) and b) time monitoring (WD-IC) for Preventing undefined states in a timing Program (SMI-C) is carried out.