CN102043699A - SOC (System on a Chip) debugging and verifying device and method - Google Patents

SOC (System on a Chip) debugging and verifying device and method Download PDF

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Publication number
CN102043699A
CN102043699A CN 201010528092 CN201010528092A CN102043699A CN 102043699 A CN102043699 A CN 102043699A CN 201010528092 CN201010528092 CN 201010528092 CN 201010528092 A CN201010528092 A CN 201010528092A CN 102043699 A CN102043699 A CN 102043699A
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bus
soc
debug
debugging
chip
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CN 201010528092
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Chinese (zh)
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杨元成
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Qingdao Hisense Xinxin Technology Co Ltd
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Qingdao Hisense Xinxin Technology Co Ltd
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Priority to CN 201010528092 priority Critical patent/CN102043699A/en
Publication of CN102043699A publication Critical patent/CN102043699A/en
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Abstract

The embodiment of the invention discloses an SOC (System on a Chip) debugging and verifying device and method, relating to the field of SOCs. The SOC debugging and checking device realizes sufficient verification on an IP hardcore and an SOC, greatly increases the developing efficiency of SOC products and lowers the developing cost. The SOC debugging and verifying device is in bus connection with an FPGA (Field Programmable Gate Array) platform, and the SOC debugging and verifying are carried out through the bus connection. The SOC debugging and verifying device and method are applied to SOC verifying.

Description

On-chip system debug demo plant and method
Technical field
The present invention relates to SOC (system on a chip) (System on Chip is hereinafter to be referred as SOC) field, relate in particular to a kind of SOC debugging demo plant and method.
Background technology
In the early development of SOC chip, the debugging of system checking is the key that can chip be succeeded in developing.The system of the SOC of a complexity is made up of numerous IP modules, and each module all will participate in the checking of total system.When the SOC chip carries out verifying early stage, generally can adopt the mode of soft nuclear, behind each IP module synthesis, be written into field programmable gate array (Field-Programmable Gate Array is hereinafter to be referred as FPGA) platform.
Because the confidentiality of IP module and the collaborative problem between the producer in the early stage in work, generally are difficult to take the soft nuclear of IP producer; The resource-constrained of FPGA platform besides, the adding of new IP system causes the not enough situation of system resource sometimes, and both of these case tends to hinder the progress of exploitation, reduces the efficient of exploitation.
At this problem, at present, in the early stage of SOC chip verifying and debugging, when carrying out the integration of IP module, the FPGA platform that generally resource that can more renew is bigger adds the IP quality risk, and this has increased the cost of development of SOC chip again to a great extent.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of on-chip system debug demo plant and method, realizes IP stone and SOC system are verified fully, has greatly improved SOC Products Development efficient, has reduced cost of development.
For solving the problems of the technologies described above, on-chip system debug demo plant of the present invention and method adopt following technical scheme:
A kind of on-chip system debug demo plant, described on-chip system debug demo plant is that bus is connected with the FPGA platform, connects by described bus, carries out SOC (system on a chip) SOC debugging checking.
Comprise:
IP kernel unit and FPGA interface unit that supporting bus connects;
Described FPGA interface unit is connected with described IP kernel unit by described bus, and is connected with the FPGA platform by described bus.
Also comprise:
Debug interface unit is connected with described IP kernel unit, is used for described IP kernel unit is carried out real-time debug.
Described bus is a pci bus.
Described bus is an advanced microprocessor bus architecture AMBA bus.
Described AMBA bus comprises: HRDATA[31..0], HWDATA[31..0], HADDR[31..0], HRESP[1..0], HBURST[2..0], HSIZE[2..0], HTRANS[1..0], HRESETn, HGRANT, HREADY, HBUSREQ, HWRITE, HCLK.
Described debug interface unit links together JTAG debugging acid and IP kernel unit by JRST, JTCK, JTDI, JTDO, JTMS.
Described IP kernel unit is provided with several pull-up resistors that driving force is provided for its debugging.
The IP kernel of described IP kernel unit is the IP stone.
A kind of on-chip system debug verification method,
The on-chip system debug demo plant is connected by bus with the FPGA platform, by IP stone mode, carries out SOC (system on a chip) SOC debugging checking.
In an embodiment of the present invention, when the SOC system verification in early stage, when not having soft nuclear of IP or FPGA platform resource not enough, can utilize this on-chip system debug demo plant IP kernel unit and FPGA platform to be linked together by bus, IP stone and SOC system are verified fully, this device has greatly improved SOC Products Development efficient, has reduced cost of development.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is one of structural representation of embodiment of the invention on-chip system debug demo plant;
Fig. 2 be embodiment of the invention on-chip system debug demo plant structural representation two;
Fig. 3 is one of structural representation of embodiment of the invention IP kernel unit;
Fig. 4 be embodiment of the invention IP kernel unit structural representation two;
Fig. 5 be embodiment of the invention IP kernel unit structural representation three;
Fig. 6 be embodiment of the invention IP kernel unit structural representation four;
Fig. 7 is the structural representation of embodiment of the invention FPGA interface unit;
Fig. 8 is the structural representation of embodiment of the invention debug interface unit;
Fig. 9 is the process flow diagram of embodiment of the invention on-chip system debug verification method.
Description of reference numerals:
1-on-chip system debug checking dress 2-FPGA platform; 11-IP vouching unit; Put;
The 12-FPGA interface unit; The 13-debug interface unit.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
The embodiment of the invention provides a kind of on-chip system debug demo plant and method, realizes IP stone and SOC system are verified fully, has greatly improved SOC Products Development efficient, has reduced cost of development.
The embodiment of the invention provides a kind of on-chip system debug demo plant, and as shown in Figure 1, this on-chip system debug demo plant 1 and FPGA platform 2 connect by described bus for bus is connected, and carries out SOC (system on a chip) SOC debugging checking.
When the SOC system verification in early stage, when not having soft nuclear of IP or FPGA platform resource not enough, can utilize this on-chip system debug demo plant IP kernel unit and FPGA platform to be linked together by bus, IP stone and SOC system are verified fully, this device has greatly improved SOC Products Development efficient, has reduced cost of development.
Further, as shown in Figure 2, in preferred embodiment of the present invention, this on-chip system debug demo plant 1 comprises: IP kernel unit 11 and FPGA interface unit 12 that supporting bus connects;
Described FPGA interface unit 12 is connected with described IP kernel unit 11 by described bus, and is connected with FPGA platform 2 by described bus.
Again further, this device also comprises:
Debug interface unit 13 is connected with described IP kernel unit 11, is used for described IP kernel unit 11 is carried out real-time debug.
Further, the various buses of above-mentioned bus for realizing, for example described bus is a pci bus, in the present embodiment, is preferably, described bus is an advanced microprocessor bus architecture AMBA bus.
Further, the IP kernel of described IP kernel unit is the IP stone.By the mode of IP stone, realize debugging checking to the FPGA platform of SOC system.
Below with a specific embodiment technical scheme of the present invention is described, as Fig. 3-shown in Figure 6, the IP kernel unit is U1 (comprising U1A, U1B, U1C, U1D), U1 is the IP kernel unit with AMBA bus, the IP kernel of this IP kernel unit is the IP stone, be connected with the FPGA platform by the AMBA bus, to carry out the debugging checking of SOC system.The AMBA bus that need use comprises HRDATA[31..0], HWDATA[31..0], HADDR[31..0], HRESP[1..0], HBURST[2..0], HSIZE[2..0], HTRANS[1..0], HRESETn, HGRANT, HREADY, HBUSREQ, HWRITE, HCLK.As shown in Figure 7, CON2 is the FPGA interface, can link together FPGA platform and IP kernel unit by this interface.As shown in Figure 8, CON1 is the JTAG debugging interface, and this interface links together JTAG debugging acid and IP kernel unit by JRST, JTCK, JTDI, JTDO, JTMS, by this interface, can be easily the IP stone of IP kernel unit be carried out real-time debug.Further, the R2 among Fig. 3, R4, R5, R6, R7 are the pull-up resistor of corresponding network, for its debugging provides driving force.
In an embodiment of the present invention, when the SOC system verification in early stage, when not having soft nuclear of IP or FPGA platform resource not enough, can utilize this on-chip system debug demo plant IP kernel unit and FPGA platform to be linked together by the AMBA bus, mode by the IP stone, realization is to the FPGA platform validation of SOC system, this method is by the mode of IP stone, need not the soft nuclear of IP, made things convenient for the real-time debug of external module, effectively saved the system resource of FPGA platform, this device has greatly improved SOC Products Development efficient, has reduced cost of development.
The embodiment of the invention also provides a kind of method of utilizing above-mentioned on-chip system debug demo plant to carry out the on-chip system debug checking, and as shown in Figure 9, this method comprises:
Step 101, on-chip system debug demo plant are connected by bus with the FPGA platform, by IP stone mode, carry out SOC (system on a chip) SOC debugging checking.
As shown in Figure 2, this on-chip system debug demo plant 1 comprises: IP kernel unit 11 and FPGA interface unit 12 that supporting bus connects; Wherein, the IP kernel of IP kernel unit is the IP stone, is connected with FPGA interface unit 12 by bus, and further is connected with FPGA platform 2 buses by FPGA interface unit 12, with the checking by the IP stone, realizes the FPGA platform debugging checking of SOC system.
This on-chip system debug demo plant 1 also comprises: debug interface unit 13, be connected with IP kernel unit 11, and be used for IP kernel unit 11 is carried out real-time debug.
Further, above-mentioned bus is preferably advanced microprocessor bus architecture AMBA bus.
In an embodiment of the present invention, when the SOC system verification in early stage, when not having soft nuclear of IP or FPGA platform resource not enough, can utilize this on-chip system debug demo plant IP kernel unit and FPGA platform to be linked together by the AMBA bus, mode by the IP stone, realization is to the FPGA platform validation of SOC system, this method adopts IP stone mode, need not the soft nuclear of IP, made things convenient for the real-time debug of external module, effectively save the system resource of FPGA platform, greatly improved SOC Products Development efficient, reduced cost of development.
Through the above description of the embodiments, the those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential common hardware, can certainly pass through hardware, but the former is better embodiment under a lot of situation.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words can embody with the form of software product, this computer software product is stored in the storage medium that can read, floppy disk as computing machine, hard disk or CD etc., comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.

Claims (10)

1. an on-chip system debug demo plant is characterized in that, described on-chip system debug demo plant is that bus is connected with the FPGA platform, connects by described bus, carries out SOC (system on a chip) SOC debugging checking.
2. device according to claim 1 is characterized in that, comprising:
IP kernel unit and FPGA interface unit that supporting bus connects;
Described FPGA interface unit is connected with described IP kernel unit by described bus, and is connected with the FPGA platform by described bus.
3. device according to claim 2 is characterized in that, also comprises:
Debug interface unit is connected with described IP kernel unit, is used for described IP kernel unit is carried out real-time debug.
4. device according to claim 3 is characterized in that,
Described bus is a pci bus.
5. device according to claim 3 is characterized in that,
Described bus is an advanced microprocessor bus architecture AMBA bus.
6. device according to claim 5 is characterized in that,
Described AMBA bus comprises: HRDATA[31..0], HWDATA[31..0], HADDR[31..0], HRESP[1..0], HBURST[2..0], HSIZE[2..0], HTRANS[1..0], HRESETn, HGRANT, HREADY, H β USREQ, HWRITE, HCLK.
7. device according to claim 5 is characterized in that,
Described debug interface unit links together JTAG debugging acid and IP kernel unit by JRST, JTCK, JTDI, JTDO, JTMS.
8. device according to claim 5 is characterized in that,
Described IP kernel unit is provided with several pull-up resistors that driving force is provided for its debugging.
9. according to the described device of the arbitrary claim of claim 1-8, it is characterized in that,
The IP kernel of described IP kernel unit is the IP stone.
10. an on-chip system debug verification method is characterized in that,
The on-chip system debug demo plant is connected by bus with the FPGA platform, by IP stone mode, carries out SOC (system on a chip) SOC debugging checking.
CN 201010528092 2010-11-02 2010-11-02 SOC (System on a Chip) debugging and verifying device and method Pending CN102043699A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102497596A (en) * 2011-12-02 2012-06-13 青岛海信信芯科技有限公司 Debugging device and verification method of field programmable gate array (FPGA) platform of television network signal
CN102693343A (en) * 2012-05-25 2012-09-26 青岛海信信芯科技有限公司 Verification device and verification method of system on chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1383200A (en) * 2001-04-27 2002-12-04 株式会社鼎新 Design checking method and device of single chip system
CN1609862A (en) * 2004-11-19 2005-04-27 华南理工大学 IP nuclear simulation confirmation platform based on PCI bus and proving method thereof
US20050138582A1 (en) * 2003-12-22 2005-06-23 Woon-Seob So System-on-chip development apparatus for wire and wireless internet phone
CN101354674A (en) * 2007-07-26 2009-01-28 北京神州龙芯集成电路设计有限公司 Method and apparatus for implementing hardware level verification

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1383200A (en) * 2001-04-27 2002-12-04 株式会社鼎新 Design checking method and device of single chip system
US20050138582A1 (en) * 2003-12-22 2005-06-23 Woon-Seob So System-on-chip development apparatus for wire and wireless internet phone
CN1609862A (en) * 2004-11-19 2005-04-27 华南理工大学 IP nuclear simulation confirmation platform based on PCI bus and proving method thereof
CN101354674A (en) * 2007-07-26 2009-01-28 北京神州龙芯集成电路设计有限公司 Method and apparatus for implementing hardware level verification

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102497596A (en) * 2011-12-02 2012-06-13 青岛海信信芯科技有限公司 Debugging device and verification method of field programmable gate array (FPGA) platform of television network signal
CN102693343A (en) * 2012-05-25 2012-09-26 青岛海信信芯科技有限公司 Verification device and verification method of system on chip
CN102693343B (en) * 2012-05-25 2014-12-03 青岛海信信芯科技有限公司 Verification device and verification method of system on chip

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Application publication date: 20110504