CN101196557A - Method, device and system for field programmable gate array test - Google Patents
Method, device and system for field programmable gate array test Download PDFInfo
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- CN101196557A CN101196557A CNA2007101725821A CN200710172582A CN101196557A CN 101196557 A CN101196557 A CN 101196557A CN A2007101725821 A CNA2007101725821 A CN A2007101725821A CN 200710172582 A CN200710172582 A CN 200710172582A CN 101196557 A CN101196557 A CN 101196557A
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Abstract
The embodiment of the invention provides a method, a device and a system for testing the field programmable gate array, the method of which comprises that: the control chip receives the FPGA (field programmable gate array) and test the data of interface format recognized by the control chip output after the transformer of the related information; the control chip sends the data of interface format which can be recognized to the test computer; the control chip receives the control information sent by the test computer; the control chip sends the control information to FPGA. The embodiment of the invention solves the problems that the online test and remote test can not be achieved due to the limit of JTAG interface and the JTAG cable in length in prior art by the control chip on the veneer and the external communication interface.
Description
Technical field
The present invention relates to the integrated circuit fields technology, specially refer to a kind of methods, devices and systems of field programmable gate array test.
Background technology
Along with development of electronic technology, the more and more frequent use electronic message unit of people is handled various information flows and data stream, satisfies growing various demands.FPGA (Field Programmable GateArray, field programmable gate array) has obtained widespread use in the electronic message unit of various fields such as communication, data processing, network, instrument, Industry Control, military affairs and Aero-Space.FPGA is at PAL (Programmable Array Logic, programmable logic array), GAL (Generic ArrayLogic, generic array logic), the product that further develops on the basis of CPLD programming devices such as (Complex Programable Logic Device, CPLDs).It is as special-purpose ASIC (Application Specific Integrated Circuit, integrated circuit) a kind of semi-custom circuit in the field occurs, both solve the deficiency of custom circuit, overcome the limited shortcoming of original programming device gate circuit number again.The use of FPGA is very flexible, can produce different circuit functions with a slice FPGA by different programming datas.
The function that FPGA realizes is more and more, and its complexity is also in continuous rising.Whether this just need test FPGA work and normally and when the problem of generation test by test circuit, and then collect data help and analyze problems and solve them at the inner realization of FPGA test circuit.
At present, the system architecture synoptic diagram of the FPGA of prior art test as shown in Figure 1.There is test circuit 101 FPGA inside, is connected with test computer by JTAG (Joint Test Action Group, combined testing action group) interface cable 102, and the testing software module 103 that is used for the FPGA test is installed on the test computer.The tester finishes various tests by the test circuit of testing software module 103 control FPGA inside.
In carrying out process of the present invention, the inventor finds that there are the following problems at least in the prior art: the on-line testing difficulty, the FPGA test needs FPGA need be connected by the jtag interface cable with test computer, in equipment, disposed well and work as FPGA, the packaged or space layout reason owing to equipment, the FPGA interface cable is not easy to be connected on the test computer; Do not support remote testing, FPGA test needs FPGA need be connected by the jtag interface cable with test computer, and the connection limited length of jtag interface cable, needs more closely on the test computer and the FPGA device space to be measured, does not support remote testing.
Summary of the invention
The methods, devices and systems that embodiment of the invention technical matters to be solved provides a kind of field programmable gate array test are with the on-line testing difficulty that solves FPGA test in the prior art and and the problem of not supporting remote testing.
The embodiment of the invention provides a kind of method of field programmable gate array test, comprising:
Control chip receives on-site programmable gate array FPGA will test the interface format data that the described control chip exported behind the relevant information conversion form can be discerned;
The interface format data that the control chip transmission can be discerned are to test computer;
The control information that control chip acceptance test computing machine sends;
Control chip sends control information to FPGA.
The embodiment of the invention provides a kind of fpga chip, comprising: test circuit and interface modular converter;
Test circuit is used to export JTAG form test relevant information;
Interface modular converter is used to receive JTAG form test relevant information and is converted to the data of the interface format that control chip can discern.
The embodiment of the invention provides a kind of veneer, comprising: comprise fpga chip and control chip;
It is the interface format data that control chip can be discerned that this fpga chip is used for the conversion testing relevant information, and receives the control information that control chip is transmitted;
This control chip is used to receive the interface format data that control chip that fpga chip sends can be discerned, and transmits control information and give fpga chip.
The embodiment of the invention provides a kind of system of FPGA test, comprises fpga chip, control chip and test computer;
It is the interface format data that control chip can be discerned that fpga chip is used for the conversion testing relevant information, and receives the control information that control chip is transmitted;
Control chip is used to transmit the interface format data that control chip can discern and gives test computer, and the control information that the transmitted test computing machine sends is to fpga chip;
Test computer is used to receive the interface format data that described control chip can be discerned, and sends control information.
This shows, the embodiment of the invention is by control chip, and receive the interface format data that the described control chip of on-site programmable gate array FPGA output can be discerned by control chip, send to test computer by external communication interface then, the control information of transmitted test computing machine transmission simultaneously makes that to the test circuit of FPGA inside not making any change when the FPGA on the equipment veneer can't connect the JTAG cable also can finish remote testing; Simultaneously, control chip connects with test computer by external communication interface, has avoided the restriction of JTAG cable length, realizes remote testing.
Description of drawings
Fig. 1 is the system architecture synoptic diagram of prior art FPGA test;
The system architecture synoptic diagram that the realization FPGA that Fig. 2 provides for the embodiment of the invention tests.
Embodiment
The embodiment of the invention discloses a kind of methods, devices and systems of field programmable gate array test.
The embodiment of the invention is by increasing by an interface conversion function module in existing FPGA inside, the output of the jtag interface of test circuit is converted to another interface format to be connected with control chip on the veneer, control chip on the veneer with test computer communication, can well solve the problem of on-line testing and remote testing by external communication interface so then.
Below in conjunction with accompanying drawing the embodiment of the embodiment of the invention is done further and to be elaborated.
The system architecture synoptic diagram that the realization FPGA that Fig. 2 provides for the embodiment of the invention tests.
The following embodiment of the invention is control chip explanation the present invention with the CPU on the veneer.
The embodiment of the invention one is an example with the CPU on the veneer, and the method for FPGA test is described.As shown in Figure 2, there are test circuit 101 and interface modular converter 201 in FPGA inside, and be connected by intercommunication interface 202 with CPU on the veneer and communicate, simultaneously testing software module 203 is arranged in this CPU inside, communicate by letter with the testing software module 103 on the test computer by the external communication interface on the veneer 204, cooperate the test of finishing FPGA.
The method of finishing FPGA test mainly comprises: interface modular converter 201 with test circuit 101 outputs the test relevant information of JTAG data layout be converted to the data of the interface format that the CPU on the veneer can discern, make the CPU on the veneer to receive the interface format data that to discern through the CPU that exports after the format conversion, discern the relevant information of test circuit 101 transmissions and can control FPGA test circuit 101 by intercommunication interface 202.After the interface format data (promptly testing relevant information) that CPU on the veneer of the CPU reception on-site programmable gate array FPGA output on the veneer can discern, testing software module 203 in the CPU sends to test computer with the test relevant information of FPGA test circuit output by external communication interface 204, and test computer carries out dependence test by testing software module 103.
Simultaneously, the control information that testing software module 203 in the CPU sends by external communication interface 204 acceptance test computing machines, and the testing software module 203 in the CPU passes to this control information the test circuit 101 of FPGA inside by intercommunication interface 202 and interface modular converter 201.
At above-mentioned interface modular converter 201 data that the data of JTAG form are converted to the interface format that the CPU on the veneer can discern can be the data of multiple interfaces form, for example USB interface formatted data, serial interface formatted data etc. are so long as the data of the interface format that the CPU on the veneer can discern all can.
The external communication interface 204 of CPU on above-mentioned veneer can be communication interfaces such as Ethernet interface, serial ports, can as long as can finish the communication interface that the CPU on the veneer communicates by letter with test computer.
By said method as can be seen, present embodiment is by realizing online remote testing by the CPU on the veneer.Because on general veneer, all having CPU to control whole veneer, and FPGA or and CPU be positioned on the same veneer, perhaps on two very near veneers of distance, so the CPU on the veneer can control and manage FPGA.Simultaneously the data of the JTAG form of the test relevant information of test circuit are converted to the data of the interface format that the CPU on the veneer can discern, make that the CPU on the veneer can receive the relevant information that the identification test circuit sends at the interface modular converter of FPGA.Make when the FPGA on the equipment veneer can't connect JTAG cable (not welding or external packing sealing) or under occasions with limited space, do not need to make other changes (weld again or unpack) and also can realize testing i.e. on-line testing.Testing software in CPU inside as the agency of test computer testing software, makes the testing software of test computer can control the test circuit of FPGA inside indirectly.CPU on the veneer connects with test computer by external communication interface, the restriction of JTAG cable length, space constraint when avoiding using the JTAG cable to be connected with test computer, thus realized remote testing.
Method of testing of the present invention not only can realize in FPGA, also can be at other DSP (DigitalSignal Processor, digital signal processor) or ASIC (Application Specific IntegratedCircuit, special IC) chip internal realize.Control chip on the veneer not only can be that CPU also can be DSP, MCU (Micro programmed Control Unit, microprogram control unit), ASIC or other control chip.
The embodiment of the invention two also provides a kind of fpga chip, as shown in Figure 2, comprises test circuit and interface modular converter;
Test circuit is used to export JTAG form test relevant information;
Interface modular converter is used to receive JTAG form test relevant information and is converted to the data of the interface format that control chip can discern.
The embodiment of the invention three also provides a kind of veneer, comprises fpga chip and control chip, and wherein to be used for the conversion testing relevant information be the interface format data that can discern of control chip to fpga chip and receive the information that control chip sends; Control chip is used to receive the interface format data that control chip that fpga chip sends can discern and transmits control information to fpga chip.
The embodiment of the invention four also provides a kind of system of FPGA test, as shown in Figure 2, comprises fpga chip, control chip and test computer;
Fpga chip is used for the conversion testing relevant information to be the interface format data that can discern of control chip and to receive the control information that control chip sends;
Control chip is used for transmitting its interface format data that can discern by external communication interface and gives the control information of test computer and the transmission of transmitted test computing machine to fpga chip;
Test computer is used to receive the interface format data that control chip can discern and sends control information.
Wherein control chip also is used to control the test circuit of FPGA inside;
Above-mentioned control chip is: the CPU on the veneer, DSP, MCU or ASIC.
The said external communication interface is: Ethernet interface, serial ports or parallel interface.
More than lift preferred embodiment; the purpose, technical solutions and advantages of the present invention have been carried out further detailed description; institute is understood that; more than be the preferred embodiments of the present invention; not in order to limit the present invention; within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the method for a field programmable gate array test is characterized in that,
Control chip receives on-site programmable gate array FPGA will test the interface format data that the described control chip exported behind the relevant information conversion form can be discerned;
Described control chip sends the described interface format data that can discern to test computer;
Described control chip receives the control information that described test computer sends;
Described control chip sends described control information to described FPGA.
2. the method for claim 1 is characterized in that, the interface format data that described control chip can be discerned are:
The interface format data that the test relevant information of the JTAG form of the test circuit output of FPGA inside can be discerned by the described control chip of the interface modular converter conversion of FPGA inside.
3. method as claimed in claim 2 is characterized in that, the interface format data that described control chip can be discerned are: USB interface formatted data, serial interface formatted data or parallel interface data layout.
4. method as claimed in claim 2 is characterized in that, described control chip sends described control information and is specially to described FPGA:
Described control chip sends to described control information the test circuit of described FPGA inside by described interface modular converter.
5. as any described method of claim 1 to 4, it is characterized in that described control chip is: the CPU on the veneer, digital signal processor DSP, microprogram control unit MCU or application-specific integrated circuit ASIC.
6. a fpga chip is characterized in that, comprises test circuit and interface modular converter;
Described test circuit is used to export JTAG form test relevant information;
Described interface modular converter is used to receive JTAG form test relevant information, and is converted to the data of the interface format that control chip can discern.
7. a veneer is characterized in that, comprises fpga chip and control chip;
It is the interface format data that described control chip can be discerned that described fpga chip is used for the conversion testing relevant information, and receives the control information that control chip is transmitted;
Described control chip is used to receive the interface format data that control chip that fpga chip sends can be discerned, and transmits control information and give fpga chip.
8. the system of a FPGA test comprises fpga chip, control chip and test computer;
It is the interface format data that described control chip can be discerned that described fpga chip is used for the conversion testing relevant information, and receives the control information that control chip is transmitted;
Described control chip is used to transmit the interface format data that described control chip can discern and gives test computer, and the control information that the transmitted test computing machine sends is to fpga chip;
Described test computer is used to receive the interface format data that described control chip can be discerned, and sends control information.
9. system as claimed in claim 8 is characterized in that, control chip is transmitted the interface format data that described control chip can discern by external communication interface and given test computer, and described external communication interface is: Ethernet interface, serial ports or parallel interface.
10. system as claimed in claim 8 is characterized in that, described control chip is: the CPU on the veneer, DSP, MCU or ASIC.
Priority Applications (1)
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| CNA2007101725821A CN101196557A (en) | 2007-12-18 | 2007-12-18 | Method, device and system for field programmable gate array test |
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| CNA2007101725821A CN101196557A (en) | 2007-12-18 | 2007-12-18 | Method, device and system for field programmable gate array test |
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| CNA2007101725821A Pending CN101196557A (en) | 2007-12-18 | 2007-12-18 | Method, device and system for field programmable gate array test |
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| CN101419485A (en) * | 2008-11-24 | 2009-04-29 | 电子科技大学 | Function-variable portable computer mainboard |
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| CN101930052A (en) * | 2010-07-21 | 2010-12-29 | 电子科技大学 | Online detection fault-tolerance system of FPGA (Field programmable Gate Array) digital sequential circuit of SRAM (Static Random Access Memory) type and method |
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| CN101419485B (en) * | 2008-11-24 | 2014-12-31 | 电子科技大学 | Function-variable portable computer mainboard |
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| CN102549443B (en) * | 2009-10-08 | 2015-04-01 | 泰拉丁公司 | Programmable protocol generator |
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| CN106569124A (en) * | 2016-11-09 | 2017-04-19 | 中国空间技术研究院 | Universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays) |
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