CN100589208C - The test circuit that is used for multi-port memory device - Google Patents

The test circuit that is used for multi-port memory device Download PDF

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Publication number
CN100589208C
CN100589208C CN200610159394A CN200610159394A CN100589208C CN 100589208 C CN100589208 C CN 100589208C CN 200610159394 A CN200610159394 A CN 200610159394A CN 200610159394 A CN200610159394 A CN 200610159394A CN 100589208 C CN100589208 C CN 100589208C
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data
write
signal
bus
read
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CN1945746A (en
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许晃
都昌镐
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14Implementation of control logic, e.g. test mode decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry

Abstract

A kind of semiconductor memory apparatus comprises: read bus, be used to transmit reading of data; Write bus is used for transmission and writes data; And temporary data storage unit, be connected and read between bus and the write bus, and by the test mode signal control that during test pattern, is enabled.

Description

The test circuit that is used for multi-port memory device
Technical field
The present invention relates to a kind of semiconductor memory apparatus, more particularly, relate to a kind of test circuit that is used for testing the peripheral circuit of multi-port memory device.
Background technology
Usually, the most of memory device that comprises dynamic random access memory (DRAM) equipment is used for the Voice ﹠ Video housed device such as high-definition television (HDTV) and LCD (LCD) TV, and in the traditional field such as desktop PC, mobile computer and server.In view of the reason of the following stated, there are needs for the memory device that can satisfy the I/O method that is different from traditional I/O (I/O) method.Conventional I/O method can be to use the data transmission method of the single-port (that is parallel I/O interface) with a plurality of I/O pin groups (pin set).
Consider the shortcoming of parallel I/O interface, repeatedly attempt so that parallel I/O interface is become serial i/O interface.Serial i/O interface is the serial received external data via a spot of bus (bus line), and in inside with the data parallelization that is received.
Therefore, because serial i/O interface uses a spot of bus, so its manufacturing cost reduces.In addition, because serial i/O interface does not need to have the single-port of a plurality of I/O pin groups, so it is applicable to multi-port memory device.
Multi-port memory device comprises a plurality of ports, and each port is carried out independent operation.Therefore, multi-port memory device can be handled needed multitude of video of multimedia and voice data simultaneously.
Tradition DRAM equipment can be handled single operation owing to single-port, and therefore, it only may carry out another operation after finishing previous operation.Multi-port memory device can overcome the above-mentioned restriction of traditional DRAM equipment, makes that the application of multi-port memory device is further expanded.
In above-mentioned multi-port memory device, the high-frequency data processing logic is for being essential with the serial data parallelization and with the parallel data serialization.
When execution is used for operation that high-frequency data handles, when the fault relevant with included storage unit in the DRAM equipment occurs, be difficult to verify the operation of high-frequency data processing logic.In addition, when the time tolerance limit between the logical signal of high-frequency data processing logic was set to than compactness, the fault relevant with this time tolerance limit can occur.Therefore, need test circuit to verify that specific fault is relevant or relevant with the time tolerance limit of high-frequency data processing logic with the storage unit that comprises in the DRAM equipment.
Summary of the invention
Therefore, an object of the present invention is to provide a kind of semiconductor memory apparatus that is used under the high frequency situation, testing peripherals and does not consider the defective of storage unit.
Another object of the present invention provides and a kind ofly is used under the high frequency situation that test is used for carrying out the circuit of read operation and the semiconductor memory apparatus of not considering the defective of storage unit.
Another object of the present invention provides and a kind ofly is used under the high frequency situation that test is used for carrying out the circuit of write operation and the semiconductor memory apparatus of not considering the defective of storage unit.
According to an aspect of the present invention, provide a kind of semiconductor memory apparatus, comprising: read bus, be used to transmit reading of data; Write bus is used for transmission and writes data; And temporary data storage unit, it is connected and reads between bus and the write bus, and by the test mode signal control that during test pattern, is enabled.
According to a further aspect in the invention, provide a kind of multi-port memory device, comprising: a plurality of memory banks (bank); With a plurality of memory bank control logic circuits, be used to control the signal transmission between global I/O line and the memory bank, wherein the number of memory bank control logic circuit is corresponding to the number of memory bank, and described multi-port memory device is configured under the high frequency situation test peripheral circuit and does not consider the defective of storage unit, wherein each memory bank comprises temporary data storage unit, this temporary data storage unit is configured to reading shared data between bus and the write bus, and preserves these data based on test mode signal temporarily.
Description of drawings
According to the following description to preferred embodiment that provides in conjunction with the accompanying drawings, above and other objects of the present invention and feature will become clear, in the accompanying drawings:
Fig. 1 is the block scheme according to multi-port memory device of the present invention;
Fig. 2 is first memory bank shown in Figure 1 and the more detailed block diagram of the first memory bank steering logic;
Fig. 3 is according to the circuit diagram of first embodiment of the invention, temporary data storage unit shown in Figure 2;
Fig. 4 is the circuit diagram of the read/write control module shown in Fig. 2; And
Fig. 5 is according to the circuit diagram of second embodiment of the invention, temporary data storage unit shown in Figure 2.
Embodiment
Describe in detail according to test circuit exemplary embodiments of the present invention, that be used for the peripheral circuit of measuring semiconductor memory device hereinafter with reference to accompanying drawing.
Fig. 1 is the block scheme according to multi-port memory device of the present invention.For the ease of explaining, illustrate multi-port memory device with four ports and eight memory banks.Specifically, suppose that multi-port memory device has 16 Frame and carries out 64 (prefetch) operation of looking ahead.
As shown in the figure, multi-port memory device according to the present invention comprises first to fourth port PO RT0 to PORT3, first to the 8th memory bank BANK0 to BANK7, first and second overall I/O (I/O) line GIO_OUT and GIO_IN, first to the 8th memory bank control logic circuit BCL0 to BCL7 and the phase-locked loop pll.
Each of first to fourth port PO RT0 to PORT3 is carried out the serial communication with external unit independently.First to the 8th memory bank BANK0 to BANK7 is divided into top memory body BANK0 to BANK3 and bottom memory body BANK4 to BANK7, and described memory bank is divided by first to fourth port PO RT0 to PORT3, and the direction that follows is arranged.
The direction that first global I/O line GIO_OUT follows between top memory body BANK0 to BANK3 and first to fourth port PO RT0 to PORT3 is arranged, and the parallel transmission output data.The direction that second global I/O line GIO_IN follows between bottom memory body BANK4 to BANK7 and first to fourth port PO RT0 to PORT3 is arranged, and parallel transmission input data.
First to the 8th memory bank control logic circuit BCL0 to BCL7 controls the signal transmission between first and second global I/O line GIO_OUT and the GIO_IN and first to the 8th memory bank BANK0 to BANK7.Phase-locked loop pll is between the second port PO RT1 and the 3rd port PO RT2, and the generation internal clocking.In response to this internal clocking, internal command and input and output data are inputed to first to fourth port PO RT0 to PORT3.
Fig. 2 be as shown in Figure 1 the first memory bank BANK0 and the more detailed block diagram of the first memory bank steering logic BCL0.Other memory bank BANK1 to BANK7 and other memory bank control logic circuit BCL1 to BCL7 have the identical structure of structure with the first memory bank BANK0 and the first memory bank steering logic BCL0.
As shown in the figure, the first memory bank steering logic BCL0 comprises test pattern definition circuit 415 and command decoder 417.Command decoder 417 receives such as the internal command of enabling order (active command), reading order and write command, and generation is read marking signal RDEN and write marking signal WDEN.Test pattern definition circuit 415 produces the test mode signal TLCHECK of definition test pattern based on the test pattern setting of the operation that is used to verify the high-frequency data processing logic.
The first memory bank BANK0 comprises a plurality of data bus sensing amplifiers (DBSA) 405, a plurality of write driver 407, temporary data storage unit 409, decoding unit 410 and read/write control module 411.
Decoding unit 410 will read marking signal RDEN and write marking signal WDEN decoding from what command decoder 417 was exported, so that drive the particular word line WL of storage unit 413, and generation is used to drive the transistorized signal of specific YI.This YI transistor connects bit line BL and such as section (segment) I/O (I/O) line of data conveyer line.
Write driver 407 is carried out the write operation that writes data.DBSA405 amplifies from the reading of data of storage unit 413 outputs, and output has the data of the amplification of 64 output datas.
The tolerance limit of data is considered and write to read/write control module 411, to write marking signal WDEN delay scheduled time, be used to control the write signal WDRV of write driver 407 with generation, and receive and read marking signal RDEN, read signal IOSTBP with what generation was used to control DBSA 405.
Temporary data storage unit 409 is reading shared data between bus Q_BIO and the write bus Q_WTD, and preserves these data based on test mode signal TLCHECK temporarily.Read bus Q_BIO shared data between the first memory bank steering logic BCL0 and DBSA405, and between described a plurality of DBSA shared data, and, write bus Q_WTD is shared data between the first memory bank steering logic BCL0 and write driver 407, and between described a plurality of write drivers shared data.In detail, during test pattern, temporary data storage unit 409 will be temporarily saved as reading of data from the data that write of external source, and use the data of being preserved as the read/write data that are used to verify the high-frequency data processing logic.
Fig. 3 is according to the circuit diagram of first embodiment of the invention, temporary data storage unit 409 shown in Figure 2.Here, signal RX_D represents the data that write from the first memory bank steering logic BCL0, and signal DSTRBP represents the Data Labels signal of signal RX_D.
As shown in the figure, temporary data storage unit 409 comprises data input cell 505, shares control module 507 and first latch units 501 and second latch units 503.
Data input cell 505 receives and writes data RX_D, and the signal that is received is put on write bus Q_WTD.First latch units 501 is positioned on the write bus Q_WTD, and latchs and write the output of data RX_D as data input cell 505.Share control module 507 and read bus Q_BIO and share to put on and write data RX_D on the write bus Q_WTD.Second latch units 503 is positioned at and reads on the bus Q_BIO, and latchs to put on to read and write data RX_D on the bus Q_BIO.
In detail, data input cell 505 comprises the first phase inverter INV1, a PMOS transistor P1 and the 2nd PMOS transistor P2 and the first nmos pass transistor N1 and the second nmos pass transistor N2.
The first phase inverter INV1 makes and informs that the Data Labels signal DSTRBP that imports the moment (point) that writes data RX_D is anti-phase.The first nmos pass transistor N1 has the grid that receives Data Labels signal DSTRBP.The 2nd PMOS transistor P2 that is connected to the first nmos pass transistor N1 has the grid of the output that receives the first phase inverter INV1.The second nmos pass transistor N2 that is connected between the first nmos pass transistor N1 and ground voltage (VSS) terminal has the grid that reception writes data RX_D.A PMOS transistor P1 who is connected between the 2nd PMOS transistor P2 and source voltage (VDD) terminal has the grid that reception writes data RX_D.
Share control module 507 and comprise the second phase inverter INV2 and transmission gate (transfer gate) TG1.The second phase inverter INV2 makes test mode signal TLCHECK anti-phase.The data RX_D that writes that transmission gate TG1 will put in response to test mode signal TLCHECK on the write bus Q_WTD is sent to and reads bus Q_BIO.
Each of first latch units 501 and second latch units 503 comprises the phase inverter latch units that contains a plurality of phase inverters.
When test mode signal TLCHECK is logic level " low ", that is, during normal mode, only will writes data RX_D and put on write bus Q_WTD.
When test mode signal TLCHECK is logic level " height ", that is, during test pattern, transmission gate TG1 operation so that with read bus Q_BIO share put on write bus Q_WTD write data RX_D.At this moment, if from external source input reading order, then the first memory bank steering logic BCL0 will read marking signal RDEN and export read/write control module 411 to.Read/write control module 411 makes and reads signal IOSTBP inactivation (inactivate), and the enable signal of signal IOSTBP as DBSA 405 read in output.Therefore, do not export the data that write, but output is stored in and writes data RX_D in the temporary data storage unit 409 from storage unit 413.
As shown in Figure 3, when activating test mode signal TLCHECK, in multi-port memory device, carry out single write operation according to the temporary data storage unit 409 of first embodiment of the invention.
Fig. 4 is the circuit diagram that read/write shown in Figure 2 is controlled Unit 411.
As shown in the figure, read/write control 411 comprises write signal output unit 601 and reads signal output unit 603.
Write signal output unit 601 useful delay cells D ELAY1 realize that this delay cell DELAY1 will write marking signal WDEN delay scheduled time, so that the signal after the output delay is as write signal WDRV.
Reading signal output unit 603 exports and reads signal IOSTBP based on test mode signal TLCHECK.In detail, read signal output unit 603 and comprise the first phase inverter INV3 and the second phase inverter INV4 and NAND (with non-) door NAND1.The first phase inverter INV3 makes test mode signal TLCHECK anti-phase.NAND door NAND1 carries out the output of the first phase inverter INV3 and reads the NAND computing of marking signal RDEN.The second phase inverter INV4 makes the output of NAND door NAND1 anti-phase, so that signal IOSTBP is read in output.
As mentioned above, when activating test mode signal TLCHECK with logic level " height ", read signal output unit 603 and do not export and read signal IOSTBP, and when making test mode signal TLCHECK inactivation with logic level " low ", signal IOSTBP is read in output.Therefore, when activating test mode signal TLCHECK with logic level " height ", read/write control 411 prevents to amplify and export the data of storage unit during reading.At this moment, if the input write command then normally will write data RX_D and write to storage unit, be applied in write bus Q_WTD and read bus Q_BIO because write data RX_D.By reading of data during the compare test pattern and the reading of data during the normal mode, may find the fault among the DBSA405.
Fig. 5 is according to the circuit diagram of second embodiment of the invention, temporary data storage unit 409 shown in Figure 2.As a reference, when activating test mode signal TLCHECK, in multi-port memory device, carry out a plurality of write operations according to the temporary data storage unit 409 of second embodiment of the invention.Specifically, based on carry out described a plurality of write operation from the address signal of outside.Here, the number of address signal is corresponding to the number of pending write operation, and the number of the latch units in the temporary data storage unit 409 is also corresponding to the number of pending write operation.
As shown in the figure, temporary data storage unit 409 comprises data input cell 701, the first shared control module 703 and second shared control module 705 and the write bus latch units 707.Data input cell 701 receives and writes data RX_D, so that the data that received are put on write bus Q_WRD.Write bus latch units 707 is positioned on the write bus Q_WRD, and latchs and write data RX_D.First share control module 703 and second share control module 705 with read bus Q_BIO share put on write bus Q_WRD write data RX_D.
In detail, data input cell 701 comprises the first phase inverter INV5, a NOMS transistor N3 and the second nmos pass transistor N4 and a POMS transistor P3 and the 2nd PMOS transistor P4.
The first phase inverter INV5 makes and informs that the Data Labels signal DSTRBP that imports the moment that writes data RX_D is anti-phase.The first nmos pass transistor N3 has the grid that receives Data Labels signal DSTRBP.The 2nd PMOS transistor P4 that is connected to the first nmos pass transistor N3 has the grid of the output that receives the first phase inverter INV5.The second nmos pass transistor N4 that is connected between the first nmos pass transistor N3 and ground voltage (VSS) terminal has the grid that reception writes data RX_D.A PMOS transistor P3 who is connected between the 2nd PMOS transistor P4 and source voltage (VDD) terminal has the grid that reception writes data RX_D.
Write bus latch units 707 is the phase inverter latch units that comprise a plurality of phase inverters.
First shares control module 703 comprises a NAND door NAND2 and the 2nd NAND door NAND3, the first transmission gate TG2 and the second transmission gate TG3 and first latch units 709 and second latch units 711.The one NAND door NAND2 carries out the NAND computing of the test mode signal TLCHECK and the first test address signal TA_0.The 2nd NAND door NAND3 carries out the NAND computing of the test mode signal TLCHECK and the second test address signal TA_1.The first transmission gate TG2 transmits in response to the output of a NAND door NAND2 by what write bus latch units 707 latched and writes data RX_D.The second transmission gate TG3 transmits in response to the output of the 2nd NAND door NAND3 by what write bus latch units 707 latched and writes data RX_D.First latch units 709 latch be connected to the first transmission gate TG2 write data RX_D.Second latch units 711 latch be connected to the second transmission gate TG3 write data RX_D.
Second shares control module 705 comprises the second phase inverter INV6 and the 3rd phase inverter INV7, the 3rd NAND door NAND4 and the 4th NAND door NAND5 and the 3rd transmission gate TG4 and the 4th transmission gate TG5.
The second phase inverter INV6 makes from the first test mode signal TLCHECK0 of test pattern definition circuit output anti-phase.The NAND computing that the 3rd NAND door NAND4 carries out the output of the second phase inverter INV6 and reads marking signal RDEN.The 3rd transmission gate TG4 will be sent to and be read bus Q_BIO by the data RX_D that writes that first latch units 709 latchs in response to the output of the 3rd NAND door NAND4.
The 3rd phase inverter INV7 makes from the second test mode signal TLCHECK1 of test pattern definition circuit output anti-phase.The NAND computing that the 4th NAND door NAND5 carries out the output of the 3rd phase inverter INV7 and reads marking signal RDEN.The 4th transmission gate TG5 will be sent to and be read bus Q_BIO by the data RX_D that writes that second latch units 711 latchs in response to the output of the 4th NAND door NAND5.
Temporary data storage unit 409 shown in Figure 5 is to be used for write operation being carried out twice exemplary circuit, so the number of latch units (that is, two) is corresponding to the number of pending write operation.It will be evident to one skilled in the art that: the number of transmission gate, latch units and test address is corresponding to the number of pending write operation.
During test pattern, connect the corresponding person among the first transmission gate TG2 and the second transmission gate TG3 based on test address signal TA_0 and TA_1, make corresponding latch units preserve and write data RX_D.In addition, when the first test mode signal TLCHECK0 and the second test mode signal TLCHECK1 are logic level " low " according to test address signal TA_0 and TA_1, connect the corresponding person among the 3rd transmission gate TG4 and the 4th transmission gate TG5, make the data RX_D that writes that to have latched be sent to and read bus Q_BIO.
As mentioned above, in the present invention, will be from the outside write data storage in being connected write bus Q_WTD and reading in the temporary data storage unit between the bus Q_BIO, and subsequently during the test pattern that is used to test the peripherals except that storage unit, with the data of being stored as reading and write data.Therefore, might under the high frequency situation, find the faulty operation of peripherals and do not consider the defective of storage unit.
According to the present invention, by with the high-frequency data processing logic as coming effective analysis of failure and guarantee that the stable operation of semiconductor memory apparatus is possible with the irrelevant peripherals checking of storage unit.In addition, can shorten the time limit that is used to develop semiconductor memory apparatus, particularly multi-port memory device, thereby improve its competitive power.
The application comprises and korean patent application 2005-90857 number and 2006-41190 number relevant theme of submitting in Korea S Department of Intellectual Property on September 28th, 2005 and on May 8th, 2006, and the full content of described application is incorporated in this by reference.
Though described the present invention with reference to some preferred embodiment, it will be evident to one skilled in the art that: under the situation that does not depart from the spirit of the present invention that limits by described claim and category, can carry out various changes and correction.

Claims (34)

1. semiconductor memory apparatus comprises:
Read bus, be used to transmit reading of data;
Write bus is used for transmission and writes data; With
Temporary data storage unit is connected and reads between bus and the write bus, and by the test mode signal control that during test pattern, is enabled.
2. semiconductor memory apparatus as claimed in claim 1, wherein, temporary data storage unit comprises:
Data input cell is used for reception and writes data, and this writes the Data Labels signal in the moment of data based on the indication input, and the data that write that received are applied on the write bus;
First latch units is positioned on the write bus, is used to latch the data that write that put on this write bus;
Data transfer unit is used in response to test mode signal and will be sent to and be read bus by the data that write that first latch units latchs; With
Second latch units is positioned at and reads on the bus, is used to latch put on the data that write that this reads bus.
3. semiconductor memory apparatus as claimed in claim 2, wherein, data input cell comprises:
First phase inverter is used to make described Data Labels signal inversion;
First nmos pass transistor has the grid that receives described Data Labels signal;
The one PMOS transistor is connected to first nmos pass transistor, and has the grid of the output that receives first phase inverter;
Second nmos pass transistor is connected between first nmos pass transistor and the ground voltage terminal, and has the grid that reception writes data; With
The 2nd PMOS transistor is connected between a PMOS transistor and the source voltage terminal, and has the grid that reception writes data.
4. semiconductor memory apparatus as claimed in claim 2, wherein, data transfer unit comprises transmission gate, the data that write that are used for will putting in response to test mode signal on the write bus are sent to and read bus.
5. semiconductor memory apparatus as claimed in claim 1, wherein, temporary data storage unit comprises:
Data input cell is used for reception and writes data, so that in response to informing the Data Labels signal of importing this moment that writes data the data that write that received are applied on the write bus;
First latch units is positioned on the write bus, is used to latch the data that write that put on this write bus;
A plurality of first data transfer unit are used for based on test mode signal with from the test address signal of external source, will read bus in the middle of being sent to by the data that write that first latch units latchs;
A plurality of second latch units are positioned at described centre and read on the bus, are used to latch the data that write from the transmission of first data transfer unit; With
A plurality of second data transfer unit are used for based on test mode signal, test address signal and read marking signal, will be sent to and be read bus by the data that write that second latch units latchs.
6. semiconductor memory apparatus as claimed in claim 5, wherein, the number of first and second data transfer unit and second latch units is corresponding to the number of pending write operation.
7. semiconductor memory apparatus as claimed in claim 6, wherein, data input cell comprises:
First phase inverter is used to make described Data Labels signal inversion;
First nmos pass transistor has the grid that receives described Data Labels signal;
The one PMOS transistor is connected to first nmos pass transistor, and has the grid of the output that receives first phase inverter;
Second nmos pass transistor is connected between first nmos pass transistor and the ground voltage terminal, and has the grid that reception writes data; With
The 2nd PMOS transistor is connected between a PMOS transistor and the source voltage terminal, and has the grid that reception writes data.
8. semiconductor memory apparatus as claimed in claim 6, wherein, each of first data transfer unit comprises:
First logic gate is used for carrying out the NAND computing of test mode signal and the corresponding test address signal of described test address signal; With
First transmission gate is used for transmitting in response to the output of first logic gate by what first latch units latched and writes data.
9. semiconductor memory apparatus as claimed in claim 8, wherein, each of second data transfer unit comprises:
Phase inverter is used for making the output of first logic gate of correspondence first data transfer unit of described first data transfer unit anti-phase;
Second logic gate is used to carry out the output and the described NAND computing of reading marking signal of phase inverter; With
Second transmission gate is used for the output in response to second logic gate, transmits by what correspondence second latch units in described second latch units latched and writes data.
10. semiconductor memory apparatus as claimed in claim 1 also comprises the read/write control module, is used for producing based on test mode signal the write signal that reads signal and definition write operation of definition read operation.
11. semiconductor memory apparatus as claimed in claim 10, wherein, the read/write control module comprises:
The write signal output unit is used for and will writes the marking signal delay scheduled time, and exports signal after this delay as write signal; With
Read signal output unit, be used for exporting and reading signal with reading marking signal based on test mode signal.
12. semiconductor memory apparatus as claimed in claim 11 wherein, produces by the internal command of selecting from the group with the order of enabling, reading order, write command and combination thereof and to read marking signal and to write marking signal.
13. semiconductor memory apparatus as claimed in claim 11 wherein, reads signal output unit and comprises:
First phase inverter is used to make test mode signal anti-phase;
Logic gate is used to carry out the output and the described NAND computing of reading marking signal of first phase inverter; With
Second phase inverter is used to make the output of logic gate anti-phase, so that signal is read in output.
14. semiconductor memory apparatus as claimed in claim 11, wherein, the write signal output unit comprises delay circuit, and this delay circuit comprises even number of inverters.
15. semiconductor memory apparatus as claimed in claim 1 wherein, reads bus and is connected between a plurality of data bus sensing amplifiers, described amplifier amplifies reading of data, and the data that will amplify export external unit to.
16. semiconductor memory apparatus as claimed in claim 1, wherein, write bus is connected between a plurality of write drivers, and the said write driver will write data and be sent to storage unit.
17. semiconductor memory apparatus as claimed in claim 1 wherein, is provided with based on the external testing pattern and is produced described test mode signal by the test pattern definition circuit of definition test pattern.
18. a multi-port memory device comprises a plurality of ports, each port is carried out independent operation, and this multi-port memory device comprises:
A plurality of memory banks; With
A plurality of memory bank control logic circuits are used to control the signal transmission between global I/O line and the memory bank,
Wherein, the number of memory bank control logic circuit is corresponding to the number of memory bank, and described multi-port memory device is configured to test peripheral circuit under the high frequency situation, and do not consider the defective of storage unit,
Wherein each memory bank comprises temporary data storage unit, and this temporary data storage unit is configured to reading shared data between bus and the write bus, and preserves these data based on test mode signal temporarily.
19. multi-port memory device as claimed in claim 18, wherein, each of memory bank control logic circuit comprises:
Command decoder is used to receive internal command, and generation is read marking signal and write marking signal; With
The test pattern definition circuit is used for being provided with and the test mode signal of generation definition test pattern based on the external testing pattern.
20. multi-port memory device as claimed in claim 18, wherein, each of described memory bank also comprises:
A plurality of data bus sensing amplifiers are connected to and read bus, are used to amplify and export the reading of data of exporting from storage unit;
A plurality of write drivers are connected to write bus, are used to carry out write operation; With
The read/write control module is used for and will writes the marking signal delay scheduled time, is used to control the write signal of write driver with generation, and receives and read marking signal, is used for the signal that reads of the total line sensing amplifier of control data with generation.
21. multi-port memory device as claimed in claim 20, wherein, each of described memory bank also comprises decoding unit, be used for to read marking signal and write the marking signal decoding, so that drive the particular word line of storage unit, and generation is used to drive the transistorized signal of particular column, and described particular column transistor is used to connect bit line and section I/O I/O line.
22. multi-port memory device as claimed in claim 20, wherein, temporary data storage unit comprises:
Data input cell is used for reception and writes data, so that this writes the Data Labels signal in the moment of data based on the indication input, and the data that write that received is applied on the write bus;
First latch units is positioned on the write bus, is used to latch the data that write that are applied on the write bus;
Data transfer unit is used in response to test mode signal and will be sent to and be read bus by the data that write that first latch units latchs; With
Second latch units is positioned at and reads on the bus, is used to latch be applied to the data that write that read on the bus.
23. multi-port memory device as claimed in claim 22, wherein, data input cell comprises:
First phase inverter is used to make described Data Labels signal inversion;
First nmos pass transistor has the grid that receives described Data Labels signal;
The one PMOS transistor is connected to first nmos pass transistor, and has the grid of the output that receives first phase inverter;
Second nmos pass transistor is connected between first nmos pass transistor and the ground voltage terminal, and has the grid that reception writes data; With
The 2nd PMOS transistor is connected between a PMOS transistor and the source voltage terminal, and has the grid that reception writes data.
24. multi-port memory device as claimed in claim 22, wherein, data transfer unit comprises transmission gate, and the data that write that are used for will being applied in response to test mode signal on the write bus are sent to and read bus.
25. multi-port memory device as claimed in claim 20, wherein, temporary data storage unit comprises:
Data input cell is used for reception and writes data, so that this writes the Data Labels signal in the moment of data in response to the indication input, and the data that write that received is applied on the write bus;
First latch units is positioned on the write bus, is used to latch the data that write that are applied on the write bus;
A plurality of first data transfer unit are used for based on test mode signal with from the test address signal of external source, will read bus in the middle of being sent to by the data that write that first latch units latchs;
A plurality of second latch units read on the bus in the middle of being positioned at, and are used to latch the data that write from the transmission of first data transfer unit; With
A plurality of second data transfer unit are used for based on test mode signal, test address signal and read marking signal, will be sent to and be read bus by the data that write that second latch units latchs.
26. multi-port memory device as claimed in claim 25, wherein, each number of the number of first and second data transfer unit and second latch units corresponding to pending write operation.
27. multi-port memory device as claimed in claim 26, wherein, data input cell comprises:
First phase inverter is used to make described Data Labels signal inversion;
First nmos pass transistor has the grid that receives described Data Labels signal;
The one PMOS transistor is connected to first nmos pass transistor, and has the grid of the output that receives first phase inverter;
Second nmos pass transistor is connected between first nmos pass transistor and the ground voltage terminal, and has the grid that reception writes data; With
The 2nd PMOS transistor is connected between a PMOS transistor and the source voltage terminal, and has the grid that reception writes data.
28. multi-port memory device as claimed in claim 26, wherein, each of first data transfer unit comprises:
First logic gate is used for carrying out the NAND computing of the corresponding test address signal of test mode signal and described test address signal; With
First transmission gate is used for transmitting in response to the output of first logic gate by what first latch units latched and writes data.
29. multi-port memory device as claimed in claim 28, wherein, each of second data transfer unit comprises:
Phase inverter is used for making the output of first logic gate of correspondence first data transfer unit of described first data transfer unit anti-phase;
Second logic gate is used to carry out the output and the described NAND computing of reading marking signal of phase inverter; With
Second transmission gate is used for transmitting in response to the output of second logic gate data that write that correspondence second latch units by described second latch units latchs.
30. multi-port memory device as claimed in claim 20, wherein, the read/write control module comprises:
The write signal output unit is used for postponing the described schedule time with writing marking signal, and exports signal after this delay as write signal; With
Read signal output unit, be used for exporting and reading signal with reading marking signal based on test mode signal.
31. multi-port memory device as claimed in claim 30 wherein, reads signal output unit and comprises:
First phase inverter is used to make test mode signal anti-phase;
Logic gate is used to the NAND computing of carrying out the output of first phase inverter and reading marking signal; With
Second phase inverter is used to make the output of logic gate anti-phase, so that signal is read in output.
32. multi-port memory device as claimed in claim 30, wherein, the write signal output unit comprises delay circuit, and this delay circuit comprises even number of inverters.
33. multi-port memory device as claimed in claim 20 wherein, reads bus and is connected between described a plurality of data bus sensing amplifier, described amplifier amplifies reading of data, and the data that will amplify export external unit to.
34. multi-port memory device as claimed in claim 20, wherein, write bus is connected between described a plurality of write driver, and the said write driver will write data and be sent to storage unit.
CN200610159394A 2005-09-28 2006-09-28 The test circuit that is used for multi-port memory device Expired - Fee Related CN100589208C (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10566034B1 (en) 2018-07-26 2020-02-18 Winbond Electronics Corp. Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels

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US8103918B2 (en) * 2008-03-25 2012-01-24 Arm Limited Clock control during self-test of multi port memory
KR20140076128A (en) 2012-12-12 2014-06-20 에스케이하이닉스 주식회사 Non-Volatile Memory Apparatus and Operating Method Thereof, and Data Processing System Having the Same

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US6178532B1 (en) 1998-06-11 2001-01-23 Micron Technology, Inc. On-chip circuit and method for testing memory devices
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Cited By (1)

* Cited by examiner, † Cited by third party
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US10566034B1 (en) 2018-07-26 2020-02-18 Winbond Electronics Corp. Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels

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