CA2027799A1 - Method and apparatus for independently resetting processors and cache controllers in multiple processor systems - Google Patents

Method and apparatus for independently resetting processors and cache controllers in multiple processor systems

Info

Publication number
CA2027799A1
CA2027799A1 CA002027799A CA2027799A CA2027799A1 CA 2027799 A1 CA2027799 A1 CA 2027799A1 CA 002027799 A CA002027799 A CA 002027799A CA 2027799 A CA2027799 A CA 2027799A CA 2027799 A1 CA2027799 A1 CA 2027799A1
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CA
Canada
Prior art keywords
processor
reset
signal
reset signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002027799A
Other languages
French (fr)
Inventor
David A. Miller
Kenneth A. Jansen
Paul R. Culley
Mark E. Taylor
Javier F. Izquierdo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
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Publication date
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Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of CA2027799A1 publication Critical patent/CA2027799A1/en
Abandoned legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24Resetting means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177Initialisation or configuration control

Abstract

ABSTRACT

A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.

Description

METHOD AND APP~RATUS FOR INDEPENDENTLY

IN MUL~IPLE PROCESSC)R SYSTEMS . -This invention rel~tes to a method and apparatus for independently controlling and implementing the reset of the processors and cache memory system controllers in multiple proces~or computer sysl:ems utilizing cache memory.

Personal computer ~ystems have developed from systems 10 utilizing a ~ingle processing unit or CPU to systems which include multiple processors operating in parallel. One of the first developments was to include a s cond arithmetic coproces~or in parallel with the main CPU to perform time-co~suming a~d complex arithmetic tasks lea~ing the 1~ main CPU fre~ to perform ~ystem control, input/output, memory opera~ions and other less time-consuming code e~erution. Syst~ms incorporating the Intel ~0386 proces~or and 80387 coprocessor are one common e~ample of ~uch more a~vance~ ~ystems.

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In addition to the development of arithmetic coprocessors, memory ~ystems u ed by the processor have evolved ~rom ~ingle units of read only memory for storing fixed system i~structions and static random access integrated circuit memory to ~urther include peripheral memory devices ~uch as ~loppy-disk and fixed-disk memories and as~ociated interface and control cixcuity.
As the ~peed of processors was enhanced, it became necessary to enhance the ~peed at which memory operations could be performed ~o as to take advantage of the newer high ~peed processor~ 8uch as the Intel ~0386. ~igh speed ~tatic RAM devices were available, but to implement the entire memory requirement with high speed RAM was too ~xpensive for personal computer systems. one solution to the problem was the implementation of what is known as a cache memory system.
In 2 cache memory ~ystem a small amount of more expensive fast memory, typically static RAM devices, is u~ed for high ~peed execution and ~lower, less expensive dynamic RAM and peripheral devices are used for the bulk memory re~uirements. Data or code co~tained in portions of the main memory is duplicated in the fast cache memory ~o that operations requiring only data or code in cache memory can be e~ecuted quickly. Idealized cache memory ~ystems se~k to ~atch the upcoming processor code and data re~ue6t8 to code and ~ata maintained in cache memory by changing ~he ~ont~nts of ~he cache ~emory as the processor e~ecutes code or instructions to ~inimize the number of ~i~e~ slower ~emory has to be accessed ~y the processor.
Updating and maintaining the directory to the cache ~e~ory i~ p~r~or~e~ by a device known as a ca~he controller. One ~uch device i the Intel 82385 cache ~ontroll~r ~e~igned for use with the 80386 processor. The cache controller ~180 determine~ whether the re~uested - 35 data or code i8 re~id~nt in cache or whether it is necessa~y to retrieve ik for the processor from main ~emory. The c~che ~ontroller there~ore interfaces between , . . . . .. . . .;

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the processor and the cache memory and the main memory via one or more system busses. Detail~ of an example of such systems is ~et orth in the Intel system design handb~oks for the 80386 family, such as the Microprocessor and S Peripheral 8andbook Volume 1, specifically pages 4-292 through 4~353 of the October, 1988 reference ~anual.
Further development of personal computer 6ystems led to the design of systems including multiple processors, each having an associated cache memory and cache controller, as well as a coprocessor. In such systems one of the processors is typically the primary processor which controls and utilizes the other secondary processors. The Intel Microprocessor and Peripheral ~andbook at page 4-295 disclosed such a multiple processor system where each processor and associated cache system were connected to a common local bus which is then connected to a system bus.
In the Intel design, another device ~nown as the Intel 82380 32-bit DMA controller was also connected to the local bus and utilized to provide direct memory access control, interrupt control, timing, wait state generation, dynamic (non-cache) memory refreshing and processor reset control. In the Intel system, both processors and cache controllers interface to the system bus via a common local bus interface. A~ designed, the cache controllers and associated proces60rs were re~et by a common signal.
Resets are utilized to interrupt all system activity and bring all elements of the system to a known initialiæation ~tate. Resets are assigned the highest priority among 6ystem signals and when a reset signal is asserted, all activity ceases. In &0386 and earlier B0286 based ~ystems reset signals can be generated by hardware ~uch as a switch, by operator command via a keyboard or under program control. A hardware reset occurs when the ~ystem is first energized or turned on. Softw~re or program controlled resets are utilized by programmer~ ~or a variety of reasons.

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One example of ~he use o a programmed reset relates to ~etting ~he ~ode of the processor. Both 80236 and 80386 processors axe initialized in a ~ode known as ~he Real Mode. Real ~ode operation is t~pically o~ly utilized a~ a prelude to ~ystem operatio~ ~uch as during a ~ystem initialization sequence ~hich occurs on power up. Real Mode operation utilizes a ~ystem addressing scheme which is limited and greatly restricts the ability of the processor to address large memory &paces. In the 80386 Real Mode operation limits the proces or to one megabyte of addressable memory space. Typically, once initialization i~ co~pleted, the system transitions to Protected Mode. Protected Mode allows the processor to use virtual addressing to expand ~he ad~ressable memory to four terabytes.
In ~he design of the 80286 family it was not anticipate~5 that after system initialization it would be .
desirable to revert from Protected Mode to Real Mode, and consequently no provision was made to accomplish this under program control. Software ~esigned for the 80286 ~ystem frequently incorporated software initiated resets to cause the 80286 to reset in order to revert from Protected Mode to Real Mode. In order to maintain software compatibility with ~oftware desi~ned for 80286 25 ~ystems, i~ is nece~sary to acco~nodate ~oftware resets as a method of resetting the processor to Real Mode.
In prior art ~ystems u~ing multiple processors and cach~ controll~r~ co~nected via a common bu~ the utilization o~ a re6et ~ignal cau6ed all prscessor~ and cache controllerfi ~o reset. On reset the 82385 cache controller clears the cache ~emory by e~ecuting ~ cache flu~h op~ratisn which invalida~e6 all data ztored in the cache. When B2385 controllers are utilized in master ~ode, a reset causes the controller to latch ~he 80386 res~t values t~ the ~y~t~m bus interfac~ by emitting a pul~d output ~ignal on it~ addre~ clock pulse (BACP) ou~put pin. Thi~ result~ in the 82385 tryin~ to ac~uire :. ~ : ,. ~ ~ .
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control o~ ~he system bus. In situations where the reset is a ~oftware reset intended only to reset one processor, as distinguished from a power up, haxdware system reset, ~he prior art provided no simple and efficient way to avoid bus contention by the 82385 controllers which tried to acquire the bus while one of ~he non-reset processors was operating. In multiprocessor systems, it i desirable to i~dependently reset each processor. The prior art provides no suitable mechanism to meet this need.
The present invention addresses these shortcomings of prior art systems and provides a system wherein each processor may be reset independently under program control after ~ystem initialization. The present invention also provides a system for resettiny each processor independently without introducing cache memory incoherency. A cache ~emory incoherency may occur when more than ~ne de~ice has access to co~mon memory space.
In such situations, one device may make an alteration to data in memory which is not also made to the duplicated data in the cache memory.

The present invention provides a system of independently resetting processors in a multiprocessor cache ~emory environment. On power up, a hardware reset, all processors and cache memory devices are reset to inikialization ~alues. The cache controllers are reset only on hardware reset, and placed in a hold state after the proces~or reset si~nals are released. Since power up resets of the processors and cache con~xollers are syn~hronized, no bus contention results. After hardware re~et, when ~he secondary processors acknowledge a hold reque~t, ~he pri~ary processor i6 given ~ccess to ~he common processor or ho~t bus ~ntil system protocol ~etermines o~e of the other processors or ~y~tem elements, ~uch as ~he e~tended industry standard (EISA) bus in EISA
~ystems, reguire~ the bus.

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Software or programmed resets cause only the selected processor(s) and not the cache controllers to be reset.
Programmed resets are ~ynchronized to hold acknowledge signals from ~he processors ~o that resets do not occur S duriny program execution by one or more processors thereby avoiding any cache ~emory incoherency. The pri~ary proce~sor can be reset under program control consistent with existing 60ftware convention without effecting the operation of the cache controllers or the secondary processor~. The pri~ary processor may also be independently reset in response to a keyboard initiated - - in~truction. The ~econdary processors can be program reset by ~etting a reset bit located in a designated ~econdary processor control register addressable under 1~ progra~ control, or via the user interface keyboard, or by the primary processor. All processors are reset in response to system ~hutdown signals.

A better understanding of the present invention can be obtai~ed when ~he following detailed description of the preferred e~bodiment is considered in conjunction with the ~ollowing drawings, in which:
~igure 1 is a ~chematic block diagram of a portion of a computer system incorporating the present invention;
Figure 2 is a ~chematic block diagram of a portion of a co~puter ~y~tem incorporating ~he present invention;
Fi~ure 3 i~ a schemati~ diagram of one poxtion of the ~ystem ~hown in Figure~ 1 and 2; and Figure 4 i8 a schematic diagram of one portion of the 3G reset control circuit which forms a part of the system ~hown in Figures 1 and 2.
Figure 5 is ~ whematic diagram of a ~econd portion of the reset control ~ircuitry which ~orms a part of the ~y~tem ~hown in figures 1 and 2.
Figure 6 i6 a ~ch~matic block diagram illu6trating a portion of the ~y~tem shown in Figures 1 and 2.

:. . . ::' : ' i ' ' : ,' :i' ,~ ... 1 ,, .. ; , -Referring now to Figures 1 and 2, the letter C
designates generally a computer system incorporating the present invention, For clarity, system C is shown in two poxtions, with the interconnections between Figures 1 and 2 desisnated by reference to the circled numbers one to ten. System C is comprised of a number of block elements interconnected via three busses. Throughout this specification in signal mneumonics an asterisk following the signal descriptors indicates the signal is active at a logic low level.
In Figure 1, a dual processor cache memory computer ~ystem is d~picted. A primary processing unit P1 comprises a processor 20, a numerical coprocessor 22 and a cache ~emory controller 24 and associated logic circuits connected to a processor bus 26. Associated with cache controller 24 is a high speed cache data random access memory 28, cache memory map programmable logic circuit 30, non-cacheable cache memory map logic circuit 32, address exchange latch circuit 34 and data exchange transceiver 36. Associated with Pl also are local bus ready loqic circuit 38, next address enable logic circuit 40 and bus reque~t logic circuit ~2.
Pxocessor 20 is preferably an Intel 80386 ~icroprocescor. Processor 20 has its control, address and data line~ interfaced to processor bus 26. Coprocessor 22 i~ preferably an Intel 80387 numeric coprocessor interfacing with processor bus 26 and processor 20 in the conventional manner. Cache ram 28 is preferably a uitable high-speed static random access memory circuit which interfaces with the addr~ss and data elements of bus 26 under control of cache controller 24 to carry out reguired cache memory operations. Controller 24 is preferably an Intel 82385 cache c~ntroller confisured to operate i~ ~wo-way ~et associative master mode. Address latch 34 and data transceiver 36 interface the cache .. . . . .. ... . ..

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controller 24 with proces~r ~0 and provide a local bus interface between processor bus 26 and a host bus 44.
Circuit 38 i~ a losic circuit which provides a bus ready sig~al to control access to bus 26 and validate address infonmation. Enable cix~uit 40 is utili~ed by processor 20 to ~nable the next address of data or code to be utilized by .ub-system elements in pipelined address mode.
Circuit 30 is a programmable logic circuit which is utiliz2d by cache controller 24 to map data locations in cache ram 28. Non-cache~ble ~ap circuit 32 is utilized by processor 20 to designate areas of cache ram that are non-cacheable to avoid any cache memory incoherency for data or code at specified main ~emory locations. Bus request logic circuit 42 is utilized by processor 20 and associated elements to.request access to the system bus 46 in situation~ ~uch as when reguested data is not located in cache memory 28 and access to system main memory is required. (Fig. 2).
In the drawings, ~ystem C i~ configured having the processor bu~ 26, host bus 44 a~d extended industry standard bu~ 46. The details of ~he portion of the system illu~trated in Figure 2, and not discu~sed in detail below are not ~ignificant to the present inventio~ other ~han to illus~rate an example o~ a ~ully c:onfi9ured dual processor ea~he ~emory ~y~tem. The EI5A 6pecification version 3.1 i5 i~cluded in Appendix 1 to fully ~xplain the reguireme~t~ of ~n EISA ~ystem. The portion of ~ystem C
illustxated in Fig. 2 i~ es~entially ~ conventionally con~igur~d EISA sy~tem which includes the nece~sary bus 46, EIS~ bus controller 4B, data transceiver 50 and ddr~ss latch 52 to inter~ace bekween bus 46 and host bus 44. Al~o illustrated in Figure 2 i~ an integrated ~ystem peripheral 54, ~uch a~ ~he Intel 82380 DMA controller and i~t0grated ~yst~m ~upport peripheral~.
Circuit 54 include~ a direct ~emory acce~s controller 56 for controlling dire~t accos~ to ~ain ~emory ~8 ' ' : , '. ' ',"~ ':. '." ' . , .' .; , - , . ~ ,: : ~

~Fig. 1) by 6ystem elements via bus 44. Memory array 58 comprises a memory circuit array of ize suitable to accommodate the particular requirements of the system.
Circuit 54 also includes interrupt controllers 70, non-maskable interrupt logic 72 and system timers ~3 which allow control of interrupt signals and generate neces~ary timing signals and wait states in a conventional manner.
In the preferred embodiment, processor generated interrupt requests are controlled via dual interrupt control circuits emulating Intel 8259 interrupt controllers resident in system integrated peripheral circuit 54.
Circuit 54 also includes DMA arbi~-ration logic 76 which controls and arbitrates among system DMA re~uests.
Memory array 58 (Fig. 1) is preferably dynamic random access ~emory. Memory 58 interfaces with bus 44 via data buffer circuit 60 and memory controller circuit 62 in a conventional manner. Buffer 60 performs data transceiving and parity checking functions. Controller 62 interfaces wi~h memory 58 via an address multiplexer circuit which includes row address enable logic circuit 64 and column address circuit 66 in a conventional manner.
Arbitration for busses 44 and 46 is controlled by arbitration logic circuit 74.
Bus 46 includes ISA and EIS~ control elements 75 and 78, ISA and EISA data elements 80 and 82 and address elements 84, 86 and 88 in a standard EISA configuration.
System peripherals ar~ interfaced via X bus 90 in combination with the control element 75 from bus 46.
Control and data/address transfer ~or X bus 90 are facilitated by X-bus control logic 92, data transceiver 94 and ~ddress latch 96.
Attached ~o X bus 90 are various peripheral devices such a~ keyboard/mouse controller 98 which interfaces bus 90 with a ~uitable keyboard and mouse via connectors 100 and 102, respectively. Also attached to X bu~ 90 are real time clo~k cixcuit 104 and a read only memory circuit 106 which contains basic operations software for the system C

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and for 6ystem graphic~. A ~erial communications port lO8 is also connected to the system C via X-bus 90.
External memory and control interface, parallel printer and communications ports, and video ~upport circuits are provided in block circuit llO in a conventional manner.
Referring now ~ack to Figure 1, a secondary processor P2 i~ illustrated. Processor P2 is ~ duplicate of proceisor Pl and consequ~ntly it is not necessary to deicribe the individual element~ in d~tail. Eleme~ts of P2 are the same a~ corresponding ~lements of Pl and have been numbered 80 that elements o~ P2 bear numhers 120, l22, 124 etc. ~orresponding to elements 20, 22 and 24 in processor Pl.
Arbitration logic circuit 74 arbitrates reguests or access to host bus 44 among Pl, ~2 and the EISA DMA
controller. If one processor requires the host bus and the other processor has the host bus, but i~ inacti~e, arbitrater circuit 74 reguests the înactive processor to relin~uish ~he bus by asserting an a~tive si~nal on ~he processor's HOLD input line. When the inactive processor asserts a HOLD ACKNOWLEDGE (HLDA) re~ponse, control of the host bus ii granted to the re~uesting processor by deasserting i~ HOLD line. If one processor reguests the host bus while it is controlled by the EISA bus master, a CPUMI5S* 8i~nal is asserted to arbitrator 76 in ISP
circuit 5~. The EISA bus ~aæter maintains ~:ontrol until the ISP arbitrator deasserts its ~I EIOLD ;aignal whereupon arbi1:ration circuit 74 deassertæ its procesæor H ~IOLD
30 ~ignal and the requesting processors ~OLD line. If both rocessors are regue~ting c:ontrol oiE the bus and primary processor P1 i~ llo~ a~srting an interrlapt, the processor leaæ~-recently on ~;he buæ iæ gr~ted control. If both proeeæssrs are reguesting t:ontrol and Pl is a6~rting an 35 internlpt, Pl is granted control. If either pro~essor has control of host bus 44, it maintain~ control until a : : . . . .. . .

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~ .`3 reguest from the other processor or the EISA bus 46 is received.
Control of the host bus 44 by either processor Pl ox P2 is protected from interruption by EISA bus controller 48 by an EISA arbitration lnhibit timer resident in arbitration circuit 74. When control of host bus 44 is transferred to either processox Pl or P2, the timer is started and remains active for a period of time as specified in a read/write, input/output arbitration register to accommodate processor operation. As long as the timer is active, the processor with control of the host bus 44 will not be interrupted by a ~ HOLD from the EIS~ controller or the other processor's bus request;
processor P2 can ~till be interrupted by processor Pl if processor Pl is asserting its interrupt request.
The period of the inhibit timer is set by multiplying the basic clock period of processor P1 by two and by the value set i~ the arbitration register under program co~trolO At reset, the arbitrat:ion valuP is zero (no arbitration inhibit) and is subseguently adjusted depending upon program requirements.
EISA bus 46 requires access to host bus 44 during direct memory access operation and EISA bus master cycles.
The EISA bus controller 48 initiates a request for access to hos~ bus ~4 by asserting a H ~OLD signal to arbitration circuit 74. If the EISA inhibit timer is not active, or when the processor which controls the bus deasserts its bus reyuest, arbitration circuit 74 requests the bus by as~erting its ~OLD line to the controlling processor.
3~ When the controlling processor asserts its ~OLD
ACKNOWLEDGE ~ignal, acce~s to the host bus 44 is granted to ~he EISA bus 46 by the arbitration circuit asserting an active ~LDA acknowledge signal. Control by EIS~ bus 46 is thereafter ~aintai~ed until ~ ~OLD is deasserted. The H ~OLD 6ignal i~ ~ynchroni2ed to CLKl* ~P1 primary clock si~nal, negative component). HHLDA is ~ynchronized to CLKl* before being as~erted.

In the drawings, logic circuit lS0 designates generally proces~or control and communication application ~pecific integrated circuit which includes logic circuits necessary to generate a variety of interprocessor control ~nd communications signals. Circuit 150 includes circuitry to accomplish pxocessor reset requests and reset ~ignal generation for the primary and secondary proces~ors. Circuit 150 also includes a communication Input/Output re~ister for facilitating interpr~cessor communications and processor control. In the preferred embodiment an ei~ht-bit register is provided for each processor in the system. These registers are part of a processor control logic circuit for each processor. These registers can be ei~her input/output or memory mapped and are decoded from four pseudo address lines designat~d PRS3 to PRS0.
While circuit 150 is illustrated as a fiingle block, .it ~hould be understood ~hat functions performed in this logic circuit as well as other logic circuits described 20 generally herein can be distributed to other single purpose or multipurpose integrated circuits without departing from the present invention. The distribution of logic functions to one or more integrated circuits is largely a mattex of design choice wi~hin the ordinary skill in the art. In the preferred embodiment, the functions described herein as within circuit lS0 are physically located in portions of two separately packaged ~at~-arrays which integxate a number ~f ~ystem control and co~munications functions. These two gate-arrays also i~tegrate a number of other functions for the ystem C
~hown ~erein as 6eparste 6chematic blocks.

Referring now to Figure 3, a schematic block diagram of a psrtion of logi~ circuit 150 is illustrated. This portio~ o~ circuit 150 includes a bu i~terface 160, an addres~ decode cir uit 162, processor control logic .

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register ~elect circuit 164, progr~mmable reset or restart logic circuit 166, a reset control port 168, a real time clock circuit 170 ~nd a secondary processor interrupt control circuit 172. Additional processor control or ~ommunication function blocks may be included in this general scheme to accommodate other functions which are not relevant to the present invention.
Bus interface 160 connects circuit 150 to the designated elements of system busses. Line 174 represents the LA address lines of EISA bus 46. Line 176 represents the SA/ISA address lines of bus 46. Line 178 represents the data lines from X bus 90, and line 180 represents ~he control lines from EISA bus 46. This interface provides circuit 150 with acces to the data, address or control signals present on these system busses.
Decoder 162 rPceives combined address signals 31 to 0 and command (CMD) and Memory Input/output (MIO) signals via lines 174 and 176 and interface 160. Decoder 162 decodes these signals to produce a function select output 182. Decoder 162 consists of latches and decode logic u ed to select via output 182 the logic function required by the system C. Each block 164, 166, 168, 170 and 172 reguires an enabling select signal. Address inputs A 31. . O are completely decoded to select memory locations. Input/output locations are decoded from inputs LA (15..2) and (SA 1..0). Bus interface 160 and decoder 162 provide an eight bit ISA interface for system inpu Voutput operations and a sixteen bit EISA interface for memory locations both of which are utilized for system functions in addition to those germane to the present invention.
Logic circuit 164 contains the processor control logic ~PCL) register selects. Address inputs 15 through 0 and the MIO input are used to decode the PCL register 6elect8 which are lat~hed ~o output lines 184 referred to herein a~ processor register select (PRS) lines. In the preferred embodiment circuit 164 decodes processor control ..

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. -14-i 7 3 select ~i~nal~ in the form of actual addresses OC6A ~hex) and FC6A ~he~) to 6elect primary and secondary processOr control, respectively, and provides four bit pseudo ~ddre~ses 0100 and 0101 on PRS lines 184. The PRS pseudo S addresses are utilized to ~elect processor control re~isters resident i~ anoth~r circuit.
Logic circuit 166 i~ selected by system C to generate a RESTM T ~ignal which is utilized to reset the processors only, independent of the cache controllers and other ~ystem components which are reset for hardware system reset ~ignal~ only. This feature enables keyboard entry of a processor reset or, in conjunction with circuit 168, programmed independent processor reset, as described herein.
Restart logic circuit 166 consists of a state machine which monitors key~oard commands and data via address decode 162 and data line 186 which interconnects to the ~ystem keyboard interface via bus interface 160 and the X data bus 90. Circuit 166 intercepts keyboard commands which need to be processed locally before being passed ~o the keyboard processor or controller.
Keyboard controller c~mmands are writes to the keyboard ~ontroller at address 64 (hex). This command together with any data ~ignal on line 186 consisting of Fxx~O (h~x~ constitutes a Restart (processor reset). When this command/data signal is detected, circuit 166 causes a proces60r Re~tart ~ignal to be generated. The R start logic consists essentially of a counter whi~h generates tim2 d~lay~ based upon the bus CLK signal from the EISA
~0 6y~tem clock.
Every time a Re~tart command is received, circuit 166 cau~es a delay of fi~teen microseconds followed by the a~ertion of th~ RSTAR* out~ut ~active low) ~r a period of five micro econds, then returns the RST M * output to i~activ~, lo~ic high level. This RSTAR* signal is utilized by other circuitry described herein to restart ,;,,;

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7 ,' 3 the primary processor in re~ponse to programmed or keyboard command.
In some application software it may be desirabl2 to provide for programmed (as distinguished from keyboard~
processor Restart. One e~ample would be the need to cause the primary processor to revert from protected to real mode. System C provides for this function via circuit 168. Circuit 168 contains an eight-bit regi~ter at IO
address 0092 (hex) which controls lo~ic to disable Real-Time clock addresses 37-3F (hex) and activate proce~sor Restart logic 166. This eight-bit register may be utilized for other system control functions in addition to the Restart function.
After system reset, circuit 168 is disabled. Writing a logic value one to bit 5 of the Port 09~ register will enable the circuit. In the preferred embodiment, bit zero of ~he eight-bit register is utilized to initiate a processor restart. After system reset, bit zero is set to a logic zero value. Thereafter, writing a one to this bit will cause Restart logic 166 to generate a RSTAR* signal in the manner described above.
Circuit 170 is a real time clock interface circuit which is selectively enabled via address decode circuit 162 to allow read and write commands to access the real time clock 104 for a variety of purposes. For the purposes of the present invention it is only important to note ~hat upon ~ySteM reset, logic circuit 170 includes logic which prevents write or read commands to clock 104 from being interrupted for the cycle in progress. ;~

Referring now to Figure 4, ano~her portion of communication and control logic circuit 150 is illustrated in block diagram ~orm. Figure 4 illustrates the processor control circuit~ wi~hin circuit 15Q which relate to interproce 60r communication and reset, restart control f~tions. ~hi~ portion of circuit 150 includes PCL

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~16-circuits 185 and 188 which relate to control functlons for ~he primary processor Pl and ~econdary processor P2, respectively. ~t should be understood that additional PCL
circuits to support 4ther system processor~, i pr~sent, could be added but are not illustrat~d or Glarity.
Circuits 186 ~nd 188 interface wi~h processors P1 and P2, respectively.
Reset input 190 is a ~ynchronized ~y6tem Reset ~ignal which txansitions in phase 2 of the system ~lock signal.
Reset only goes to an active state i~nediately after power up. RSTAR* input 192 is utilized for r~star~ing the primary processor under program control. RSTAR* is input to circuit 186 only since programmed resets originating in application software are only used directly for the primary processor Pl. Programmed resets for ~econdary processors can be made by writing to a defined address in ~econdary processor register 213. The RSTAR* signal originates ~rom circuit 166 in Fig. 3.
A PHOLD output ~ignal is generated by circuit 150 as a pxocessor hold request t~ put 1~e æelected proc~ssor in hold prior to programmed reset o;r restart. PHOLDA input which originates with the processor is used by circuit 150 logic to ensure that the selected processor has no bus cycles in pro~ress when a progra~med reset or restart is initiated.
PRS input 202 originates with ~CL Register select circuit 164 in Fig. 3 and is ~ four-bit p~eudo ~ddress input ~ignal u6ed to decode one Gf fi~t~en eight-bit re~ister~ resident in circuits 186 and 18~ illustrated ~chematically as regi~ters 212 and 213 in Fiq. 4, Referring back to Figure 3, a processor control ~ignal to address OC6A ~hex) is decoded by ~ircui~ 164 which presents a 0100 ~ignal on PRS input lin~s 202. This pseudo address i~put on PRS lines 20~ ~elect~ register 216 for r~ad~write operatio~s depending on the ~tatu~ o~ W-R
input 217.

, : ., , . . .,....... , . ; ...... ~. .,:...... . . .

:, ~ ,:,,: . , ,, :. :

-17~

Primary processor register 216 may be used for a variety of control functions. For the purposes of the present invention, a primary processor control ~ignal which writes a logic level one to bit six of register 216 will result in an interrupt signal 214 being provided as an IRQ13 signal to the primary processor via integrated ~ystem peripheral ~ubcircuit 70. Bit six of register 216 is reset to zero on power up. Setting this bit ~o one causes a primary processor interrupt which allows the secondary processors to communicate with ~he primary processor. A r~gistex decode logic circuit 217 is provided to decode signals in registers 212. Decode circuit 217 interprets the values in register 212 depending on the value of Pl/P2 mode input 219. For the primary processor this input is hardwired to the Pl mode.
A secondary processor control register 218 is addressed at FC6A (hex) via circuit 164 which provides a decoded pseudo address of ~101 on PRS lines 202. Writing a logic level one value to bit zero of register 218 is decoded by decode circuit 219 to cause a ~econdary processor reset request to ~e initiated via reset logic described below. Register decodle circuit 219 decodes the contents of register 213 based upon the status of the Pl/P2 mode input, which is set to P2 mode for the secondary proces~ors. The PRS signal enables the secondary processor to be progr~nmably reset. The output of thi~ bit i~ not provided directly to the secondary proc~ssor but is utilized in the Reset/Restast logic circuit described below. Bit zero of register 218 powers up at zero value.
To enable a 6econdary processor interrupt, a one is written to bit 6 of register 218. This bit is reset to zero on power up. A P2 interrupt signal 220 is generated by circuit 219 in response to bit 6 of port 218 being set to one. Thi~ enables other system component~ including the primary proce~sor to communicate with the ~econdary proces~or, Bit ~even of register 218 is an interrupt : ` : ` `

;18- .~J ~ .J l ~ ~5 .

disable INTDIS bit which when set to one prevents the secondary processor rom interrupting the primary processor.
The ERESP output signal is the early reset signal for the processors only, as distinguished from the cache controllers 24 and 124, or o~her components such as the numeric co-processors. Output ERESP is generated in re ponse to programmed processor reset requests, keyboard resets, or in response to a system SHUTDOWN signal. The ERESP signal is also used to reset the processors in response to a hardware ~ystem reset as described below.
~ The ERESP 6ignal is resynchronized by E-PAL circuits 224, 226 associated with each processor control circuit 186, 188, respectively, to the falling edge of the system CLK1*
signal, which is the clock signal used internally by the processors. CLK1 is ~enerated by dividing the system clock ~ignal from clock 170 designated CLK2, by two. The resynchronization is necessary to meet the 80386 ~etup/initialization timing reguixements.

.
Referring now to Figure 5, the details of reset control logic circuit 230 shown in block diagram form in Figure 4 are illustrated. This circuit controls the genexation of re6et 6ignals for t~e processors only. A
~rocessor reset output ~ignal 23~ is provided in response to RSTAR*, P~ST or S~UTDOWN i~put ~ignals on lines 234, 236 and 238, respectively. Hardware sy~tem resets are received via input l90 and also cause a processor EXESP
reset signal to be generat~d. Circuit 230 is duplicated 30 in each processor control logic circuit 186, 188 etc.
associated with primary and ~econdary processors.
To ~acilitate ~ax ~anufacturing, circuit 230 is designed to receive either RSTAR* or PRS inputs depending upon whet:her the particular circuit 23û is used with a 35 primary proce sor control circuit or a secondary processor c:ontrol circuit. For primary processor control, the .

7 . ~
RSTAR* input is connected to the output of circuit 166 to enable primary processor programmed or keyboard initiated resets. ~or secondary processor control circuits, the RSTAR* input is not connected. Secondary processor programmed resets are initiated in response to the PRST
si~nal generated by a decoded secondary processor reset request from decode circui~ 219 in Figure 4. In all applications, a system SHUTDOWN input signal, which is generated by the system C in response to conditions indicative of major malfunctions, is treated as a programmed reset request.
Throughout the following detailed description, in accordance with industry practice, logic signals which are active at a low level will be identified with an asterisk following the signal identifier, such as RQ2*.

Hardware resets result from power on or other switched reset condi~ions as distinguished from programmed or keyboard initiated resets. It is not important to independently reset the processors on hardware reset because all system elements will be reset synchronously and no bus contention or cache incoherency will result.
In the present system, the system elements other than the processors, such as the cache controllers and numeric coprocessors, are reset by hardware reset in a conventional manner. The processors are also reset on hardware resets, but the reset signal for the processors is generated by an independent processor reset control circuit 230 which responds to the system hardware reset signal.
Referring now to Figure 5, the details of circuit 230 are illustrated. System reset signal RST is pro~ided as a reset signal to flip-flop 246 via inverter 2S2.
Consequently, output RESCPU* is set to an active low state. Output RESCPU* is provided as a D-input to flip-flop 248. Flip-flop 248 is clocked by clock signal ~;,': ~

-2~ 7 ~

MCLKl. MCLKl i~ generated by taking the NAND product of CLX2* and CLKl* to ~ynchronize the ERESP output to the gir~t pha~e of CLK1 u~ed internally by the processor.
Following Reset, ~ignal RST reverts to a low level, and on the first ZCLKlR pulse ~he RESCPU* and RESCPU signals are set to inactive high and low levels, respectively.
For a 80386 processor, system reset is reguired to be maintained active for at least 15 CLK2 periods or 78 CLK2 periods if a self test is going to be executed followlng reset. In the pr~sent ~ystem, the ERESP output will remain active in response to the RST 6ystem reset on terminal 190. RST is generated in o~her circuitry in the system C to comply wi~h processor reset reguirements.

Keyboard initiated, and software or program controlled resets of the processors independently from the other ~ystem elements is provided under the control of circuit 230, illustrated in Figure 5. After system reset, the output ~ignal~ of flip-flops 240, 242, 244, 246 and 248 are set to their respective inactive values. Signals RQ2*, RQl*, RQ0* and ~ESCPU* are inactive, high. The ERESP output of circuit 248 is inactive low. The ~HOLD
output of flip-flop 250 i8 inactive low. The output signal on line 258 of flip-flop 256 is inactive low, as 2~ are the other i~puts to OR~TE 260. The PRST input to ORGATE 2Ç0 i6 only active high in re~ponse to a secondary processor progr~mmed at keyboard initiated reset reguest.
The 5~UTDOWN input i~ only active high in response to a proces~or ~ignal i~dicative of ~ajor system malfunctions requiring ~ystem ~hutdown.
A pri~ary pro~e~sor progra~med or keyboard reset cause~ si~nal RSTA~* to be ~et ~o an active low lev~l.
The R~TAR* si~nal i~ provided 3~ a D-inpu~ to flip-flop 256. Flip-flop 256 is clock~d by signal ZCLKlR. ZCLKlR
35 i8 g~nerated a~ ~he output of N~NDGATE 271 which has the CLKl ~nd CL~2* ~ignalæ as inpu~s. CLKl is the clock , , . . :
.: . , ~ , , -. , ,' :'' ;, ; ~,. ~; .:

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' , : : ' ', : ,''' ;. ': , ,:, , .

~ :21 ~ r ~ ~ ~ ~ ~ 7 , `~

signal used i~ternally by the processor. CLK2 is the system clock which runs at twice the frequency of CLKl.
CLK2* is the inverse of CLK2. The NAND product of CLKl and CLK2* produces a ZCLRlR signal which is synchxonized to the second phase of CLKl. With RSTAR* active, the next ZCLKlR pulse sets output 258 to an active high level, thus initiating a programmed reset of the processor.
The high level signal at terminal 258 enables ORGATE
260, setting the input to ANDGATE 262 to a high level.
The second input to ANDGATE 262 is fixed high. Thus, the active RSTAR* slgnal causes the output of ANDGATE 262 to enable ORGATE 264, setting the R02 D-input to flip-flop 240 to an active high level.
With R02 high, the next ZCLKlR pulse sets the RQ2 and RQ2* outputs of flip-flop 240 to active high and low levels, respectively. Output signals RQ2*, RQl* and RQ0*
are provided as input signals to thxee-way NANDGATE 268.
When RQ2* is set low, the output of NANDGATE 268 is set high. This output is designated RESREQ and is provided as ~he input to inverter 269. Thus, ~he ~Q2* active low signal sets ~he output of inverter 269 to a logic high level. The output of inverter 269 is provided as a D~input to flip-flop 250, which !;ets its PHOLD output to an active high level on the next ZCLKlR clock pulse.
PHOLD i~ a processor hold reques1; si~nal used by circuit 230 to request that th~ processor be placed in a hold stats prior to and during a programmed reset to avoid interrupting ongoing processor bus cycles.
The high level active RESREQ output of gate ~68 is also provided as a first input to NAN~ATE 270. NANDGATE
270 i~ therefore enabled when the processor returns an active P~IDA signal, acknowledging the hold reguest, which enables ORGATE 272. Thus once ~he P~LDA ~ignal i5 active, the output of gate 270 is set active high. The output of gate 270 is provided a~ a D-i~put to flip-flop 246 so that on the nex~ ZCLKl~ pulse the RESCPU* output o~ flip-flop 246 i8 ~et to its a~tive low level. ~n active RESCPU*

signal initiates the generation of a synchronized ERESP
~ignal via flip-flop 248 as described above with regard to hardware resets.
For programmed resets, it is desirable to provide a reset ~ignal with a defined pulse width. It i~ therefore necessary to ~aintain the ERESP output signal active for a ~pecified period. To accomplish this, circuit 230 includes a three bit grey-code counter circuit comprised of flip-flops 244, 242 and 240 with associated logic gates. This circuit maintains the ERESP signal active for sixteen CLK2 counts to comply with ~he 80386 reset - requirements.
As described above, when a programmed reset is initiated the RESCPU output signal from flip-flop 246 is active high. This signal is provided as an input to ~NDGATE 274. Rt this time output RQ2* is low, and outputs RQ0*, and RQl* are at inactive high levels assumed after r~set. Th~se three outputs are provided as the inputs to ~ANDGATE 268~ The output ~ignal RESREQ of NANDGATE 268 will remain active high as long 21S one of signals RQ2*, RQl*, or RQ0~ is low. If RESRE5~ is active high, and ORGATE 272 is enabled, the RESCPU* output of flip-flop 246 will remain activ~ low, thereby maintai~ing the ERESP
6ignal active.
After a programmed re~et is active, the RESCPU ~utput of flip-flop 246 is ~et to an active high level. This ~i~nal is provided as an enablin~ input to ORGATE ~72.
NAND~ATE 270 will remain enabled after the ERESP reset ~ignal becomes active ~ntil ~he RESREQ output of NANDGATE
268 i~ ~t low. Thus, the duration of the ERESP a~tive ignal is controlled by ~he ~tatus of the RQ2*, RQl* and RQ0* inputs ~o N~NDGATE 268.
R2ferring back now to the input to ~NDGATE 274, when ~he RESCPU signal i8 ~c~ive high indicating ~he ~tart of a pro~r~med reset, ~he RQ2 and RQl* input~ are al~o high.
~Q2 wa~ ~et high ~t ~he beginning of the programmed reset cycle and RQl* remains high as a condition ~e~ ~f~er -~3-i'-J ~ 7 i s v hardware reset. Thus, the RESCPU high ~ignal enables ~NDG~TE 274, which disables NORGATE 276, which in turn disables ANDGATE 278, setting the input to flip-flop 244 low. On ~he next ZCLKlR 6ignal, outputs RQ0* and RQ0 will S be &et to active low and high levels, respectively.
This change in ~tate for RQ0* and RQ0 will cause the active RQ outputs of counter circuit designated generally as circuit 280 to be ~et high, corresponding to a binary eight and to count down so that only after ~ixteen CLK2 cycles or eight CLKl cycles will all three low outputs RQ0*, RQl* and RQ2* be at inactive high levels.
Once RQ0*, RQl* and RQ2* are all inactive high, NANDGATE 268 is disabled, RESREQ is set low and the ERESP.
signal becomes inactive in the manner described above.
As will be apparent when either the secondary processor reset signal PRST or the SHUTDOWN signal which are inputs to ORGATE 260 go to an active high level, circuit 230 causes a ERESP output from flip-flop 248 in the same manner as described above with respect to the RSTAR* primary processor programmed reset siynal.
Re~erring now to Figure B, the present invention provides a method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control, without causing cache controllers 24 or 124 to xeset. The processors 20 a~d 120 are reset via control circuit 150. Cache controllers 24 and 124, as well as coprocessors 22 and 1~2 ar~ reset by power on reset ~ignals only and are not effected by programmed or keyboard initiated resets. Programmed resets are detected and decoded via a bus interface and proce~sor select circuit 160 which interfaces with ~ystem host bus 44 and other bus~es.
Depending on the particular processor and bus timing in the sy~tem, it may be necessary to conditi~n the ERESP
processor reset signals prior to providing *hem to the processor reset input terminals. Generally, it is desirable not t~ reset the processors until ~ valid 6ystem : .:. . . . , , ~ :;

:;: :.: . :: ::: .- . : .: ;: : ~ .,: :
: , : :: ; : : - ;

-24- ~

power on condition existæ, and to coordinate the timing of processor resets with host bus reque ts and other system events. Such functions are t~pically carried vut by a programmed logic array circuit illustrated schematically as circuits 300 and 302, interfaced between circuits 186 and 188 and the respective processors. The design of such circuits is a matter of ordinary skill in the art and do not form a part of ~he present invention.

- . ', ! . . ~ :

Claims (14)

1. A computer system of the type adapted to operate in response to coded program instructions stored in system memory devices, the system including a primary and one or more secondary processors interfaced to a common system bus for executing program instruction, and wherein the system is initialized in response to a system reset signal, a processor reset control system comprising:
a. means responsive to the system reset signal for resetting the processors;
b. means for generating a primary processor reset signal;
c. means responsive to the primary processor reset signal for resetting only the primary processor.
2. The system of claim 1, wherein said means for generating a primary processor reset signal includes:
instruction reset means responsive to address coded instructions present on the system bus to determine that a primary processor reset has been requested.
3. The system of claim 2, wherein said instruction reset means comprises:
means for receiving address coded instructions and data via the system bus;
decoding means for decoding said program instructions to determine that a primary processor reset has been requested;
reset signal means responsive to said decoding means for generating a primary processor reset signal.
4. The system of claim 3, wherein said decoding means comprises:
an address decoding circuit for address decoding of program instructions;
a primary processor reset data register;
means for generating a register select signal for enabling said primary processor reset register to receive data in response to program primary processor reset instructions;
means for writing primary processor reset data to said processor reset data register.
5. The system of claim 4, wherein said reset signal means comprises:
means responsive to the status of data in said primary processor reset register for generating a primary processor reset initiation signal;
means responsive to the reset initiation signal for generating a processor hold request signal;
means for providing the processor hold request to the primary processor;
means for delaying the generation of the primary processor reset signal until the primary processor is in a hold state;
means for providing a reset signal to the processor.
6. The system of claim 5, further comprising:
reset timing means for maintaining the primary processor reset signal active for a specified period.
7. The system of claim 6, wherein said reset timing means comprises:
a counter circuit activated by the initiation of the primary processor reset signal;
means, associated with said counter circuit, for deactivating the primary processor reset signal after the specified time period has elapsed.
8. The system of claim 1, further comprising:
means for generating a secondary processor only reset signal;
means responsive to the secondary processor reset signal for resetting only the secondary processor.
9. The system of claim 1, further comprising:
means for generating a processor reset signal to reset all system processors in response to a system shutdown condition.
10. A computer system of the type adapted to operate in response to coded program instructions stored in system memory devices, the system including a processor for executing coded instructions, a system main memory for storing data and coded instructions, a cache memory for temporarily storing a duplication of a portion of the data and instructions stored in system memory for high speed access by the processor, and a cache memory controller interfacing with the processor, the cache memory and the main memory to determine whether instructions or data required by the processor are resident in cache memory, and wherein the cache controller and the processor interface via a system bus for transmitting data and system control signals, and where the system is initialized in response to a system reset signal, a processor reset control circuit comprising:
a. means responsive to the system reset signal for resetting the processor and the cache controller;

b. means responsive to program instructions for generating a processor reset signal;
c. means responsive to the processor reset signal for resetting the processor only.
11. The system of claim 10, wherein said means for generating a processor reset signal includes:
means responsive to address coded instructions present on the system but to determine that a processor reset has been requested.
12. The system of claim 11, wherein said instruction responsive reset means comprises:
means for receiving address coded instructions and data via the system bus;
decoding means for decoding program instructions to determine that a processor reset has been requested;
reset signal means responsive to said decoding means for generating a processor reset signal.
13. The system of claim 12, wherein said decoding means comprises;
an address decoding circuit for decoding the address of program instruction;
a processor reset data register;
means responsive to said decoding circuit for enabling said processor reset register to receive data in response to processor reset instructions;
means for writing processor reset data to said processor reset register.
14. The system of claim 13, wherein said reset signal means comprises:
means responsive to the status of data in said processor reset register for generating a processor reset initiation signal;
means responsive to the reset initialization signal for generating a processor hold request signal;
means for providing the processor hold request signal to the processor;
means for delaying the generation of a processor reset signal until the processor is in a hold state;
means for providing a reset signal to the processor.
CA002027799A 1989-11-03 1990-10-17 Method and apparatus for independently resetting processors and cache controllers in multiple processor systems Abandoned CA2027799A1 (en)

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US5465360A (en) 1995-11-07
EP0426366A2 (en) 1991-05-08
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