CA1211854A - Shared resource lockout operation method and apparatus - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A system having a plurality of units includes a shareable unit which is shareable between two or more of the other units. Lock apparatus is provided in the shareable unit to allow a first unit to lock the shareable unit so that no other unit attempting to lock the shareable unit will be permitted access to the shareable unit. The lock apparatus includes means that permit two units desiring to lock the shareable unit to make simultaneously asynchronous requests to lock the shareable unit. The lock apparatus further includes means to permit the unit which has locked the shareable unit to unlock the shareable unit so that it becomes available for a subsequent lock by a unit. The lock apparatus also includes means to allow the shared unit to be accessed by other units not attempting to lock the shareable unit even when the shareable unit is locked.

Description

lZl 18 5 4 BACKGROUND OF TH~ INVENTION

Field of the Invention The present invention generally relates to data processing systems and more part~cularly to a lock operation which provides that one user, of a possible plurality of users, of a sha~ed resource is ~iven exclusive use of the shared eesource during the period of time in which the shared resoucce is locked.

~n a system havinq a plurality o~ dev~ces coupled to a ~hare~ resource, an ordecly sy~tems mu~t lDe pro~J~ded by which one of the user devices may obtain the exclusive use of the hared resource for certain types of operations.
During this period of exclu~ive use by one of the devices performing an operation which requires exclusivity, the lS other device wishing to perform an operation which also requires the exclusive use of the shared resource. This problem becomes more complicated when such devices include, for example, one or more data proces~ors, one or more memory units, and variou~ type~ of peripheral devices ~uch as magnetic tape storage device~, disk storage device~, card reading equipment and the like.

~,~

Description of the Prior Art Various methods and apparatu~ are known in the prior art for interconnecting such a system. Such prior art systemQ range from those having common data bus paths to those having speci~l paths between various devices. Such systems also may include a capacity for either synchronous or asynchronous operation in combination with the bus type. Some such systems, independent of the manner in which such devices are connected or operated, require the data processor to control any such data transfer on the bus even though, for example, the transfer may be between devices other than the data processor.

One such structural scheme is shown in U.S. Patent 4,000,485 entitled, ~Data Processing System Providing Lock Operation of Shared ResourceQ~. This patent describes a data processing system in which the shared resource is the main memory which is connected to a common bus over which all transfers to and from device controllers and the central processing unit occur. In this system, if the central processing unit wants to perform a read-modify-write operation on the contents of the location in main memory, the data processing system first locks the main memory containing the location to be read and updated so that during the multiple common bus cycles required to first read a memory location and then write it ~Z~8~
-4- . .

back can be performed uninterrupted without another central processing system or device controller being able to perform another lock operation until the first lock operation haR been completed. In this system, although the common bus is an asynchronous bus (any device wishing to make a transfer over the common bus may asynchronously request use of the bus at any time, if the bus is not already in use) there is a priority resolver such that the lock mechanism associated with the shared resource need not be able to handle the case in which the shared resource is being locked by a first requester and a second loc~ reguest is made asynchronou~ly from a second requester wishing to perform a lock operation on the shared resource.

With the development of dual ported memories, it has become possible that multiple users may be making simultaneous reque3ts to perform a lock operation on the shared resource. For example, if one port is connected to the common bus which connects device controller~ to the main memory and the second port i8 connected to the central processing unit, it i~ possible that a device controller may be attempting to perform a lock operation on the main memory at the same time that the central proce~or wants to perform a lock operation. Therefore, what is needed i-~ a lock mechanism for a shared resource . _5_ -in which competing asynchronous requests from multiple reque8ters to lock or unlock the shared resource can be handled.

121~ 4 OBJECTS OF T~E INVENTION

Accordingly, it i~ an object of the present invention to provide an improved locking mechani~m for shared resources in which ~ultiple asynchronou~ request~ to lock a shared resource may be re~olved.

It is a ~till further object of the present invention to provide a low co~t locking mechanism for shared re~ource~.

Thi~ invention is pointed out with.particularity in the appended claim~. An understanding of the above and further objects and advantage~ of this invention can be obtained by referring to the following de wription taken in conjunction with the drawings.

--7 ~

SUMMARY OF THE_INVENTION

The above and other objects of the invention are obtained by providing lock logic within a data processing system comprising a plurality of units coupled by mean~ of a common bus to transfer information between any two of the plurality of units. The plurality of units includes at least a first and second unit, the first unit being a resource capable of being shared by at least the second unit and a third unit and wherein the second unit and third unit operate a3ynchronously with respect to one another and both are capable of making requests for the uninterrupted use of the first unit. A first storage means is included in the fir~t unit for storing a lock signal from the second unit or any other unit of the plurality of unit~, the lock signal indicating that the second or other unit which is3ues the lock signal desires uninterrupted access to the fir~t uni~. A second storage means is provided in the first unit for storing an indication that the third unit desirec uninterrupted acces~ to the first unit. A third storage means is provided which s~ores the indication of th0 second stcrage means at the time the second unit presents the lock signal. Logic is further provided in the first unit which is responsible to the indication of the first storage means and the third storage mean~ to generate a po~itive lZ~1854 --8-- .

acknowledge~ent to t~e second unit if, when the second unit re4ue~ts uninterrupted access to the ~hared unit, neither the first storage mean~ nor the third storage means indicate that uninterrupted access to the shared resource has been requested. This same logic also generates a negative response to the second unit if when the second unit presents the lock ~ignal, either the first storage means or the third storage means indicates that uninterrupted access to the shared resource has been requested . Log ic is al~o provided to store.the status of the lock signal in the first storage means whenever a positive acknowledgement is generated to any of the plurality of units on the common bus. Purther logic is included in the first unit that is responsive to an unlock signal such that the first storage means will be reset if a positive acknowledgement is generated by the first unit in response to a unlock signal presented by any of the plurality of units on the common bus. Logic is also provided which inhibits the third unit from gaining access to the first unit if the fir~t storage means indicates that a unit9 of the plurality of units desires uninterrupted access to the shared unit. Further mean~ is provided for resetting the second storage means once the ~econd unit has completed the operation which requires uninterrupted access to the shared unit.

~2~354 - 8a -In accordance with the present invention, there is pro-vided a lock apparatus for use in a system having a plurality of units, a shared unit of said plurality of units capable of being accessed by a first unit and a second unit of said plurality of units, said first unit and said second unit operating asynchronously with respect to one another, said lock apparatus comprising:
A. first lock request receiver means, included in said shared unit, for receiving a first lock signal, said first lock signal indicating that a unit of said plurality of units which trans-mitted said first lock signal, desires uninterrupted access to said shared unit such that no unit of said plurality of units can perform a lock operation on said shared unit during the time said shared unit is locked by another unit of said plurality of units;
B. first lock storage means, included in said shared unit and coupled to said first lock request receiver means, for storing an indicator that said first lock signal has been received when an access permitted signal is received;
C. second lock storage means, included in said shared unit, for unconditionally storing an indicator that said second unit desires uninterrupted access to said shared unit such that no other unit of said plurality of units can perform said lock operation on said shared unit during the time said shared unit is locked by another unit of said plurality of units;
D. synchronization means, included in said shared unit and coupled to said first lock request receiver means and to said second lock storage means, for storing said indicator of said ~2~1854 - 8b -second lock storage means when said first lock control signal is received by said first lock request receiver means; and E. response means, included in said shared unit and coupled to said synchronization means and said first lock storage means, for generating an access denied signal if said first lock signal is received and if said first lock storage means indicates that said first lock signal has been received or if said synchronization means indicates that said second lock storage means indicates that said second unit desires uninter-rupted access to said shared unit, said response means for generating said access permitted signal if said first lock signal is received and if said first lock storage means does not indicate that said first lock signal has been recei~ed and if said synchronization means does not indicate that said second lock storage means indicates that said second unit desires uninterrupted access to said shared unit.
In accordance with the present invention, there is alsoprovided a system comprising a plurality of units coupled by means of a common bus to transfer information between any two of said plurality of units, a shareable unit of said plurality of units capable of being accessed by any other unit of said plurality of units, said shareable unit also capable of being accessed by a main unit by means other than said common bus, said system capable of having a one of said plurality of units and said main unit making simultaneous asynchronous requests for access to said shared unit, said shareable unit including lock operation logic comprising:

~21i85~
- 8c -A. first means for receiving a first lock signal by means of said common bus from said one of said plurality of units which desires uninterrupted access to said shareable unit;
B. first bistable means, coupled to said first means for receiv-ing, for indicating in response to a positive acknowledgement signal being generated by a response means that said share-able unit is being accessed by said one of said plurality of units from which said first lock signal has been received;
C. second bistable means, for indicating that said main unit desires uninterrupted access to said shareable unit;
D. third bistable means, coupled to said second bistable means, for storing the ind~cator of said second bistable means when said first lock signal is received; and E. response means, coupled to said first bistable means and said third bistable means, for generating a positive acknowledgement signal to said plurality of units over said common bus if said first bistable means and said third bistable means do not indicate that any unit desires uninterrupted access to said shareable resource when said first lock signal is received and for generating a negative ac~nowledgement signal to said plurality of units over said common bus if either said first bistable means or said third bistable means indicates that one of said plurality of units or said main unit desires uninter-rupted access to said shareable resource.
In accordance with the present invention, there is also provided a method for inhibiting access to a shared resource within 12~1854 - 8d -a system having a plurality of units operating asynchronously with respect to a main unit, said main unit and a one unit of said plurality of units capable of simultaneously requesting uninter-rupted access to said shared resource, said method comprising the steps of:
A. allowing said main unit to unconditionally set a first indicator that said main unit desires uninhibited access to said shared resource;
B. receiving a first lock signal from said one unit indicating that said one unit desires uninterruptable access to said shared resource;
C. synchronizing said main unit's request and said one unit's request for uninterrupted access to said shared resource by storing the status of said first indicator in a second indicator when said first lock signal is received;
D. generating a positive response to said one unit when said first lock signal is received if said second indicator does not indicate that said main unit desires uninterrupted access and if a third indicator does not indicate that said first lock signal has been received;
E. generating a negative response to said one unit when said first lock signal is received if said second indicator indicates that said main unit desires uninterrupted access to said shared resource or if said third indicator indicates that said first lock signal has been received; and F. storing said indication that said one unit desires uninter-rupted access to said shared resource in said third indicator if said positive response is generated.

12~18~
- 8e -In accordance with the present invention, there is also provided in a data processing system having a plurality of first type units and a second type unit wherein said second type unit is adapted to be utilized by all of said first type units, wherein when one of said first type units performs a particular kind of operation (lock operation) utilizing said second type unit the others of said first type units must be prevented from performing said particular type of operation, and wherein when one of said first type units requires to perform said particular type of operation it generates a corresponding request signal (BSLOCK, SETLCK); apparatus for controlling said second type unit to appro-priately respond to only one ofsaid request signals, characterized by:
a first storage element for receiving a request signal (BSLOCK) from one of said first type units and, when enabled by a first signal (MEACKR) which denotes that said second type unit is in a state to accept said request, storing a representation that said request has been granted;
a second storage element for receiving a request signal (SETLCK) from another one of said first type units and, regardless of the state of said second type unit, storing a representation ~hat said other first type unit has made such a request;
a third storage element for receiving a signal corresponding to the representation stored by said second storage element and, when enabled during a time (BSDCNN) in the cycle of operation of said first type units in which a request signal may be supplied to - 8f -said first storage element, storing a representation that the request represented by the signal of said second storage element has been granted; and a logic circuit coupled to said first and third storage elements and responsive to signals ~LOCKDD, LOCKED) corresponding to the representations held therein for (i) enabling generation of said first signal (MEACKR) if neither said first storage element nor said third storage element holds a representation that a request has been granted or (ii) preventing generation of said first signal if either of said first or third elements holds a representation that a request has been granted.

BRIEF DESCRIPTION OF ~HE DRAWINGS

The manner in which the method of the present invention is performed and the manner in which the apparatus of the present invention is constructed and its mode of operation can best be understood in light of the following detailed description .together with the accompanying drawings in which like reference numbers identify like elements in the several figures and in which:

PIG. 1 is a general block diagram of a data processing system containing the lock logic of the pre~ent invention;

FIGS. 2 through 6 illustrate the format of various information transferred over the common bus of the data processing system of PIG. l;

FIG. 7 illu~trates a timing diagram of the operation of the bus of the data processing system of ~IG. l;

FIG. 8 illustrates a logic diagram of the lock logic of the present inventiont FIG. 9 illustrate~ a timing diagram of an example operation of the lock logic of FIG. 8; and --10-- , FIG. 10 illustrates a block diagram of the microoperations performed by the CPu of the data processing system of FIG. 1 when performing a lock memory operation using the lock logic of FIG. 8.

i21~854 DESCRIPTION OF THE PREFE~RED EMBODIMENT

DATA PROCESSING SYSTEM CONTAINING TaE LOCK LOGIC
FIG. 1 shows a data proces~ing system of the preferred embodiment which comprises of a CPU/memory board 100, memory module 1 101, memory module 2 102, a first I/O
controller 103 with an attached I/O device 105 and a second I/O controller 104 with an attached I/O device 136, and common bus 107. In FIG. 1, the thinner lines connecting the various components are control lines and the thicker lines connecting the components are data/address lines.

CPU/memory board 100 is a single printed circuit board which connects to common bus 107. CPU/memory board 100 contains both the CPU logic 108 and the memory controller logic 109. There is no main memory contained within CPU/memory board 100. The main memory for holding data and software instructions is provided by connecting one or more memory modules such as memory module 1 101 and memory module 1 102 to CPU/memory board 100. All requests to acce~s the main memory contained in memory module 1 and memory module 2, which can be from either the CPU or an I/O controller, are via memory controller logic 109.
Memory controller logic 109 is dual ported. One port connects to common bus 107 so that memory requests and data transfers can be made by either I/O controller 103 or ~21185~

I/O controller 104 via common bus 107. Requests for memory from the ~PU logic 108 fGr data or software instructions normally take place directly between CPU
logic 108 via the second port of memory controller logic 109 without going yia common bus 107.

Within the preferred embodiment, each memory module 101 and 102 can contain, for example, 256K (lR = 1024) words of main memory. In the preferred embodiment, each word of memory contains 1~ bits of data which can also be addressed as two 8-bit bytes. In the preferred embodiment, the memory is comprised of MOS se~iconductor chips with each location in memory actually containing 22 bits of information. Sixteen of the bits are used for the 16 bits of data in the word and 6 bits are used for error lS detection and correction (EDAC). Each memory module is a separate physical printed circuit board which contains 88 MOS memory chips of 64~ bits each. Memory controller loglc 109 is comprised of lock logic 110, priority resolver 111, and refresh logic 112. In addition, memory controller logic 109 contains timing, error detection and correction logic and chip addressing logic which is not shown in FIG. 1.

Lock logic 110 is provided to lock the main memory under the command of either the CPU or an I/O controller against another lock operation being performed by either ~llB~

an I/O controller or the CPU until the main memory is unlocked.
Priority resolver lo~ic 111 is provided to resolve competing requests for access to main memory. Priority must be resolved between main memory access requests originating: from the CPU 108, from an I/O controller 103 or 104 via common bus 107 or from refresh logic 112.
Priority resolver logic 111 is designed such that each time the main memory becomes available, a resolution cycle takes place that examines all three possible sources of access requests and will assign the main memory first to a request from refresh logic 112. If no refresh request is present, it will assign the main memory to a request from common bus 107 which originated from an I/O controller. If neither a refresh request nor a bus request is present, it will assign the main memory to the CPU 108 if it is making a request. Refresh logic 112 is provided to periodically perform a refreshing of the data stored in the volatile MOS memory ships of memory module 1 101 and memory module 2 102.
BUS REQUEST AND RESPONSE CYCLES
The common bus 107 of the system of the preferred embodiment provides a communication path between two units in the system. The common bus 107 is asynchronous in design enabling units of various speeds connected to the bus to operate efficiently in the same system. The design of the bus of the present invention permits communications including memory transfers, interrupts, data, status and command transfers. For a further description of ; ~

12~

the bus and interface logic of such system, U.S. Patents, Nos.
3,993,981, issued on November 23, 1976 and 4,236,203, issued on November 25, 1980, should be consulted.
The common bus 107 permits any two units to communicate with each other at a given time via common shared signal paths.
Any unit wishing to communicate, requests a bus cycle. When that bus cycle is granted, that unit becomes the master and may address any other unit in the system as the slave. Some types of bus interchange require a response cycle (a single fetch memory read, for example). In cases where a response cycle is required, the requestor assumes the role of master, indicates that a response is required, and identifies itself to the slave. When the required information becomes available, (depending on slave lZ~ 54 response time), the slave then assumes the role of master, and initiates a transfer to the requesting unit. This completes the single fetch interchange which ha~ taken two bus cycles in this case. Intervening time on the bus between these two cycles (the reque~t cycle and the re~ponse cycle) may be used for other system traffic not involving the~e two units.

A master may address any other unit on the bus as a slave. It does this by placing the slave addre~s on the address leads. There may be 24 address leads for example which can have either of two interpretation~ depending on the state of an accompanying control lead called the memory reference signal (BSMREP-). If the memory reference signal is a binary ZERO, the forma~ of FIG. 2 applies to the addres-~ leads with the 24th such lead being the least significant bit. It should be noted that as used in this specification, the terms binary ZERO and binary ONE are used respectively to refer to the low and high states of electrical signals. If the memory reference signal i5 a binary ONE, the format for such 24 bits as shown in FIG. 3 applies. In essence, when the memory is being addressed, the bu~ enables up to 2 to the 24th power bytes to be directly addres~ed in memory. When units are pa~sing control informqtion, data or interruptq, 12118~4 they addre~s each other by channel number. The channel nu~ber allows up to 2 to the 10th power channels to be addressed by the bus. Along with the channel number, a six bit function code is pas~ed which ~pecifies which of up to 2 to the 6th power possible functions this transfer implies.

When a master requires a response cycle from the slave, it indicates this to the slave by one state (read command) of a control lead named BSWRIT- (the other state thereof not requiring a response, i.e., a write command).
In this case, the master provides its own identity to the slave by means of a channel number. The data leads, as opposed to the bus address leadq, are coded in accordance with the format of FIG. 4 to indicate the master's identity when a response is required from the slave. The re~ponse cycle is directed to the requestor by a non-memory reference transfer. The control lead, indicated as a second-half bus cycle (BSSHBC-), is enabled to designate that this i8 the awaited cycle (as compared to an unsolicited transfer from another unit). When a master require~ a double fetch from a slave, it indicates this to the slave by one ~tate of a control lead named, BSD8PL- ~the other state thereof not requiring a double fetch, i.e., a single fetch). When the slave responds to thé master's request, one state of this same control lead .. . . .

1211~3S4 (BSDBPL-) is used to indicate to the requesting unit that this response cycle is the first response cycle of two response cycles (the other state thereof indicating that this is the last response cycle of a double fetch operation).
A distributed tie-breaking network provides the function of granting bus cycles and resolving simultaneous requests for use of the bus. For the most part, priority is granted on the basis of physical position on the bus, the highest priority being given to the first unit on the bus. The logic to accomplish the tie-breaking function is distributed among all units connected to thebus and is fully described in U.S. Patent No. 4,030,075, and an improvement thereof described in U.S. Patent No. 4,096,569.
In a typical system, the memory is granted the highest priority and the central processor is granted the lowest priority with the other units being positioned on the basis of their performance requirements. In the system of the preferred embodiment which is illustrated in FIG. 1, both the CPU logic and the memory control-ler are on one printed circuit board which is positioned at the high priority end of the common bus and the priority logic has been improved to allow the CPU to be assigned the lowest priority as is described in Canadian Patent Application Serial No. 453,406 entitled, "Distributed Priority Network Logic for Allowing a Low Priority Unit to Reside in a High Priority Position`'.
Thus, referring to FIG. 1, a typical system of the present invention includes a multiline common bus 107 coupled with a CPU, a memory and one or more I/O devices and controllers. Such ~21~8S4 memory controller 109 having the highest priority and CPU logic 108 having the lowest priority with the I/O controllers 103 and 104 having intermediate priorities. Further, each one of such units includes address logic for recognizing its channel number or memory address. The address logic for a typical basic device controller is also discussed in U.S. Patent No. 4,030,075.
A channel number will exist for every end point in a particular system with the exception of the memory type processing elements which are identified by the memory address. A channel number is assigned for each such device. Full duplex devices as well as half-duplex devices utilize two channel numbers. Out-put only or input only devices use only one channel number each.
Channel numbers are easily variable and accordingly one or more hexadecimal rotary switches (thumb wheel switch) may be utilized for each such unit connected with the bus to ~Z118~i4 --19-- . .

indicate or set the unit's address. Thus, when a system is configured, the channel number may be designated for the particular unit connected to the bus as may be appropriate for that particular system. Units with multiple input/ou~put (I/O) ports generally will require a block of consecutive channel numbers. By way of example, a four port unit may use rotary switches to assign the upper 7 bits of a channel number and may use the lower order 3 bits thereof to define the port number and to distinguish input ports from output ports. The channel number of the slave unit will appear on the addre~s bus for all non-memory tran~fers as shown in FIG. 3. ~ach unit compares that number with its own in~ernally stored number (internally stored by means of the rotary switches). The unit which achieves a compare is, by definition, the slave, and must respond to that cycle.
Generally, no two points in a single system will be assigned to the same channel number. As shown in FIG. 3, a ~pecific bu~ or I/O function can be performed as indicated by bits 18 through 23 of the bus addre ~ leads for non-memory transfer3. Function code~ may designate output or input operation~. A11 odd function codes designate output transfers (write) while all even function codes designate input transfer reguests (read). For example, a function code of OO(ba~e 16) may be used to indicate a single fetch memory read and a function code of 121~8~4 20(base 16) may be used to indicate a double fetch read operation. The central processor examines the least significant bit, 23, of the 6 bit function code field for an input/output command and uses a bus lead to designate the direction.

There are various output and input functions. One the output functions is a command whereby a data quantity, for example 16 bits, is loaded into the channel from the bus. The meanings of the individual data bits are component Qpecific, but the data ~uantity is taken to mean the data to be stored, sent, transmitter, etc., depending upon the specific component functionality. Another such output function is a command whereby for example a 24 bit quantity is loaded into a channel address register (not shown in the figures). The address is a memory byte address and refers to the starting location in memory where the channel will commence input or output of data.
Various other output functions include an output range command which define~ the size of the memory buffer assigned to the channel for a specific transfer, an output control command which by its individual bits causes specific responses, output task functions such as print commands, output configura~ion which is a command to indicate function~ such as terminal speed, card read mode, etc., and output interrupt control which is a command B5~

which loads for example a 16 bit word into the channel with the format as shown in FIG. 5. The first 10 bits indicate the central processor channel number and bits 10 through 15 indicate the interrupt level. Upon interrupt, the central processor channel number is returned on the address bus while the interrupt level is returned on the data bus. The input functions include functions similar to the output functions except in this ca~e the input data i~ transferred from the device to the central processor via the bus.

As previously discussed, a unique device identification number is a-asigned to every different type of device which i~ connected to the bus. This number is presented on the bus in reRponse to the input function command entitled input device identification. This number is placed on the data bus in the format shown in FIG. 6.
For convenience, ths number is aeparated into 13 bits identifying the device (bits 0 through 12) and three bits identifying certain functlonality of the device ~bits 13 through 15) as may be required.

BUS TIMING
FIG. 7 illu~trate~ the bus timing diagra~ and will be diQcus~ed more specifically hereinafter. Generally, however the timing is a~ follows. The timing applies to all transfers from a maste~ unit to a slave unit connected ~211 854 to the bu~. The ~peed at which the transfer can occur is dependent upon the configuration of the system. That is, the more units connected to the bus and the longer the bus, then, due to propagation delays, the longer it takes to communicate on the bus. On the other hand, the lesser amount of units on the bus decreases the respon~e time.
Accordingly, the bus timing i~ truly asynchronous in nature. A master which wishe~ a bus cycle makes a bus request. The signal BSREQT- i8 common to all units on the bus and if a binary ZERO, indicateQ that at least one unit is requesting a bus cycle. When a bus cycle iq granted, the signal BSDCNN- become~ a binary ZERO indicating that a tie-breaking function is complete ond that one specific maQter now has control of the bu~. At the time the signal BSDCNN- become~ a binary ZERO, the master applies the information to be tran~ferred to the bus. Each unit on the bus develop~ an internal strobe (BSDCND-) from the signal BSDCNN-. The ~trobe lBSDCND-) i5 delayed for example approxi~ately 60 nanosecond~ from the reception of the b$nary ZERO state of the BSDCNN- signal. When the delay i~ complete in the slave, the bu~ propagation time variation~ will have been accounted for and each ~lave unit would have been able to recognize its addre~ (memory addre~ or channel number). The addre~sed slave can now make one of these responses, either an acceptance (ACR), a non-acceptance ~NAR) or a wait ~WAIT) ~ignal or more lZ11854 specifically a ~SACKR-, a BSNARR- or a BSWAIT- signal.
The response is sent out on the bus and serves as a signal ~o the master that the slave has recognized the requested action. The control lines then return to the ~inary ONE
state in the se~uence as shown in FIG. 7. Thus, the bus handshake is fully asynchronous and each transition will only occur when the preced$ng transition has been received. Individual units may therefore take different lengths of time between the strobe and the ACR, etc.
transition depending on their internal functionality. ~A
bus timeout function exists to prevent hang-upa which could occur if no unit on the bus responds to a request.

Information which is transferred over the bus can include, for example, 50 signals or bits, which may be broken down as follow : 24 address bits, 16 data bits, 5 control bits and 5 integrity bits. These various ~ignals will be discus~ed hereinafter.

BUS PRIORITY
The common~bus request tie-breaking function is that of re~olving simultaneous request~ from different units for service and granting bus cycles on a basis of a po~itional priority system. A~ indicated hereinbefore, the memory has the highest priority and the central proce~sor has the lowest priority even though they both physically reside at one end of the co~mon bus 107. Other 5~

units occupy positions along the bus and have priority which increases relative to their proximity to the memory end o the buR. The priority log~c i~ included in each one of the units directly connected to the bus in order to accomplish the tie-breaking function. Each such unit' 3 priority network include~ a grant flip-flop. At any point in time, only one specific grant flip-flop may be set and that unit by definition is the ma~ter for that specific bus cycle. Any unit may determine at any time that it need~ a bus cycle and ~et it~ u~er flip-flop. At any time therefore, many user flip-flops may be set, each representing a future bu~ cycle. I~ addition, each unit on the bus contains a reque~t flip-flop. When all units are considered together, the request flip-flops may be lS considered as a request register. It i~ the ou~puts of this regi~ter that supply the tie-breaking network which function~ to set only one grant flip-flop no matter how may requests are pending. More specifically, if there were no pending u~er~ then no reque~t flip-flops would be ~et. The fir~t user flip-flop to set would cause its request flip-flop to set. This in turn would inhibit, after a short delay as hereinafter described, other device~ from ~etting their reque~t flip-flops. Thus, what - occurs is that a ~nap-shot of all user flip-flops i-~ taken for the given period in time (the delay period). The result is that a number of reque~t flip-flops may be set ~Z118~4 during this delay period depending upon their arrival. In order to allow the request flip-flops to have their outputs become stable, each unit include~ such delay in order to insure that such stabilization has occurred. A
particular grant flip-flop is set if the unit associated therewith has had its reque~t flip-flop set and the delay time has elapsed and no higher priority unit wants the bus cycle. A strobe signal i8 then generated after another delay period and finally the grant flip-flop i~ cleared (reset) when the master receives an ACR, NAK or WAIT
signal from the slave unit.

As indicated hereinbefore, there are three pos3ible slave responses, the ACR, the WAIT or the NAR signal. In addition, there is a fourth state in which there is no response at all. In the case where no unit on the bus recognizes the tran~fer as addresQed to it, no response will be forthcoming. A time out function will then take place and a NAR ~ignal will be generated thereby clearing the bus. An ACR signal will be generated if the slave is capable of accepting the bus transfer from the master and wishes to do so. The WAIT respon8e ig generated by the slave if the slave is temporarily busy and cannot accept a transfer at this time. Upon receipt of the WAIT signal, the master will retry the cycle at the next buQ cycle granted to it and continue to do 80 until successful.

~21~354 Some of the conditions which cause a WAIT response from a slave, when the central processor is the master are: if the controller is waiting for a response from memory or if the controller has not yet proce~ed the previous input/output command, or in the ca~e of the inatant invention, when the controller i~ the master and attempts to lock memory and the memory is already locked by another controller or the central processor. The NAK signal generated by the slave means it cannot accept a transfer at this time. Upon receipt of a NAR signal, a master unit will not immediately retry but will take specific action depending upon the type of master.

As generally indi~ated hereinbefore, there are basic timing signals on the bus which accomplish the hand-shaking function thereof. These five signal~, as discussed hereinbefore, are bus request signal (BSREQT-) which when a binary ZERO, indicates that one or more units on the bu~ have requested the bus cycles the data cycle now signal (BSDCNN-) which when a binary ZERO indicate~ a speciflc master is making a bus transfer and has placed information on the bu~ for use by ~ome speciic slaves the ACK signal (BSACRR-) which is a signal generated by the slave to the master indicating that the slave is accepting this transfer by making this aignal a binary ZEROs the NA~
signal ~BSNARR-) which is a signal generated by the ~lave 1211~

to the ma~ter indicating to the master when it i~ a binary ZERO that the slave is refus~ng this transfer; and the WAIT signal (BSWAIT-) which is a signal generated by the slave to the master indica~ing when it is a binary ZERO
that the slave is postponing the deci~ion on the transfer.

In addition and as indicated hereinbefore, there may be as many as fifty information signals which are transferred as the information content of each bu~ cycle.
The~e signals are valid for u~e by the slave on the leading edge of the strobe signal BSDCND- of FIG 7. All of the following discussion i8 by way of example and lt should be understood that the number of bits may be changed for different functions. Thus, there may be 16 leads or bits provided for the data. There are 24 leads provided for the address. There is one bit provided for the memory reference signal ~BSMREF-) which when a binary ZERO indicates that the addre~s leads contain a memory addresa. When the memory reference signal is a binary ONE, it indicates that the address lead~ contain a channel addres~ and a function code as indicated in FIG. 3.
There i9 also provided a byte signal (BSBYTE-) which indicate~ when it is a binary ZERO that the current transfer i~ a byte transfer rather than a word transfer, a word typically comprising two byte~. There is also a write signal ~BSWRIT-) which lndicate~ when lt i~ a binary Z~18S4 ONE that the ~lave is being reguested to supply information to the master. A separate bu~ transfer will provide this information. There i5 further provided a second-half bus cycle ~SS~BC-) which is used by the master to indicate to the slave that this is the information previously requested. Prom the time a pair of units on the bus have started a read operation as indicated by signal (BSWRIT-) until the second cycle occur~ completing the transfer of the data read from memory (indicated by BSSHBC-), both units may be busy to all other units on the bus.

BUS LOCg MEMORY OPERATION

In addition to miscellaneou~ error and parity signal3, there is also included a lock signal among the fifty information signals on the bus. The lock signal (BSLOCR-) is used to cause a lock operation to occur. A
memory lock operation is a multi-cycle bus transfer whereby a unit may read or write a word or multi-word area of memory without any other unit on the bus or, as will be dew ribed belo~, the CPU being able to break into the operation with another lock operation. This facilitates using memory locat~ons aQ flags to communicate between asynchronously processing units within the system. The effect of the lock operation is to extend a busy condition beyond the duration of the memory cycle for certain types 12~ 3S4 of operation. Other units on the bus attemptin~ to initiate lock signals before the last cycle is complete will receive a NAK reaponse. The memory will, however, still respond to other tnon-locked) memory requests.

S An example of the lock operation is the read-modify-write cycle, the three bus cycles of which are as follows~ During the first bus cycle (time A to F in FIG. 9), the address bus contains the memory address, the data bus contains the channel number of the originator, the signal BSWRIT- is a binary ZERO indicat~ng a re~ponse is required, the signal BSLOCR- is a binary ZERO
indicating that this is a locked operation and further the BSMREF- signal is a binary ONE~ During the second bus cycle of the read-modify-write operation ~time G to R in FIG. 9), the address bus contains the channel number of the originator, the data bus contains the memory data, the BSSH8C- signal is a binary ZERO denoting a read re~ponse and the BSMREF- signal is a binary ONE. During the third bus cycle (time L to P in FIG. 9), the address bus contain~ the memory address, the data bus contain~ the memory data, the BSLOCR- signal is a binary ZERO
indicating the completion of the read-modify-write operation and the BSMREF- ~ignal is a binary ZERO, and the BSS~BC- signal is a binary ZERO. In addition, the BSWRIT-si~nal is a binary ONE. Note the above discus~ion is in -30- .

general term~ and the ~ndividual signals may only be in the described state for a portion of the bus cycle as shown in FIG. 9. As in all other operations, the intervening time on the bus between the three bu5 cycles of the read-modify-write operation can be used by other units not involved in the transfer. In addition, the CPU
can access the memory so long a~ the CPU does not attempt a memory lock operation.

In addition to the other control signals, also provided on the bus may be the bus clear (BSMC~R-) ~ignal which is normally a binary ONE and which become~ a binary ZERO when a master clear operation is performed such as during a power-up ~eguence of the system.

BUS PRIORITY NET TIMING

The timing diagram of FIG. 7 will now be more specifically discu~sed in detail with respect to the addre~ logic circuitry of the memory and the central processing unit.

With reference to the timing diagram of FIG. 7 in every bus cycle there are three identifiable part~, more particularly, the period ~7-A to 7-C) during which the highest priority requesting device wins the bu~, the period (7-C to 7-E) during which the master unit call~ a slave unit, and the period (7-~ to 7-G) during which the .

8S~

slave responds. When the bus ~ idle the bus request signal (BSR~QT-) is a binary ONE. The bus request signal's negative going edge at time 7-A starts a priority net cycle. There ic an asynchronous delay allowed within the ~ystem for the priori~y net to settle (at time 7-B) and a ma~ter user of the bus to be ~elected. The next signal on the bus is the BSDCNN- or data cycle now signal.
~he BSDCNN- signal'~ transition to a binary ZE~O at time 7-C means that use of the bus ha~ been granted to a master unit. Thereafter, the second phase of bus operation means the master has been selected and is now free to transfer information on the data, address and control leads of the common bus 107 to a slave unit, that the master so designates.

The slave unit prepares to initiate the third phase of the bus operation beginning at the negative going edge of the strobe ~ignal BSDC~D-. The strobe signal is delayed, for example, sixty (60) nanoseconds from the - negative going edge of BSDCNN- gignal by a delay line 824 of FIG. 8 in the bus priority re~olution logic. Upon the occurrence of the negative going edge of BSDCND- signal at time 7-D, the slave unit can now test to see if thi~ is it~ address and if it i9 being called to start the decision making proces~or of what response to generate.
Typically, thi~ will cause an acknowledge signal (BSACRR-) ~21~85~4 to be generated by the slave unit or in the non-typical case~ a BSNAgR- or BSWAIT- signal or even no response at all (for the case of a non-existent slave) may be generated as herein described~ The negative going edge of the acknowledge signal at time 7-E when received by the ma~ter unit, causes the master'~ ~SDCNN- signal to go to a binary ONE at time 7-F. The strobe signal returns to the binary ONE state at time 7-G which is a delay provided by the delay line 824 in FIG. 8 from time 7-P. Thus, in the third phase of the bus opera~ion, the data and address on the bus are stored by the slave unit and the bus cycle will begin to turn off. The ending of the cycle, i.e., when BSDCNN- goes to binary ON~, dynamically enables another priority net resolution.

A bus request ~ignal may, at this time, be generated and if not received this means that the bus will return to the idle state, and accordingly the BSREQT- signal would go to the binary ONE state. If the bu~ request signal is present at that time, i.e., a binary ZERO as shown, it 2Q will start the ~ ynchronous priority net selection process following which another negative going edge of the BSDCNN-signal will be enabled as shown by the do~ted lines at time 7-I and 7-J. It should be noted that thiq priority net resolution need not wait or be triggered by the po~itive going edge of the acknowledge signal at time 7-~, ~21~854 but may in fact be triggered at a time 7-F just following the transition of the bu3 to an idle state if thereafter a unit desires a bus cycle. Although the priority net resolution can be triggered at time 7-F by the positive going edge of the BSDCNN; signal, the second negative going edge of the BSDCNN- signal, in re~ponse to the setting of a grant flip-flop must await the positive going edge of the acknowledge signal at time 7-~. The negative going edge of the BSDCNN- signal at time 7-I illustrates the case where the priority net resolution i~ triggered at time 7-E and the resolution occurs before time 7-H~ The negative going edge of the BSDCNN- signal at time 7-J
illustrates the case where the acknowledge signal clears before the resolution of the priority net. The negative going edge of the BSDC~N- signal at time 7-L illustrates the case where there i3 no bus request at time 7-F and the priority net resolution is triggered by a later bus request signal BSREQT- at time 7-R. Thi~ process repeats in an asynchronous manner.

READ MEMORY OPERATION

A memory read operation will now be discus~ed by way o~ example. In the example, an I/O controller will make a read request- of memory and the two bus cycles associated with the reque~t and response will be examined. During the fir~t bu~ cycle, the I/O controller ~s the master and ~Z~8S~

the memory i~ the slave. During this first cycle, the I/O
controller bidc for the bus using its priority network logic and the memory controller re~ponds. During ~he second bus cycle, in which the memory controller is the master and the central processor is the slave, the the master and the I/O controller i~ the slave, the memory bids for the bus using its priority network logic and the I/O controller respond~ using bus interface logic. The memory controller busy signal is provided to indicate that one of the memory module~ connected to the memory controller is in fact busy. If a memory module i~ busy, then a WAIT signal will be generated in response to a master (reque~ting) unit making a memory request. The acknowledge signal tACK) will be generated when the memory controller is not bu~y. It i~ again noted that the WAIT
signal means that there will be a very short delay since the memory i8 still bu~y.

L~C~ MEMORY OPERATION

The other condi~on which indicates which of the ACR, NAR or WAIT signals i~ to be genera~ed, is the lock signal which as indicated hereinbefore comprise~ a multi-cycle bus transfer whereby a device can acces~ a ~pecific memory location without any other locking unit being able to bre~k into the operation. The effect of this lock operation is to extend ~he bu~y condition of the memory ~21'185~

controller beyond the completion of a single cycle for certain kinds of operations. Devices on the common bus 107 attempting to initiate a lock operation before the last cycle of the sequence i5 complete will receivè a NAR
S signal. The memory will however -qtill respond to a memory request as shall be pre-Rently explained. It is noted that the intervening time between the-Re bus cycles may be used by other units not involved in the transfer. A lock operation is used primarily where it i~ desirable for two or more unit~ or deviceQ to share the same resource, such a~ memory for example. The lock operation, which can include any number of bus cycles and memory cycles, is unlocked by the particular unit or device which has had control of the shared resource. While the shared resource is locked, other units desiring to access the shared resource will be locked out if such other units on the bus present the lock control signal, or if the CPU attempts to do a lock operation. If a lock operation is not attempted, it is pos~ible for the CPU or such other units to gain access to the shared resource such as, for example, to process an urgent request or procedure.
Before any unit pre~enting the lock ~ignal gains access to the shared resource, the shared resource i8 tested to see wheth~r it is involved in a lock operation and then, if the resource is not involved in a lock operation, the 1;211~3~4 resource can be accessed by the unit attempting the lock operation.

Thus, it can be seen that the lock operation for sharing a resource is one that is effective between those units which issue the appropriate controls, i.e., the lock control si~nal and may be used for example in sharing a portion of memory in which a table of information may be stored. Further, if one of the units desires to change information in the shared resource, other units may be locked out 80 that they do no~ gain access to only partially changed information, but rather be allowed accesa only after all such change3 have been made. A
read-modify-wri~e operation may be involved in 3uch case.

It is noted that the BSS~BC- signal for a lock operation performed via common bU8 107, as shall be seen, i8 used in a somewhat different manner than has been heretofore discussed. During a bus lock operation, the 8SSH~C- signal is issued by the unit attempting to share a resource both to gain access to the shared re~ource by means of a test and lock procedure and to unlock the shared resource when it has completed its lock operation.

LOCK LOGIC

The method by which lock logic 110 of memory controller 109 is utilized to perform an indivisible l'~lil35~

memory operation on behalf of an I/O controller or the CPU will now be discussed with reference the logic block diagram of FIG. 8 and the timing diagram of FIG. 9. Because memory controller 109 is dual portea in that it provides memory access from an I/O
controller via common bus 107 or from the CPU logic 108, lock logic 110 must provide for the synchronization of lock requests which can be asynchronously generated by either an I/O controller or the CPU logic. This synchronization of the asynchronous lock and unlock operations occurs as described below.
FIG. 8 is a logic block diagram of lock logic 110 of memory controller logic 109. In FIG. 8, the small circles on the inputs or outputs of the logic elements represent inverting inputs and outputs respectively. In FIG. 8 the lock logic 110 is comprised of locked by CPU flip-flop 801, locked by bus flip-flop 820, synchronizing flip-flop 802 and other flip-flops, inverters, ~ND, NAND and NOR gates. Flip-flops 801 and 820 are J-K negative-edge-triggered flip-flops with preset and clear of the type S 4S112 manufactured by Texas Instruments Inc. of Dallas, Texas and are described in their book, The TTL Data Book for Design Engineers, Second Edition, copyrighted 1976. Synchronization flip-flop 802 is a D-type positive-edge-triggered flip-flop with preset and clear of the type 74F74 manufactured by Fairchild Camera and Instrument Corporation of Mountainview, California, and described in their book, Fast Fairchild Advanced Schottky TTL, copyrighted 1980.

Initially, before any memory lock operation begins, locked by CPU flip-flop 801, locked by bus flip-flop 820, and synchronization flip-flop 802 are in their reset state such that the output signal at their Q output is a binary ZERO and the output at their Q-bar output is a binary ONE. Thus, signal CPLKME+ at the Q output of flip-flop 801 and signal LOCKDD+ at the Q output of flip-flop 820 are binary ZEROs, and signal LOCKDD- at the Q-bar output of flip-flop 820 and signal and LOCKED- at the Q-bar output of flip-flop 802 are binary ONEs.
Flip-flops 801, 820 and 802 are initially set to the reset state by a bus master clear signal, ~SMCLR-, which is an input to the reset (R) input of each of these flip-flops, transitioning to a binary ZERO for a short period of time when the system is initial-ized so that logic in units connected to common bus 107 is cleared to an initialized state.
LOCK MEMORY EXAMPLE
The lock logic 110 of FIG. 8 will now be explained with reference to the timing diagram of FIG. 9 which lZ11~35~ .
-39- .

illustrates a case in which an I~O controller wishes to do a lock operation on a location in one of the memory modules In this example illustrated in PIG. 9, after the I/O controller has initiated the memory locked operation, the CPU determines that it wants to perform a lock operation on the memory and also initiate~ a lock operation. The example in FIG. 9 shows that the I/O
controller lock operation is completed before the CP~ lock operation is allowed to take place. During the CPU lock operation, the I/O attempt~ to initiate another memory lock operation. FIG. 9 shows that the I/0 memory lock operation begins at time A and complete~ a time O, during which a memory read is performed from time A to time J, the data is modified by the I/O controller from time J to L and the modified data is written into the memory from time L to O. Pollowing the bu~ memory lock operation on behalf of an I/O controller, the CPU complete~ its memory lock operation, which began at time AA, and during which the CPU has the memory locked from time C to X and which i~ compri~ed of the CPU doing a memory read from time BB
to CC, the CPU modifying the data from time CC to DD, and the CPU writing the modified data into memory from time DD
to EE. During the CPU, which results in a NAR
re~ponse.memory lock operation, an I/O controller attempted to do a memory lock operation from time R to U, which result~ in a NAR response.

~2~1~54 In YIG. 9, at time A an I/O controller, such as I/O
controller 103, o FIG. 1 has determined that wishes to perform a read-modify-write operation of a location in memory. This requires that a memory lock operation be performed and at time A the I/O controller reque~ts use of common bus 107 by causing bus request signal BSREQT- to transition from the binary ONE to the binary ZERO state.
When the bus request signal BSREQT- transitions to the binary ZERO state, it starts a bus priority resolution cycle and pciority logic in each of the units attached to common bus 107 then proceed to determine which of all possible requesting units has the highest priority and, if the I/O controller is the highest priority, it will be granted the bu~ as the master unit and the I/O
controller's priority logic will cause data cycle now signal, BSDCNN-, on the bus to transition from the ONE to the binary ZERO state at time B. At this same time, I/O
controller logic 103 as the ma~ter unit will put on the bus address lines the addres3 of the location which iq to be read and will al80 set bus lock signal BSLOCR- ~o the binary Z~RO state and leave second half bus cycle, signal B5H~BC-, in the binary ONE state thus signalling the memory as the slave unit that a lock operation is to be performed. Thus, at time B in FIG. 9 we see that signal BSH~BC- i~ a binary ONE at one input of AND gate 818 of FIG. 8 and signal BSLOC~ a binary ONE at the other input of AND gate 818 causing the output thereof, signal LOCRER+, to be a binary ONE at the J input of locked by bus flip-flop 820. Signal BSLOCR+ is output by inverter 821 which inverts input signal BSLOCR- from common bus 107. Bus lock ~ignal BSLOCK+, which becomes a binary ONE
at time B in FIG. 9, i~ al~o one input to AND gate 819.
The other input to AND gate 819 is bus second half cycle, signal BSSHBC+, which is the inverted output of inverter 822, the input of which is signal BSS~BC- from common bus 107. At time B, signal BSSHBC+ remain~ a binary ZERO thu~
disabling the output of AND gate 819 causing signal UNLOCK+ to be a binary ZERO at the R input of locked by bus flip-flop 820. At time ~, data cycle now signal BSDCNN- on the bu~ changes from the binary ONE to the binary ZERO state and causes the output ~ignal BSDCNN+ of inverter 823 to change from the binary ZERO to the binary ONE sta~e and at the clock ~C) inpu~ of synchronization flip-flop 802 thereby clocking signal CPLRME+ at its data ~D) input. Because signal CPLRME+ is a binary ZERO at time B, synchronization flip-flop 820 remains in the reset #tate causing its Q-bar output, signal LOCR~D-, to remain a binary ON~ and thus continue to partially enable NAND
gate 804.

Thus, a~ it will become more apparent later, when an I/O controller i~ attempting to lo~k memory, the output of S~
--42-- .

AND .gate 818, signal LOCE~ER+, is a binary ONE and the outpu~ of AND gate 819, signal UNLOCR+, is a binary ZERO
in response to the I/O controller setting signal BSLOCR-to the binary ZERO state and maintaining signal BSSHBC- in the binary ONE state as i~ done at times B and S in FIG.
9 at the beginning of a I/O memory lock operation. The output of AND gate 818 is a binary ZERO and the output of AND gate 819 is a binary ONE when an I/O controller is attemp~ing to unlock the memory which is done by the I~O
controller setting signal BSLOCR- to the binary ~ERO ~tate and setting bus second half cycle signal BSS~BC- to the binary ONE state such as is done at time M in FIG. 9.
Thus, at time B in FIG. 9, the lock and unlock signals are established at the J and R inputs, respectively, of locked by bu~ flip-flop 820. Establishing the e inputs at the J and K inputs of flip-flop 820 has no effect until flip-flop 820 is clocked by clocking signal MEACRR-transitioning to the binary ZERO state which occurs later at time D~ Until time D, locked by bus flip-flop 820 remains in the re~et state such that its Q-bar output signal, LocRDn-~ remain~ in the binary ON~ state at the other input of NAND gate 804. With both input~ of NAND
gate 804 in the binary ONE state, the output thereof, ignal LOCRED+, will remain in the binary ZERO state until one it~ input~ becomes a binary ZERO.

12~

Signal LOCXEDI is one of the inputs to AND gate 805 and to ~AND gate 807~ The other input to AND 805 and NAND
gate 807 is signal LOCRER+, the output of AND gate 818.
The output of NAND gate 804, signal LOCRED+, will be a binary ONE if the memory i~ already locked by either the CPU or the bus and a binary ZERO if the memory is not locked by either the CPU or the bus.

Signal LOCKEDi being a binary ZERO at one input of A~D gate 805 and an input of NAND gate 807, will disable these gate~ and cause their outputs, signal MENARR+ to be a binary ZERO and ~ignal MENA~R- to be a binary ONE, respectively. Signal MENAKRt is one input to NOR gate 806 and signal MENARR- is one input to NOR gate 808. The other ~nput~ to NOR gates 806 and 808 are 3ignals MESAME-, MODPAR-, P~RER8+ and PARER0+~ In order for the output of NOR gate 806 or NOR gate 808 to be a binary ONE, each of their five inpu~s must be binary ZE~Os. Signal MESAME- is a binary ZERO when the addre~s o~ the memory location to be read or written is within the address space of the memory controller 109 (i.e~, the address memory location must fall within memory module 1 101 or memory module

2 102 and the addressed module must be physically present within the ~ystem). Therefore, at time B, if the address presented on the common bus 107 bus by I/O controller 103 as master falls within a memory module which i8 pregent, ~21~8~

signal MESAME-, will be a binary ZERO. Signal MODPAR- is an address modular parity signal which indicates whether the parity on the upper eight bi~ address lines of the common bu~ agrees. with the parity line on the common bus and, i so, will be a binary ZERO. Parity error signals PARER0+ and PARER8+ are data parity error indicatorq for the low order 8 bit and high order 8-bit data lines, respectively, and will be binary ZEROs if no parity error occurs. Therefore, in the normal case when an I/O
controller is addressing a location within memory, signals MESAME-, MODPAR-, PARER8+ and PARER0+ will all be binary ZEROs and the outpu~ of NOR gate~ 806 and 808 will be dete~ined solely by i~put signals MENARR~ and MENARR-, respectively. In this case, at time B, signal MENARR+
will be a binary ZERO causing the output of NOR gate ~06, signal MECYLE~, to be a binary ONE and signal MENARR- will be a binary ONE and cause the output of NOR gate 808, signal MBNARR~, to be a binary ZERO. D-type flip-flops 809 and 810 are clocked by strobe signal BSDCND+ at their clock (C) inputs transitioning from the binary ZERO to the binary ONE state. Strobe ~ignal BSDCND+ is derived by delaying signal BSDCNN+ about ~ixty nanosecond~ by delay line 824 which i~ part of the memory controller's bu~
priority resolution logic. Signal B5DCND- shown in FIG.
7 is derived by inverting ~ignal BSDCND+ by inverter 826.
The clocking of the binary ON~ s~gnal, MECYLE+, at the D

~Z~3S4 input of flip-flop B09 will re~ult in the setting of flip-flop 809 causing it8 Q output, signal MECYLL+, to become a binary ONE and its Q-bar output, signal MECYLL-, to become a binary ZERO~ At thi3 same time when signal BSDCND+ transitions from the binary ZERO to the binary ONE
state, flip-flop 810 will be clocked and the binary ZERO
of -Qignal MENAKR~ at its D input will result in flip-flop 810 remaining in the rese~ state which will cause its Q-bar output, signal MENAKK-, to remain in the binary ONE
1~ state. The clocking of flip-flops 809 and 810 takes place at time D when ~ignal BSDCND+ transitions from the binary ZERO to the binary ONE state. The outputs of flip-flop 809, signal MECYLL+ and MECYLL-, are used to determine whether a positive acknowledgement (ACK) or a wait (WAIT) response will be generated by the memory as the ~lave unit to the request from the ma~ter unit via the bus. The output of flip-flop 810, signal MENARX-, is used to determine whether a negative (NAR) response will be generated ~o the requesting unit.

AT time D, after flip-flop 809 is set, signal M~CYLL~
will become a binary ONE and partially enable NAND gate 811~ Also at time D, signal MECYLL- will be a binary ZERO
at one input of NOR gate 812 and therefore ~ts output ~ignal, MYWAIT+, will be determined by its other input sign~l, WAITER-. Signal WAITER- is output by memory bu~y ~2~1~5~
-46- . , flip-flop 803 which is used to indicate whether the memory is curr.ently busy or not. Signal WAITER- i5 also the .other input to NAND gate 811. Therefore, at time D, if memory busy flip-flop 803 is not set indicating that the memory i5 not currently busy, signal WAITER- will be a binary ONE at its Q-bar output and partially enable NAND
gate 811 and cause its output, signal MEACKR-, to be a binary ZERO when signal MECY~L+ become3 a binary ONE at time D. Signal MEACXR- is inverted by inverter 814 to produce signal MYACRR+ which is in turn inverted by inverter 815 to produce signal BSACRR- which is the positive bus acknowledgement signal which becomes a binary ZERO at time D in FIG. 9. It should be noted that for purposes of simplicity, the propagation delays associated with the elements in FIG. 8 is ignored in the timing diagram of FIG. 9 in many ca-~es. For example, the transition of signal BSDCNN- to a binary ZERO at time D is shown as immediately re-~ulting in signal BSACKR- becoming a binary ZERO in FIG. 9 and ignores the propagation delays of elements 823, 809, 811, 814 and 815. With signal WAITER- being a binary ONE at one input of NOR gate 812, the transition of signal ~CYLL- from the binary ONE
to ~he binary ZERO state at time D will not make any difference in the output of NOR gate 812 such that signal MYWAIT~ will remain a binary ZERO and the bu3 wait signal, BSWAIT-, which is output by inverter 816 will remain a binary ONE.

Thus, it can be seen that at time D in FIG. 9~ if an I/O controller attempt~ to lock the memory and the memory haR not been previously locked by either an I~O con~roller or the CPU and the memory is not busy, the positive acknowledgement (ACR) will be generated by the slave uni.t's lock logic 110 and sent to the I/O controller as the master unit via common bus 107 at ti~e D. Returning now to flip-flop 810, at time D, when the binary ZERO of signal ME~ARR+ is clocked into flip-flop 810, flip-flop 810 will remain re~et and its Q-bar output, signal ~ENAKR-, will remain a binary ONE causing the output of inverter 813, signal MYNARR+ to remain a binary ZERO and lS which in turn is inverted by inverter 817 to produce bus signal BSNARR- which will remain a binary ONE thereby indicating that a negative response (NAR) is not generated to the requesting I/O controller which is performing a lock opera~ion.

The transi~on of signal MEACRR- from the binary ONE
to the binary ZERO state at time D at the clock (C) input of locked by bus flip-flop 820 clocks the binary ONE of signal LOCRER+ at the J input and thereby sets flip-flop - 820 causing signal LOCRDD+ to become a binary ONE and 3ignal LOCRDD- to become a binary Z~RO. Thus, locked by ~21185~

bus flip-flop 820 is clocked each time a reque~ting unit attached to common bus 107 receives a positive acknowledgement (ACR) from memory controller 109. The transition of signal LOC~DD- from the binary ONE to ~he 5binary ZERO state at time D will cause the output of NAND
gate 804, signal LOCREDI, to becoms a binary ONE at time F.

At time D, when the memory controller has determined that the memory reguest from the I/O controller will be 10given a positive acknowledgement, the memory controller latches in the memory addres3 into the bus port of the dual ported memory and in addition latches in the state of the bus line which indicates whether the memory read or write operation is to be performed and makes a reguest of 15the priority resolver logic 111 for a memory cycle to be performed on behalf of a unit attached to the bus. At time ~, after the master unit, which in our example is I/O
controller 103, ha3 received the ACR from memory controller 109, the I/O controller removes the bus lock 20and data cycle now signals, BSLOCK- and BSDCNN-, and returning them from the binary ZERQ to the binary ONE
state and, in addition, the I/O controller removes the memory address and the read or write memory indicating siqnals. The transition of the data cycle now signal, 25BSDCNN-, from the binary ZERO to the binary ONE at time E

lZ118~4 thereafter causes the I/O controller to reset the bus request signal such that signal BSR~QT- transitions from the binary ZERO to the binary ONE state at time E. At time F, both flip-flops 809 and 810 are reset by signal BSDCNB~ becoming a binary ZERO at their re~et (R) inputs.
Signal BSDCNB+ i5 output by OR gate 825 which has inputs of signal BSDCND+ and signal BSDCNN+. The resetting of flip-flops 809 and 810 at the end of the memory bus cycle resultc in the ACX, WAIT or NA~ signals, whichever was active, being reset and returning to the binary ONE state as does signal BSAC~R- at time F, FIG. 9. Thu~, at time F, the slave unit removes its positive, wait, or negative response signal from the bus in preparation for the next bus cycle.

Later at time G, when the requested data has been read from the memory, the memory controller 109 makes a request for use of the bus at time G by causing the bus request signal BSREQT- to transition from the binary ONE
to the binary ZERO state. After the priority resolution has been determined, signal BSDCNN- transitions from the binary ON~ to the binary ZERO state at time ~ and, assuming that the memory has won the bu~, the memory as the master unit then places on the bus data lines the word of data read from the memory. It also, at this time, causes bus second half cycle, signal BSSHBC-, to ~z~
- so -tran~ition from the binary ONE to the binary ZERO state thereby indicating to the slave unit that this is response cycle to the previous read request. When the I/O
controller, as slave, recognizes itC controller address on the common bus 107, it~ responds by generating a positive acknowledgement and changes signal BSACKR- from the binary ONE to the binary ZERO state at time I.

The receipt of the ACR by the memory cau~es the memory controller's priority network logic to cause he data cycle now signal, BSDCNN~, to transition from the binary ZERO to the binary ONE state at time J and also causes the memory to remove the bu~ second half cycle signal, BSSHBC-, such that it returns from the binary ZERO
to the binary ONE state at time J. The receipt of the positive acknowledgement and the change of the data cycle now signal from the binary ZERO to the binary ONE state cau3es the bus request signal from the memory controller, signal BSREQT-, to tran3ition from the binary ZERO to the binary ONE s~ate at time J. At time K, after delaying the data cycle now signal BSDDNN- within its priority network logic, the I/O controller which had responded with an acknowledgement as a slave uni~, resets the bu~
acknowledgement signal, BSACXR-, from the binary ~ERO to the binary ONE state at time X.

~2 At this point in time in the lock operation exampl~, the I/O memory reque~t has been completed in that from time A through F the I/O controller w~ the ma~ter and the memory responds a~ the slave and took the memory address from the bus and from time G through R, the memory became the master and responded to the I/O controller as slave and provided the word of data read from the memory.
Between time E and G, other units on the common bus 107 could request and receive access to the bus and could also receive acces~ to memory controller iq they are not attemptinq to do a lock operation. Also during this time, the CPU, if it had not requested a lock operation at time C, could have access to the memory when the memory was not being u~ed in response to bus requests which are a higher priority as determined by the priority resolver logic 111.
From time J through to L, the I/O controller performed operations to modify the data read from memory. At time L, ~he I/O controller wanted ~o write back into memory the modified data and requests use of the bus by setting the bus request line, BSREQT- from the binary ONE to the b~nary ZE~O state. After the I/O controller wins the bus a~ master, it causes the data cycle now signal, BSDCNN-, to transition from the binary ONE to the binary ZERO O at time M and, in addition, puts the address of the locatlon in memory to be written onto the bus addre~ line~ and the data in memory to be written into that locatlon onto the ~21~354 ~52--bus data lines. At time M, the I/O controller also indicates that this i~ the completion of the lock operation and to do this it unlocks the memory by causing ~ignal BSLOCK to transition from the binary ONE to the binary Z~RO state and by causing the second half bus cycle line, BSSHBC-, to transition from the binary ONE to the binary ZERO state thereby indicating that this operation is an unlock operation as opposed to the lock operation which occurred at time B, during which the signal BSS~BC-was held at the binary ONE ~tate~

Returning now to the lock logic 110, illustrated in FIG. 8, it will be appreciated that at time M during th~
memory write bus cycle, in which an I/O controller as the master unit has indicated that the memory i~ to be unlocked by ~etting signal 3SLOCR- and signal BSSHBC- to the binary ZERO state, the output of AND gate 818, signal LOCKER+ will be a binary ZERO indica~ing that this is not a lock operation and the output of AND gate 819, signal UNLOCK+, will be a binary ONE indicating that this is an unlock operation At thi~ time M, locked by bus flip-flop 820, remains in the set state cau~ing its Q-bar output, signal LOCRDD-, to remain in the binary ZERO state. The binary Z~RO of signal LOCKDD- disables NAND gate 804 causing its output, ~ignal LOCRED~, to be a binary ONE
thereby $ndicating that memory is currently locked. The .. . . . __ . ,, . _ .. .. ,.. , .. , . _. _ _.. .. , , . , . ._ . . , 121~4 . -53-binary ONE of signal LOCKED~ partially enable~ AND gate 805 and NAND gate 807. However, both of these gates are disabled by the binary ZERO of si~nal LOCRER+ thus making the output of NAND gate 805, signal ME~ARR~, a binary ZERO
and the output of ~AND gate 807, signal MENARR-, a binary ONE. Assuming that the other four ~ignals that are inputs to NOR gates 806 and 808 are in the binary ZERO state indicating that the memory address on the bus is to a memory location controlled by the memory controller and that thece i~ no addre~ parity or data parity error, the output of NOR gate 806, signal MECYLE~, will be a binary ONE and the output of NOR gate 808, ~ignal MENA~R+ will be a binary ZERO because it~ input signal MENARR- is a binary ONE. Thereafter, after signal BSDCNN+ has been delayed by delay line 824 and causes clocking signal BSDCND+ to transition from the binary ZERO to the binary ONE state clocking flip-flops 809 and 810, flip-flop 809 will be set and cause its Q-output ~ignal MECYLL+ to become a binary ONE and flip-flop 810 will remain reset and cause its Q-bar signal, MEANKR-, to remain a binary ONE.

Assuming that the memory i~ now available, such that the output of memory busy flip-flop 803, signal WAITER-, iQ a binary ONE, NAND gate 811 will be fully enabled and cause its output ~ignal, MEACKR-, to become a binary ONE, which in turn will be inverted by inverters 814 and 815 lZ1~59~

and cause bus acknowledgement signal 8SACRR- to become a binary ZERO at time N in FIG r 9~ At time N in FIG. 9, bus wait signal and bu NAR signal, BSWAIT- and BSNARR-, will remain in the binary ONE state. When signal MEACRR-5transitions from the binary ONE to the binary ZERO state at time N, it will clock locked by bus flip-flop 820 which will have a binary ZERO at its J input and a binary ONE at its X input thus resulting in the resetting of flip-flop 820 which will cause its Q output ~ignal, LOC~DD+, to 10transition from the binary ONE to the binary ZERO state.

As discussed earlier, the receipt of the acknowledgement signal by the slave uni~, which is the I/O
controller in this case, will cause the I/O controller to remove the bus lock and bus second half bus cycle and the 15write address and data from the common bus 107 at time O
and thereby make signals BSDCNN-, BSLOCR-, and BSSHBC-transition from the binary ZERO to the binary ONE ~tate.
Receipt of the ACK and the transition of the data cycle now signal, BSDCNN-, will also result in the I/O
20controller releasing the bu~ request line such that signal BSREQT- ~ransition~ from the binary ZERO to the binary ONE
tate at time O. After delaying signal BSDCNN+ in the priority re~olution logic delay line 824 of the memory controller, the output of OR gate 824, signal BSDCNB+, at 25the reset (R) inputs of flip-flop~ B09 and 810 trans~tions from the binary ONE to the binary ZERO thus resetting both flip flops and causing the bus acknowledgement signal, BSACRR-, to transition from the binary ONE to the binary ZERO state at time P.

The return of the acknowledgement ~ignal BSACKR- at time P to the binary ONE state completes the I/O memory write cycle and completes the total read-modify-write cycle in which the memory wa~ initially locked at the start of the read cycle at time n when the locked by bus flip-flop 820 was set and ends at the end of the write cycle at time N when the locked by bus flip-flop 820 was reset.

A~ can be appreciated from the above discus~ion of the lock logic 110 in FIG. 8, each time the lock logic generate~ an ACR to a master unit which is requesting use of the bus, locked.by bus flip-flop 820 i8 clocked by ~ignal MEACXR- transitioning from the binary ONE to the binary ZERO state ~uch as at ~imes D, I and N in FIG. 9.
At time ~, the locked by bus flip-flop 820 was set and at ti~e N, it wa~ reset. At time I, the clocking of flip-flop 820 did not resul~ in any change of state of the flip-flop becau~e the J and R inputs were in the binary ZERO state because AND gates 818 and 819 were disabled by the binary ZERO ~tate of lock ~iqnal BSLOCR+.

~21~ 4 -56- .

It ~hould be noted that flip-flops 809 and 810 only generate an AC~, wAIT or NAR signal on the bus when the master unit has addressed a location within memory and will not be generated when a master unit i9 addressing another I/O contrpller or a location ~hat is not within ~he memory controlled by memory controller 109. This occur~ even though signal BSDCNDI clocks flip-flops 809 and 810 during each bus cycle. However,- unless the addres~ lines on the common bu~ 107 indicate a memory location wi~hin the memory, signal MESAME-, which is an input to both NOR gates 806 and 808 will be in the binary ONE state thereby causing their outputs, signals MECYLEI
and MENARR+, respectively, which are the inputs to the data (D) inputs of the flip-flops to be in the binary ZERO
state and thereby result in flip-flops 809 and 810 always being reset whenever they are clocked by signal BSDCND+.
This resetting in turn result in no change of state of their Q and Q-bar outputs, which in turn will result in no bus AC~, WAIT or NAR signal being changed to the binary ZERO state Be~ides being used to generate an ACX response, signal MEACRR- output by NAND gate 811 i8 also used a~ an I/O memory request into the priority rePolver logic 111 such that each time the memory gives a positive acknowledgement (ACR) to a memory request coming from ~2~8S4 common bu~ 107, it makes a reque~t for the memory through priority resolver logic 111.

J-~ flip-flops are set by clocking a binary ONE into the J input and are re~et by clocking a binary ONE to the R input. Therefore, the clocking of locked by bu~
flip-flop 820, each time the memory controller a~ a slave unit on the bu~, responds with an ACK to the master unit requesting a memory location be written into or read from.
The locked by bus flip-flop 820 will only change state if 10it i~ being locked or if it being unlocked a~ specified by the combination of the BSLOCK- and BSS~BC- signals such as happens at time B and time M in FIG. 9 and does not occur at time H in FIG. 9 because signal BSLOCK- i~ a binary ONE.

15Before discussing the method by which the memory i5 locked by the CPU, it should be noted that a normal (i.e., non-lock) memory read or write operation can take place on behalf of an I/O controller attached to common bus 107 durinq the time that the memory is locked. That i~, the only thing th ~ is inhibited during the time that the memory 1~ locked i-~ another locked read or write operation, be i~ from the CPU or bus. For example, if an I/O controller requested a memory read, the sequence shown in FIG. 9 starting at time A through time J would take place with the exception that the master unit would not .. .. ... . . . . . ..

~Z~18~4 cause the bus lock signal BSLOCK- to go to the binary ZERO
state at time B and therefore signal LOCKER~, at the J
input of flip-flop 820, would be a binary ZERO and it would also be a binary ZERO at the irsput of AND gate 805, which would cause the output thereof, ~ignal MENARR+, ~o be a binary ZERO which would result in the output of NOR
gate 806, signal MECYLE+, being a binary ONE. When the binary ONE of signal MECYLE+ was clocked into flip-flop 809 by the transition of ~ignal BSDCND+ to the binary ONE
state, NAND gate 811 would be fully enabled, assuming signal WAITER- is a binary ON~, and result in an ACK from the memory as the slave unit to the I/O controller as the master unit. This ACXing of the ma~ter unit would result in the clocking of locked by bus flip-flop 802, but because a binary ZERO appears at both the J and R inputs thereof,.the state of flip-flop 820 would not change and its previous unlocked state would remain unchanged.

CPU LOCK MEMORY OPERATION

The portion of lock logic 110, which allows the CPU
to perform a memory lock operation, will now be dlscussed with reference to FIG.s 8, 9 and 10. When the CPU wishe~
to read or write into the memory, whether it be during a non-locked or locked operation, the CPU does not communicate to the memory via common buQ 107 but instead uses the second port of the memory controller 109.

Therefore, the CPU does not make requests to use common bu~ 107 by changing the state of the bus request line BSREQT- nor does the CPU u~e any of the timing signals or the lock signals such as data cycle now signal 3SDCNN- or the lock signal BSLOCX- or the ~econd half bus cycle signal BSSHBC-. In addition, the CPU does not look at the ACK, WAIT or NAR ~ignal line3 to see whether the memory as a ~lave unit has accepted the command from the ma~ter unit which want~ to access the memory.

This mas~er-slave unit relationship does not exi~t between the CPU and the memory because the CPU
communicates directly to the memory through its own port.
The CPU locks the memory whenever it want~ to do a locked operation by setting locked by CPU flip-flop 801, which as described above, i~ a J~K flip-flop. In the preferred embodiment, the CPU is a microprogrammed system and during the time that it i5 executing a software instruction that requires a memory lock operation, such as when the CPU is executing a decrement instruction which requires that:
the memory location be read into a CPU regi~ter, a one subtracted from the content~ of the register, and then the register content8 written back into the memory. The CPU
sets flip-flop 801 by performing a microoperation which causes signal SETLCR- at the set (S) flip-flop 801 to transition from the binary ONE to the binary ZERO state.

... , . .. . _ ... ... _ .. . .. . . .

~2~
-60- .

The setting of flip-flop 801 causes it~ Q output, Qignal ~PLRME~, to transition from the binary ZERO to the binary ONE state. An example of this is shown at time C in FIG.
9~ which has occurred slightly after the memory has already been locked by a memory request which occurred from the bus at time B. As will be appreciated later, because of the asynchronous operation of the execution of the CPU microoperations with respect to bus cycles on the common bus 107, a race condition can occur between the bus attempting to lock the memory at the same time the CPU is attempting to lock the memory. Before describing the possible race between the CPU and the bus to lock the memory, the method by which the CPU locks the memory will be described.

15As described above, locked by CPU flip-flop 801 is initialized to the reset state by bus master clear signal BSMCLR-, when the CPU is initialized, as is synchronization flip-flop 802 and locked by bus flip-flop 820. There~fter, during the execution of the software by 20the CPU, when a software instruction require~ tha~ a lock operation be performed on a memory because the CPU want3 to read a location, modify the contents and write it back without being interrupted, the microin~tructionQ executing the software instruction perform a set lock operation by 25generating signal SETLCR- to the binary ZERO state at the set (S) input of flip-flop 801. This lock ~emory microoperation is indicated in FIG. 10 as block lO01. It should be noted that the setting of locked by CPU
flip-flop 801 takes place unilaterally by the CPU without the CPU examining the status of the locked by bus flip-flop 820 to determine whether the memory has already been locked by the bu~. Further, the CPU need not determine whether the memory has already been locked by the CPU by examining the status of locked by CPU flip-flop 801 because the CPU implicitly knows that the microinstruction sequence that locks and then unlocks the memory is not interruptable such that if the memory had been previouqly locked by a CPU microoperation, it would have been followed by an unlock microoperation and, therefore, if the CPU is now in a position to lock the memory, the status of locked by CPU flip-flop 820 mu~t be ~uch that it is in a reset state and that the memory is not currently locked by the CPU.

Synchronization flip-flop 802 is necessary because of the asynchronous nature of the bu~ ~ignals with respect to the execution of the CPU microinstructions. Thereore, by clocking in the output of locked by CPU flip-flop 801, signal CPLRME+, at the data (D) input of flip-flop 802 by use of the bu-~ data cycle now signal ~SDCNN+, which i~
derived by inverting bus signal BSDCNN- by inverter 823, ~211854 --62-- .

the Q-bar output of flip-flop 802, signal LOCRED-, will be stabilized and thereby inCure that the signals at the data (D) inputs of flip-flops 809 and 810 will be in a stable state when they are clocked approximately 60 nanoseconds later by signals BSDCND+ tran~itioning ~o the binary ONE
state. Therefore, synchronization fl~p-flop 802 ensures that if the CPU locks the memory before the occurrence of the data cycle now ~ignal BSDCNN- on the bus going ~o the binary ZERO state, the locked by CPU 3ignal will be visible and stabilized such that it will affect the status of the MECYLE+ and MENARR+ signal~ at the inputs of flip-flops 809 and 810 and re~ult in the NARinq of a request from the bus to perform a locked memory operation.
~owever, if the CPU does not ~et the locked by CPU

flip-flop 801 before the occurrence of the data cycle now signal on the bus, the synchronization flip-flop 802 will remain in the reset state and the inputs to flip-flop 809 and 810 will ~ot be affected until the next bus cycle. By clocking flip-flops 809 and 810 60 nanoseconds after clocking synchronization flip-flop 802, there is provided sufficient tim~ to ensure that the Q-bar output of flip-flop 802 has reached a steady ~tate, which may take from 20 to 30 nanoseconds, and that that output has had sufficient time to propagate through NAND gate 804, AND

gate 805, NOR gate 806, or through NAND gate 804~ NAND
gate 807 and NOR g~te 808 prior to the clocking of ~2118~4 -63- ~

flip-flops 809 and 810. Once the CPU has set locked by CPU flip-flop 801 and its output has been clocked into synchronization flip-flop 802 by the occurrence of data cycle now on the bus, the binary ZERO state of Qignal ~OCRED- will cause the output of NAND gate 804 to become a binary ONE and stay in that state until ~uch time a both synchronization flip-flop 802 and locked by bus flip-flop 820 are reset. Thus, the output of NAND gate 804, 3ignal LOCRED+, when a binary ONE indicates that the memory ha~
been locked by either the CPU or the bus or both.
The use of the ~OCRED+ ~ignal by the re~t of the lock logic 110 is the same as has been discussed above with respect to locking the memory Erom the bus. Locking the memory by the CPU does not result in the generation of an ACR, WAIT or a NAK response to the CPU, however, because these signals are only generated in response to a master unit requesting use of the memory over common bus lQ7. No bus cycle is involved with the CPU's use of memory, therefore the locking of the memory by the CPU will not result in the generation of a response from the memory as slave to the master unit, whereas a response is generated when the memory i~ locked by the bus because the locking of the bus tahes place as part o a bus cycle. Therefore, the setting of locked by CPU flip-flop 801 is done in preparation for a sub~equent bus memory cycle so that any ~2~
-64- .

I/O device acting as a master in attempting to perform a locked operation on the memory via the bus will receive the correct response, whether the memory was locked by an I/O device on the bus or by the CPU.

As discus~ed above, locked by CPU flip-flop 801 is set by the CPV executing a microoperation which causes signal SETLCX- to become a binary ZERO. The CPU execute~
this set lock microoperation when it is performing a lock operation which requires a read-~odify-write of a memory location. During each memory acce~, for either a read or write, and whether the acces~ is being performed on behalf of the CPU or an I/O device connected to the common bus, a timing signal MCASCP- becomes a binary ZERO when the column address is presented to the semiconductor chips which make up the main memory. Therefore, during each memory acces-~, locked by CPU flip-flop 801 will be clocked by signal MCASCP- becoming a binary ZERO at the clock (C) input. During a memory write, which i-~ being performed on behalf of the CPU, and not on behalf of an I/O controller on the common bus, signal MMWRIT+ is a binary ONE at the time that column addre3s ~ignal ~CASCP- becomes a binary ZERO. Therefore, by inputting CPU memory write signal, MMW~IT+, in~o the R input of flip-flop 8Ql, the locked by CPU flip-flop will be reset each time a memory write is performed on behalf of tha CPU. Therefore, it can be . -65- . .

appreciated that locked by CPU flip-flop 801 is set by the execution of a CPU microin~truction in anticipation of performing a read-modify-write operation and the flip-flop is unconditionally reset whenever a memory write is done on behalf of the CPU. This simplification of the lock logic 110 is po~ible because it i8 implicit that the only time that the CPU locks the memory is in preparation of doing a read-modify-write operation and, therefore, the logic can unconditionally reset the locked by CPU
flip-flop at the end of any CPU write operation because it will be the final act of the read-modify-write sequence which could have asked for the memory to be locked.

Memory busy flip-flop 803 was described earlier with re~pect to it~ output signal WAITER-. When memory busy flip-flop 803 i8 set, its Q-bar output, signal WAITER-, will be a binary ZER0 to indicate that the bus memory port of the dual ported memory is busy performing a memory operation on behalf of a device connected to common bus 107. Thus, the setting of memory busy flip-flop 803 prevents a ~ub~equent memory request from the bus to be positively acknowledged until the current memory request is completed. As seen in ~he above discu~sion, when memory bu~y flip-flop 803 i5 set, the binary ZER0 of signal WAITER- will disable NA~D gate 811 and prevent and ACK from being generated to the ma~ter unit reque~ting acces~ to me~ory and instead will result in the enabling of ~OR g~te 812 which will result in a WAIT signal being generated by the memory in response to a request from an I/O controller for access ~o the memory.

5When the sy~tem i~ initialized, signal MEMRDY- is set to the binary Z~RO state and thereby setting flip-flop 803 and holding it set until 3uch time as the system ha~ been powered up and the me~ory i8 Up to speed and ha~ been cleared out. Thereafter, signal MEMRDY+ returns to a 10binary ONE and memory busy flip-flop 803 will be set during a bus cycle if the data (Dl signal MEBUS~+ i9 a binary ONE when the data cycle now signal BSDCNN+ becomes a binary ONE at the clock (C~ input. Signal MEBUSY+
result~ from the accumulation of a collection of memory 15signals a~ ociated with the bus port of the dual ported memory, the result of which is that signal MEBUSY+ will be in the binary ONE state whenever the bus port of the dual ported memory is engaged in a memory operation and is not free to accept a memory request from the common bus 107.
20When the mem~ y ha~ completed the memory operation sn behalf of a device connected to common bus 107, ~ignal MEBUSY+ returns to the binary ZERO state and the next time the memory bus flip-flop 803 is clocked by bus data cycle now signal BSDCNN+, memory busy flip-flop 803 will be 25reset. This resetting occur~ early enough in the bu3 ~Z~18S4 cycle such that memory bu3y flip-flop 803 will be reset prior to the generation of the ACR or WAIT ~ignal of a bus cycle in which a request for memory from an I/O controller takes place.

The above di~cussion has indicated how the bu~ can lock the memory by setting locked by bus flip-flop 820 ~nd how the CPU can lock the memory by setting locked by CPU
flip-flop 801. The method by which the locked by bus flip-flop 820 is reset has been discu~sed as has been the method by which the locked by CPU flip-flop 801 i3 unconditionally reset whenever a memory write operation performed on behalf of the CPU. It has al90 been discu~sed as to how a ~ubsequent lock operation from the bus is given a negative acknowledgement (NAR) if an attempt i3 made to perform a lock operation during the time in which the memory i~ already locked by either the CPU or the bus. The method by which the CPU determines whether the memory has been locked by the bus when the CPU
attempts to per$orm a locked operation will now be discussed.
Becau~e the CPU does not see the ACR, WAIT or NAK
signal~ which are generated only when thè memory i8 responding to a ~emory request origina~ed from the bus, the CPU looks directly at the outputs of the locked by bus flip-flop 820 by examining the Q output signal LOCRDD~.

lZ1~354 -68- .

Basically, what the CPU does is to unconditionally set locked by CPU flip-flop 801 via a firmware microoperation and then by another firmware microopera~ion looks at the ~tatus of the locked by bu~ flip~flop 820 and loops until the memory is not locked by the bu~ The CPU then perform~ its read-modify-write operation with the memory write by the CPU resetting the locked by CPU flip-flop 801. This sequence i8 illu3trated in FIG. 10 which shows four block~, each block corre3ponding to a ~ingle microoperation of the CPU firmware. These four blocks, 1000 through 1004, represent microoperation~ which may be part of a ~oftware instruction which performs a memory lock operation such as di~cussed earlier, f~r example, a decrement word operation in which a word is read from memory, the word is decremented by one, and the decremented value is written back into the memory.

In block 1001, the CPU firmware unconditionally sets locked by CPU flip-1Op 801. Thi~ microoperation may be followed immediately by the microoperation repre~ented by block 1002 or there can be intervening microoperations a3 shown by the broken line running from block 1001 to block 1002. In block 1002, a microoperation is performed which reads the ~ontent~ of the memory location which is to be operated on and within the same microoperation, a te~t i~
made to see whether locked by bu~ flip-flop 820 i~ ~et.

~2~85~
-6~- .

If the ~ignal LOC~DD+ i5 ig a binary ONE, indicating that the me~ory has been locked by the bus, the microoperation branches back to the beginning such that block 1002 will be re-executed and the location will again be read from memory and locked by bu~ flip-flop 820 retested. Thi~
looping within block 1002 will continue until such time as the locked by bus flip-flop 820 is reset at which time the microoperation 1002 will not branch back and the microoperation of block 1003 will be executed. ~lock 1003 may in fact be ~e~eral microoperation3 which compute the new value of the word which was read ~rom ~emory ~o an updated value can be sub3equently written into memory.
Again, there may be intervening microoperations between blocks 1002 and 1003 and between blocks 1003 and 1004 as indicated by the broken line. In block 1004, the updated value is written into memory and because each memory write operation unconditionally re~ets locked by CPU flip-flop 801, the memory i~ unlocked by the CPU. As discussed above, during the time that the CPU has locked the memory in block 1001 until it has been unlocked in block 1004, any attempt by a unit on common bus 107 to unlock the memory will result in a NA~ being generated by lock logic 110 when the memory respond~ a~ the slave unit to the I/O
controller which was making the reque~t as a master un~ t.

~Z1~8~4 . -70-Returning now to FIG. 9, it can be seen that the CPU
perform~ a CPU memory lock operation beginning at time AA
and ending at time EE. From time AA to time BB, the CPU
is executing the memory lock operation of block 1001 of FIG. 10 which reqults at time C in the ~etting of the locked by CPU flip-flop 801 which cau~es the Q output thereof, signal CPLKMEI, to become a binary ONE. From time BB through time CC, the CPU firmware is engaged in a loop in which the CP~ firmware reads the memory whenever the memory becomes available to the CPU as determined by priority resolver logic 111 and at the sa~e time te~ts locked by bu~ flip-flop 820 and continues to re-execute the block 1002 until ~uch time during the last execution of ~he block, it finds that the signal LOCRDD+ hag returned to the binary ZERO state at time N. From time CC
through time DD, the CPU executes the microin~tructions between blocks 1002 and 1004 including block 1003 which modifies the da~a to be written into the memory. During time DD thrQugh time EE, the CPU executes ~lock 1004 and write~ the data back into the memory. The writing of the data into memory by the CPU results in the re~etting of locked by CPU flip-flop 801 which cau3es signal CPLMR~+ to transi~ion from the binary ONE to the bin~ry Z~RO ~tate at t.ime X. After time X, any subsequent regue~ts for use of the bus, ~uch a3 at time Y in FIG. 9, will result in the data cycle now signal ~SDCNN- transitioning from the 12~18~

binary ONE to the binary ZERO state such as at time Z, which will in turn result in the resetting of synchronization flip-10p 802 which will cause the output of NAND gate B04, ~ignal LOCRED~, to tran~ition from the binary ONE to the ~inary ZERO ~tate such as at time Z.

Also shown in PIG. 9 is an attempt by an I/O
controller to perform a locked memory operation during the time in which only the CPU has the me~ory lockeZ. Thu~, at time R, the I/O controller, as a master unit, make3 a request for the bu~ which cauRe3 the data cycle now signal BSDCNN- to transition from the binary ONE to the binary ZERO state and re~ults in the I/O controller putting the memory address to be read onto the bus and alQo causes it to set the locked signal BSLOCK- to the binary ZERO state at time S to indicate that a locked operation i5 desired.
Because the bus is at th~s time locked by the CPU, as indicated by the fact that the output of NAND gate 804, signal LOCRED+, i9 in the binary ONE state, the output of NAND gate 807, signal MENARR- will be a binary ZERO and cau~e the outpu~bof NOR gate 808 to be a binary ONB which will re~ult in the setting of flip-flop 810 at time T, which in turn will result in the generating of a NAR onto the bu~ and cause signal BSNACRR- to transition from the binary ONE to the binary ZERO ~tate a~ time T. When the negative acknowledgement ia received from the memory as 12~85~

the 31ave unit by the I/O controller as the master unit at time U,~the I/O controller will remove the bus lock signal and the data cycle now signal and the bus request ~ignals from the bus such that at time ~, ~ignals B5LOCR-, BSDCNN-and BSREQT- will transition from the binary ZERO to the binary ONE state. At time W, when flip-flop 810 i~ reset by signal BSDCNBI transitioning to the binary ZERO state at its reset ~R) input, flip-flop 810 will be re~et and cause signal BSNACRR- to transition from the binary ZERO
to the binary ONE state.

10Although this attempted I/O memory lock operation is indicated after the completion of the previsus I/O memory lock operation, any attempt by another I/O controller to perform a memory lock operation during the time that the memory is locked on behalf of the bus will result in the 15same sequence occurring with the I/O controller attempting to do the lock operation receiving a NAK from the memory.
This is so because the output of NAND gate 804 indicates that ~he memory i3 locked on behalf of the CPU or the bus, or both, all of which will result in a NAR being generated 20in re~ponse to any subsequent attempts to initiate a locked operation on behalf of a device connected ~o common bu~ 107.

~ecause of a possible race condition which can result in which both the CPU and the bus are attempting to more ~Z1185~

or less simultaneously lock the memory, there is a constraint as to the minimum time whieh must elapse between when the CPU microinstructaon which sets the locked by CPU flip-flop 801 i~ executed and the microinstruction ~hich looks at the output of locked by bus flip-flop 820. There are two cases of interest in this more or le~s ~imultaneously attempting to lock th~
memory. The first case in which the CPU locks the memory just slightly before the bu~ locks the memory and the second case in which the CPU locks the me~ory ju~t slightly after the bu~ locks the memory. The second case imposes this time constraint as to the mini~um time that must elapse between when the CPU 3ets the locked by CPU
flip-flop 801 and when it looks at the output of locked by bus flip-flop 820.

During the first case, if the CPU just sets the locked by CPU flip-flop 801 by executing the microoperation of block 1001 of FIG. 10 slightly before an I/O controller on the bus makes a memory lock operation request of the memory, the locked by CPU flip-flop 801 will be set before signal BSDCNN- from the bus indicating data cycle now ciocks synchronization flip-flop 802. In thi~ ca-~e, the beg$nning of the bus cycle associated with the bus attempting to lock the memory will result in the setting of synchronization flip-flop 802 which in turn ~Z11~354 will result in its output ~ignal, LOCRED-, becoming a binary ZERO. Signal LOCKED- being a binary ZERO will result in the output of NAND gate 804 becoming a binary ONE and which in turn will result in a negative acknowledgement (NAK)` being generated in response to the lock request and from the bus. Locked flip-flop 820 will not be clocked because a NAK wa~ generated instead of an ACX and therefore the bus will not lock the memory and the memory cannot be locked by the CPU until the CPU completes it~ total memory lock operation (i.e., a read-modify-write into the memory~. In thi3 ca~e in which the CPU locks the memory ~lightly ahead of the lock request from the bu~, there is no constraint with respect ~o the elapsed time between the execution of microinstruction 1001 which sets the locked by CPU flip-flop and the execution of the microoperation a~ ociated with block 1002 which looks at the status of the locked by bus flip-flop 820.

The ~econd case in which the race between the CPU and the bus for locking the memory occurs when the bus makes the lock reguest slightly ahead of when the CPU locks the memory by setting locked by C~U flip-flop 801. This ca~e is illustrated in FIG. 9 in which an I/O controller ha~
made a request ~o lock the memory at time A, the data cycle now ~ignal BSDCNN- is generated by the I/O
controller at time B which i8 slightly ahead of the time ~Zll~
--75-- .

that the microoperation associated with block 1001 in FIG~
10 iQ executed and which ~ets the signal SETLCK to the binary ZERO state such that locked by CPU flip-flop 801 is set at time C resulting in signal CPLMRE+ becoming a binary ONE. In this case, the binary ONE that becomes available at the data (D) input of ~ynchroni~ation flip-flop 802 just mis~ed getting clocked into flip-flop 802 such that its Q-bar output signal LOCRED-, remains a binary ONE. Becau~e at time C, locked by bus flip-flop 820 will not yet have been clocked by the ACR which will be generated to the I/O controller, the other ~ignal into NAND gate NAND gate 804, signal LOCRDD-, will also be a binary ONE therefore fully enabling NAND gate 804.
Therefore, at time C, the memory has not been locked by the bus and the synchronization flip-flop has not been set resulting in the output of NOR ga~e 806 being a binary ONE
which will cause the setting of flip-flop 809, which in turn will result in the generation of an ACR to the I/O
controller which ig requesting the lock operation be perfor~ed. The generation of the ACR signal will in turn clock locked by bus flip-flop 820 resulting in its being set 80 that its Q output signalQ, LOCRDD+ will change to the binary ONE ~tate at time D.

In this second case in which the bus has won the race to lock the memory, if the time between when the CPU set~

~2~18S4 --76-- .

locked by CPU f lip-f lop 801 and when it look~ at the output~of locked by bus flip~flop 820 i~ too short, the locked by bus flip-flop 820 may not yet have been ~et by the clocking ACR ~ignal. Therefore, the CPU
mic~ooperation that examines the state of locked by bus flip-flop 820 associatea with block 1002 cannot occur any sooner after the setting of locked by CPU flip-flop 801 than it takes for the output of locked by bus flip-flop 820 to become ~table so that the se~ting of locked by bu~
flip-flop 820 will be vi~ible to the microoperation of block 1002 in FIG. 10. In the preferred embodiment, this ~inimum time i5 approximately 60 nanosecond~ because the clocking signal BSDCND+ at the clock inputs of flip-flops 809 and 810 occurs approximately 60 nano3econds ater the clocking signal BSDCNN+ of ~ynchronization flip-flop 802.
The 60 nanosecond time ignores the propagation delays associated with NA~D gate 811 and the ~ettling time of locked by bu~ flip-flop 820. Therefore, as long as the CPU firmware doe~ not look at the output of locked by bus flip~flop 820 sooner than 60 nanoseconds after ~etting locked by CPU flip~flop B01, the locking of the memory by the bu~ will be visible to the CPU and no action will be taken during this time by the CPU when the outcome of the race between the CPU and the bu~ to lock in the memory is undetermined.

~2~

In the preferred embodiment in which the CPU requires about 240 nano~econds to execute each microin~truction of FIG. 10, this presents no problem because there iq assured to be sufficient time between tha execution of the microoperation of block 1001 which sets locked by CPU
flip-flop 801 and when ~he output of locked by bus flip-flop 820 is examined by ~he microoperations of block 1002. However, if ~he reverse were the ca~e in which the microoperations took le39 time than the time between the clocking of synchroni~a~ion flip-flop 802 and the clocking o locked by bus flip-flop 820, the firmware opera~ions of FIG. 10 could still be used a~ long a-~ there were sufficient microoperation3 executed between block 1001 and block 1002 to ensure that the block 1002 would not examine the output of flip-flop 820 before it has had ~ime to set and stabilize when the bu~ just beat the CPU in locking the memory. It should be noted that although block 1002 unconditionally read the memory each time it is executed, during the time that the bus has the memory locked, the memory data i~ thrown away because a re-read occurs, these i8 never a case in which data read from memory when the memory was locked by the bus will later be used by the CPU because the memory i~ always re-read if the memory was locked. It should be al~o noted that although the firmware of FIG. 10 combines the reading of memory and the testing of the bus lock in one mlcroinstruc~ion, the~e lZ118~i4 operation~ could take place in separate microin3tructions ~o long a~ the looping on the bus lock microoperation precedes the memory read microoperation.

From the above discu3sion, it can be appreciated that the lock logic 110 of FIG. 8 and the firmware operations of FIG. 10 combined provide a simple mechanism by which two units operating a~ynchrohously oan perform lock and unlock operation~ on a shared resource. In the preferred embodiment thi-~ is accompli~hed by the CPU firmware, once the CPU has determined that sooner or later it requires that it do a lock operation on the memory, unconditionally sett~ng a CPU lock flip-flop without regard to whether the memory has already been locked by the bus. After sufficient time has elapsed to allow the CPU to be guaranteed that a bus lock operation that just bea~ out the locking of the memory by the CPU has had an opportunity to set the locked by bus flip-flop, the CPU
then issues a read command and ~imultaneously examines the locked by bus flip-flop. If the locked by bus flip-flop ha~ ~ot been set, the CPU is guaranteed that the CPU has won any race and that any subsequent attempt by the bus to perform a lock operation will be given a negative acknowledgement (NAK). The CPU can then examine the locked by bu~ flip-flop and if the memory has not been locked by the bus, the CPU can then use the data read, lZ~854 modify the data and then write the modified data back into the memory and at the same time the CPU resets the locked by CPU flip-flop. If the CPU firmware finds that the bus hac won the race and locked the memory, the CPU firmware continues to loop until such time as it find~ that the locked by bus flip-flop has been reset at which time the CPU can read the memory, modify the data, and write the modified data back into the memory and re~et the locked by CPU flip-flop.

The CPU is guaranteed that once the memory has become unlocked by the bu~ that no subsequent bus reque~ts can lock the memory because any further attempt to lock the memory from the bus will not result in the memory beinq locked by the bus and the unit on the bus requesting to lock the memory will be given a negative acknowledgement which will re.ult in that unit later retrying the lock operation. The lock logic 110 of FIG. 8 operates such that an attempt to lock the memory from the bus will only result in the memory being locked if the memory has not already been locked by either the CPU or the bus. Any attempt to lock the memory from the bus, if the memory is already locked, will re~ult in a negative acknowledgement being generated to the IjO controller on the bu~ will later retry to lock the memory. Once locked by the bu~, the memory will remain locked until ~uch time as the I/O

~LZ~8~4 o80~

controller on the bu~ signals the memory via way of an unlocked sequence, at which time the memory will be unlocked by the bus. Durlng the time that the memory is locked by either the CPU or the bus, any unit on the bu~
can make a memory access reque3t which does not require a lock or unlock memory speration. In ~he preferred embodiment there is only one CPU and the sequence between when the CPU set~ locked by CPU flip-flop 801 and when the memory write operation at the end of a memory locked operation is performed is non-interrup~able by any CPU
operation which will do a memory write which would prematurely reset locked by C~U flip-flop 801.

In the preferred embodiment, the memory i5 a ~bared resource which can be allocated to either a single CPU or to one of a plurality of devices connected to a common bus, however r it is po~sible to extend thi~ logic to handle the case of multiple CPUs or other type devices.
Further, although the invention has been described in terms of the preferred embodiment in which the memory i5 a shared resource and is 3hared among the plurality of units connected to a common bu~ and a CPU this invention is equally applicable to sharing other types of resources that muct be allocated to an individual user for a certain operation during which other users can ~ot be allowed access to the resource.

~2~854 --81-- .

Wh$1e the invention has been shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that the above and other changes in form and detail may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

Claims (22)

-82-

1. A lock apparatus for use in a system having a plurality of units, a shared unit of said plurality of units capable of being accessed by a first unit and a second unit of said plurality of unit , said first unit and said second unit operating asynchronously with respect to one another, said lock apparatus comprising:
A. first lock request receiver means, included in said shared unit, for receiving a first lock signal, said first lock signal indicating that a unit of said plurality of units which transmitted said first lock signal, desires uninterrupted access to said shared unit such that no unit of said plurality of units can perform a lock operation on said shared unit during the time said shared unit is locked by another unit of said plurality of units;
B. first lock storage means, included in said shared unit and coupled to said first lock request receiver means, for storing an indicator that said first lock signal has been received when an access permitted signal is received;
C. second lock storage means, included in said shared unit, for unconditionally storing an indicator that said second unit desires uninterrupted access to said shared unit such that no other unit of said plurality of units can perform said lock operation on said shared unit during the time said shared unit is locked by another unit of said plurality of units;
D. synchronization means, included in said shared unit and coupled to said first lock request receiver means and to said second lock storage means, for storing said indicator of said second lock storage means when said first lock control signal is received by said first lock request receiver means; and E. response means, included in said shared unit and coupled to said synchronization means and said first lock storage means, for generating an access denied signal if said first lock signal is received and if said first lock storage means indicates that said first lock signal has been received or if said synchrnonization means indicates that said second lock storage means indicates that said second unit desire-uninterrupted access to said shared unit, said response means for generating said access permitted signal if said first lock signal is received and if said first lock storage means does not indicate that said first lock signal has been received and if said synchronization means does not indicate that said second lock storage means indicates that said second unit desires uninterrupted access to said shared unit.

2. The lock apparatus as in Claim 1 further comprising:
A. first unlock receiving means, included in said shared unit and coupled to said first lock storage means and said response means, for receiving a first unlock signal, said first unlock signal indicating that said unit of said plurality of units which transmitted said first lock signal no longer desires uninterrupted access to said shared unit such that other units can now perform said lock operation on said shared resource; and B. first unlock means, included in said first lock storage means and coupled to said first unlock request receiving means and said response means, for resetting said indication that said first lock signal has been received when said access premitted signal is received if said first unlock request receiving means has received said firs unlock signal.

3. The lock apparatus as in Claim 1 further comprising a looping means coupled to said second unit and said first lock storage means, said looping means for inhibiting said second unit from accessing said shared unit until after sufficient time has elapsed between when said second unit indicated to said second lock storage means that said second unit desired uninterrupted access to said shared unit and when said first lock storage means could have responded to said access permitted signal to set said indicator that said first lock signal had been received after which said looping means then permits said second unit access to said shared resource only if said first lock storage means does not indicate that said first lock signal had been received.

4. The lock apparatus as in Claim 3 further comprising a second unlock means, included in said second lock storage means and responsive to a second unlock signal, for resetting said indicator that said second unit desired uninterrupted access to said shared unit.

S. The lock apparatus as in Claim 4, further comprising second unlock signal generation means, inlcuded in said shared unit and coupled to said second unlock means, for generating said second unlock signal when said shared unit performs an operation that is unique to said second unit and wherein said unique operation is the final operation of all said lock operations performed by said second unit.

6. The lock apparatus as in Claim 1 wherein said response means further includes a wait means for generating an access retry signal if said shared unit is busy when said first lock signal is received.

7. The lock apparatus as in Claim 1 whereas said shared unit is a memory and wherein said first unit is an I/O controller and is coupled to said memory by a common bus and wherein said second unit is a central processing unit.

8. The lock apparatus as in Claim 1 wherein said first lock storage means comprises a J-K type flip-flop and wherein said second lock storage means comprises a J-K type flip-flop.

9. The lock apparatus as in Claim 8 wherein said synchronixation means comprises a D-type flip-flop.

10. The lock apparatus as in Claim 3 wherein said looping means comprises a microoperation which branches as a function of said indicator of said first lock storage means.

11. A system comprising a plurality of units coupled by means of a common bus to transfer information between any two of said plurality of units, a shareable unit of said plurality of units capable of being accessed by any other unit of said plurality of units, said shareable unit also capable of being accessed by a main unit by means other than said common bus, said system capable of having a one of said plurality of units and said main unit making simultaneous asynchronous requests for access to said shared unit, said shareable unit including lock operation logic comprising:
A. first means for receiving a first lock signal by means of said common bus from said one of said plurality of units which desires uninterrupted access to said shareable unit;
B. first bistable means, coupled to said first means for receiving, for indicating in response to a positive acknowledgement signal being generated by a response means that said shareable unit is being accessed by said one of said plurality of units from which said first lock signal has been received;
C. second bistable means, for indicating that said main unit desires uninterrupted access to said shareable unit;

D. third bistable means, coupled to said second bistable means, for storing the indicator of said second bistable means when said first lock signal is received; and E. response means, coupled to said first bistable means and said third bistable means, for generating a positive acknowledgement signal to said plurality of units over said common bus if said first bistable means and said third bistable means do not indicate that any unit desires uninterrupted access to said shareable resource when said first lock signal is received and for generating a negative acknowledgement signal to said plurality of units over said common bus if either said first bistable means or said third bistable means indicates that one of said plurality of units or said main unit desires uninterrupted access to said shareable resource;

12. The lock logic as in Claim 11 further comprising:
A. second means for receiving a first unlock signal by means of said common bus from one of said plurality of units, said second means for receiving coupled to said first bistable means;
and B. first reset means, coupled to said second means for receiving and said first bistable means, and responsive to said first unlock signal and said positive acknowledgement signal, for resetting said first bistable means so that it no longer indicates that one unit of said plurality of units desires uninterrupted access to said shareable unit.

13. The lock logic as in Claim 12 further comprising:
A. looping means, coupled to said main unit and said first bistable means, for examining said indication of said first bistable means in response to the setting of said second bistable by said main unit, said examination by said looping means only starting after sufficient time has elaspsed to allow for the setting of said first bistable means by said positive acknowledgement signal if one of said plurality of units requested uninterruptable access to said shareable unit just before said main unit requests uninterrupted access to said shareable unit; and B. second reset means, coupled to said second bistable means and responsive to a second unlock signal which indicates that said main unit no longer desires uninterrupted access to said shareable unit, for resetting said second bistable means in response to said second unlock signal.

14. The lock operation logic as in claim 13 further comprising means coupled to said response means for enabling access to said shareable unit by any of said plurality of units or said main unit which does not indicate that it desires uninterrupted access to said shareable unit.

15. The lock operation logic as in Claim 14 wherein said system further comprises logic in each of said plurality of units for enabling the transfer of units, except said shareable unit, during the time uninterrupted access to said shareable unit is desired by any of said plurality of units.

16. The lock operation logic as in Claim 15 wherein said shareable unit is a memory and said main unit is a central processing unit.

17. A method for inhibiting access to a shared resource within a system having a plurality of units operating asynchronously with respect to a main unit, said main unit and a one unit of said plurality of units capable of simultaneously requesting uninterrupted access to said shared resource, said method comprising the steps of:
A. allowing said main unit to unconditionally set a first indicator that said main unit desires uninhibited access to said shared resource;
B. receiving a first lock signal from said one unit indicating that said one unit desires uninterruptable access to said shared resource;
C. synchronizing said main unit's request and said one unit's request for uninterrupted access to said shared resource by storing the status of said first indicator in a second indicator when said first lock signal is received;
D. generating a positive response to said one unit when said first lock signal is received if said second indicator does not indicate that said main unit desires uninterrupted access and if a third -94- , indicator does not indicate that said first lock signal has been received;
E. generating a negative response to said one unit when said first lock signal is received if said second indicator indicates that said main unit desires uninterrupted access to said shared resource or if said third indicator indicates that said first lock signal has been received; and F. storing said indication that said one unit desires uninterrupted access to said shared resource in said third indicator if said positive response is generated.

18. The method of Claim 17 further comprising:
A. examining said third indicator after sufficient time has lapsed after the setting of said first indicator so that if said main unit unit requests uninterrupted access just after said one unit, said third indicator could have been set by said positive response, said examination continuing until said third indicator does not indicate that said one unit desires uninterrupted access to said shared resource; and B. resetting said first indicator when said main unit no longer desires uninterrupted access to said shared resource.

19. The method of claim 18 further comprising resetting said third indicator if a positive acknowledgement is generated in response to an unlock signal from one of said plurality of units.

20. In a data processing system having a plurality of first type units and a second type unit wherein said second type unit is adapted to be utilized by all of said first type units, wherein when one of said first type units performs a particular kind of operation (lock operation) utilizing said second type unit the others of said first type units must be prevented from performing said particular type of operation, and wherein when one of said first type units requires to perform said particular type of operation it generates a corresponding request signal (BSLOCK, SETLCK); apparatus for controlling said second type unit to appro-priately respond to only one of said request signals, characterized by:
a first storage element for receiving a request signal (BSLOCK) from one of said first type units and, when enabled by a first signal (MEACKR) which denotes that said second type unit is in a state to accept said request, storing a representation that said request has been granted;
a second storage element for receiving a request signal (SETLCK) from another one of said first type units and, regardless of the state of said second type unit, storing a representation that said other first type unit has made such a request;
a third storage element for receiving a signal corresponding to the representation stored by said second storage element and, when enabled during a time (BSDCNN) in the cycle of operation of said first type units in which a request signal may be supplied to said first storage element, storing a representation that the request represented by the signal of said second storage element has been granted; and a logic circuit coupled to said first and third storage elements and responsive to signals (LOCKDD, LOCKED) corresponding to the representations held therein for (i) enabling generation of said first signal (MEACKR) if neither said first storage element nor said third storage element holds a representation that a request has been granted or (ii) preventing generation of said first signal if either of said first or third elements holds a representation that a request has been granted.

21. The apparatus of claim 20, wherein the data processing system which includes said apparatus, said plurality of first type units comprises a plurality of controllers coupled to said second type unit by a common bus and a processor separately coupled to said second type unit, wherein said second type unit is a memory unit, and wherein each of said controllers generates the BSLOCK
request signal and said processor generates the SETLCK request signal.

22. The apparatus of claim 21, wherein each of said first type units generates a signal to clear the corresponding one of said first, second and third storage elements when the such unit has completed its particular type of operation.