CA1134052A - Address control system for software simulation - Google Patents
Address control system for software simulationInfo
- Publication number
- CA1134052A CA1134052A CA341,030A CA341030A CA1134052A CA 1134052 A CA1134052 A CA 1134052A CA 341030 A CA341030 A CA 341030A CA 1134052 A CA1134052 A CA 1134052A
- Authority
- CA
- Canada
- Prior art keywords
- address
- program
- virtual machine
- translation
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
Abstract
ABSTRACT OF THE DISCLOSURE
An address control system for software simulation in a virtual machine system having a virtual storage function. In the case of a simulator program simulating an instruction of a program to be simulated, an address translation of an operand address of the program to be simulated is achieved using a translation lookaside buffer, thereby to greatly reduce an overhead for the address translation in the simulator program execution.
An address control system for software simulation in a virtual machine system having a virtual storage function. In the case of a simulator program simulating an instruction of a program to be simulated, an address translation of an operand address of the program to be simulated is achieved using a translation lookaside buffer, thereby to greatly reduce an overhead for the address translation in the simulator program execution.
Description
3~!L~
This invention relates to an address control system for software simulation, and more particularly to an efEective address control system for software simulation in a virtual machine system having a virtual storage function.
Description of the Prior Art In recent years, the concept of "virtual machine" has been intro-duced and attempts have been made to put it into practice. The concept of virtual machine is described in detail, for example, in "IBM System Journal"
1972, No. 2. The utility of a virtual machine may be summarized as follows:
1) It is possible, -through utilization of one hardware system, to create such an environment as if each of a plurality of users sharing one computer system uses it all for himselE~
This invention relates to an address control system for software simulation, and more particularly to an efEective address control system for software simulation in a virtual machine system having a virtual storage function.
Description of the Prior Art In recent years, the concept of "virtual machine" has been intro-duced and attempts have been made to put it into practice. The concept of virtual machine is described in detail, for example, in "IBM System Journal"
1972, No. 2. The utility of a virtual machine may be summarized as follows:
1) It is possible, -through utilization of one hardware system, to create such an environment as if each of a plurality of users sharing one computer system uses it all for himselE~
2) It is possible to virtually establish computer systems of slightly different architectures or system configurations. Accordingly, the use of the virtual machine enables simultaneous running of programs that run under different operating systems, and permits more flexible modification of the system configuration; furthermore, the operating state oE the system can be monitored, and each user is free to use the debug function of the machine.
Since a plurality of user programs run under the operating system (OS), a computer resource (a central processor, a main memory, channels, an input/output controller, an input/output device, and a system console) is managed so that it is shared by respective programs. Between the operat-ing system and the real machine is provided a conceptual interface called a hardware interface, and between user programs and the operating system is ~! ~
~ , , , ~3'~
provided an interface called a user program/OS inter-face. In the case of the virtual machine system, a program called a virtual machine monitor (VMM) controls a plurality of operating systems so that the system resource is shared by the respective programs. Under the virtual machine system, a plurality of virtual machines can be run simultaneously.
Nowadays, multiprogramming techniques are utili~ed for eEficient running of the computer system, and the multi-programming techniques permit sharing oE the system resource by the respective programs. The system re-source is controlled by the operating system and can be accessed by an instruction commonly called a "privileged instruction" which only the operating system can issue.
Each user program is assigned a "problem mode", and when the user program issues the aforementioned privileged instruction, a program inter-ruption called a "privileged-operation exception" is detected.
In the case of the virtual machLne, a plurality of conventional operating systems can be run at the same time; consequently, the system resource controlled by the operating systems in the past are controlled by the program referred to as the virtual machine monitor (~MM). The user programs, including the operating systems used, are all assigned the "problem mode", and only the virtual machine monitor operates in a "privi-leged mode". Accordingly, when the operating system of each user tends to execute the "privileged instruction", a program interruption is detected and execution control is transferred to the virtual machine monitor, which simulates this "privileged instruction".
The vir-tual machine monitor has such functions as follows:
The virtual machine monitor:
(1) Controls the user programs (including the operating systems) '3"' ~
~q;~
to share the system resource eEEiciently;
(2) Simulates the "privileged instruction" Erom each operating system;
Since a plurality of user programs run under the operating system (OS), a computer resource (a central processor, a main memory, channels, an input/output controller, an input/output device, and a system console) is managed so that it is shared by respective programs. Between the operat-ing system and the real machine is provided a conceptual interface called a hardware interface, and between user programs and the operating system is ~! ~
~ , , , ~3'~
provided an interface called a user program/OS inter-face. In the case of the virtual machine system, a program called a virtual machine monitor (VMM) controls a plurality of operating systems so that the system resource is shared by the respective programs. Under the virtual machine system, a plurality of virtual machines can be run simultaneously.
Nowadays, multiprogramming techniques are utili~ed for eEficient running of the computer system, and the multi-programming techniques permit sharing oE the system resource by the respective programs. The system re-source is controlled by the operating system and can be accessed by an instruction commonly called a "privileged instruction" which only the operating system can issue.
Each user program is assigned a "problem mode", and when the user program issues the aforementioned privileged instruction, a program inter-ruption called a "privileged-operation exception" is detected.
In the case of the virtual machLne, a plurality of conventional operating systems can be run at the same time; consequently, the system resource controlled by the operating systems in the past are controlled by the program referred to as the virtual machine monitor (~MM). The user programs, including the operating systems used, are all assigned the "problem mode", and only the virtual machine monitor operates in a "privi-leged mode". Accordingly, when the operating system of each user tends to execute the "privileged instruction", a program interruption is detected and execution control is transferred to the virtual machine monitor, which simulates this "privileged instruction".
The vir-tual machine monitor has such functions as follows:
The virtual machine monitor:
(1) Controls the user programs (including the operating systems) '3"' ~
~q;~
to share the system resource eEEiciently;
(2) Simulates the "privileged instruction" Erom each operating system;
(3) Receives all interrupts (including an I/O interrupt, an external interrupt and an interrupt accompanying a virtual memory) and performs processing according to the interruption sources and, if necessary, posts the interruption to each operating system.
The virtual machine has such advantages as mentioned previously, but in the case of running a program under the virtual machine, perEormance - 10 degradation is caused to some extend due to an overhead peculiar to the virtual machine, as compared with the case of running the same program under the operating system oE an ordinary computer heretofore employed. The overhead can be divided into direct and indirect ones as follows:
(1) Direct overhead This occurs mainly in the course of processing by software of the virtual machine monitor and this type of overhead is as follows:
(a) Overhead by simulation of privileged instruction.
As described above, each user program including the operating ~- system used therefore is assigned the 7'problem mode", privileged instruct-~ 20 ions issued by the operating system are all simulated by the virtual machine : monitor.
(b) Overhead for switching each user program.
(c) Overhead for supporting the virtual memory function of the operating system (d) Overhead for translation of channel programs.
, `::
`.~'~.:
A channel program for starting an input/output device by the operating system is a logical address to a host computer; therefore, the virtual machine monitor translates the logical address to a real address of the host computer.
~ . ~
(e) Overhead Eor supporting in~erruptionS
In the virtual machine, each interruption is indexed by t~e virtual machine monitor, so that if this interruption is required, it must be reflected in t~e operating system; this processing is carried out by the virtual machine monitor.
(f~ Overhead for supporting console function The virtual machine monitor supports the console function, including the debug function.
(2) Indirect overhead `
In the existing operating system, various algorithms are incorporated in the system of allocation and management of the system resource so as to enhance its availability, but when run under the virtual machine system, these algorithms may in some cases produce a contrary result~
Next, the prior art will be described in connection with the simulation of the privileged instruction Since each user program, including the operating system used therefor, i5 assigned the "pro~lem mode" as described above, the prlvileged instructions used by the operating system are all ~detected as "privileged-operation exceptions" and indexed in the virtual machine monitor (VM~1~. Then, the vir-tual machine monitor ~VM~1) simulates the privileged instruction in the following manner.
When a program interrupt of the "privileged-operation exception"
is detected, an old program status word (PSW~, an interruption code, ~tc. are loaded in a prefix area. After saving a general purpose register in a working area of the virtual machine monitor tVMM~, the virtual machine monitor (VM~I) reads from a virtual machine (VM) area an operation code of an instruction having issued the privileged-operation exception from the old program status word and, after an operand address computation corresponding to the operation code from the contents of a field of the instruction and the saved general purpose register, transfers control to the instnlction processing routine corresponding to the operation code.
In the instruction processing routine, a required operand is read from or written in, or read from and written in the virtual machine (VM) area.
The processing of some steps by the virtual machina moni-tor (VMM) is accompanied by read/write of an operand in the program area of the virtual machine (VM). The program of the virtual machine monitor (VMM) operates in the real address mode for supporting a virtual memory of the operating system. Accordingly, in the processing of these steps, when the program area of the virtual machine (VM) is accessed, the logical address of the operand is translated into a real address using an instruction explicitIy instructing an address translation (a load real address instruction) and then the main memory is accessed with the real address thus obtained. Since the load real address instruction usually does not use a translation looka-side buffer (TLB) for loading a pair of logical and real addresses, a segment table and a page table on the main memory are always accessed for dynamic address translation (DAT), resulting in an appreciable amount of ove-rhead.
Especially in the case of accessing a plurality of operands of different locations by one instruction, the overhead necessary '~
~L34~6~
for the d~lamic address transla~ion tDAT) becomes remarkable.
SUMMARY OF TH~ INVENTION
This invention has for its object to reduce the 'roverhead due to address translation during the simulation of a pri~ileged instruction".
T~e above objective can be achieved by providing an address control system for software simulation in a data processor which has a translation device for coordinating an address on a program with a main memory address and a function of simulating the exe-cution of an instruction of a program to be simulated by the execution of one or more instructions of a simulator program and which is provided with first means for holding information for dlscriminating the operating state of the simulator program and the operating state of the program to be simulated, second means for holding control information for coordinating the address on the program to be simulated with the address on the main program in the case o simulating the program to be simulated by the simulator program, third means for holding control information for coordinating the addres~ on the simulator program with the address on the main memory, and fourth means for indicating the selection of either the second or third ~eans is selected during the operation of the simulator program, ~.Therein the address translation is controlled by the first, second, third and fourth means~
~46~
BRIEF DESCBI_TI0N OF THE _RAI~INGS
Fig. 1 is a diagram showing the concept of a general machine system heretofore employed;
F~g. 2 is a diagram showing the concept of a virtual mach:Lne system;
Fig. 3 is a flow chart showing processing of a virtual machine monitor (VMM);
Fig. 4 is a block diagram illustrating the construction of an address control circuit according to a first embodiment oE this invention;
Fig. 5 is a block diagram illustrating the construction of an address translation circuit according to this invention;
Fig. 6, on the first sheet of drawings, is a diagram showing dynamic address translation (DAT) control information loaded in a control register;
Fig. 7, on the first sheet oE drawings, is a diagram showing the content of a prefix register;
~; Fig. ~ is a block diagram illustrating the construction of an ` address control circuit according to a second embodiment of this invention;
and Fig. 9 is a diagram showing an example of the content of a register during the execution of a move character instruction.
DESCRIPTION OF THE PP~EFERRED EMBODrMENTS
Fig. 1 schematically shows the concept of an ordinary computer system heretofore emp]oyed; and Fig. 2 schematically shows the concep~ of the virtual machine system. In Figs. 1 and 2, the real machine means compu-ter hardware In Fig. 2, the broken line blocks each correspond ~o the convention-al ordinary computer system and are each referred to as a virtual machine ~....
,. ..;
lg~
(VM). Under the virtual machine system, a plurality of Yirtual machines can be run simultaneously.
Fig. 3 shows a process char~ of the virtual machine monitor (VMM).
In the flowchart of Fig. 3, processing of steps 1, 2 and 3 is accompanied by read/write of an operand in the program area oE the virtual machine (VM).
The program of the virtual machine monitor (~M) operates in the real address mode for supporting a virtual memory of the operating system.
Accordingly, in the processing of the steps 1, 2 and 3, when the program area of the virtual machine ~VM) is accessed, the logical address of the operand is translated into a real address using an instruction explicitly instructing an address translation (a load real address instruction) and then the main memory is accessed with the real address thus obtained. Since the load real address instruction usually does not use a translation looka-side buffer (TLB~ for loading a pair oE logical and real addresses, a segment table and a page table on the main memory are always accessed for dynamic address translation (DAT), resulting in an appreciable amount of overhead.
Fig. 4 illustrates an address control circuit produced in accordance ; with a first embodiment of the present invention. In Fig. 4, reference numeral 1 indicates a first word of a program status word (PS~) register;
2 designates a second word of the PSW register; 3 :
:;
-8a-idcntifies an operand one-address register; 4 denotes an operand.
two-address register; 5 represents a virtual machine dynamic address translation (VMDAT~ latch, 6 shows a status indicate latch; 7 to 9 refer to AND gates; and 10 indicates an OR gate.
Upon detection of a proyram exception during O~ ~ O~ ~c.
user program (including an operating system~, an interruption occurs and, according to address tra.nslation control informa-tion in PSW controlling the dynamic address translation (DAT~
at that time, the VMDAT latch S is set. In concrete terms, duri.ng the operat.ion of-each`~ser program, when a bit (EC bi-t) indicating an extended control mode and a bit (T bit~ indicating an address translation are both 1l1", the VMDAT latch 5 is set at the moment of occurrence of status transition from the vir~ual machine (VM) state to the virtual machine monitor (VMM) sta-te ~hat is, at the moment of occurrence of an interruption in the VM state). Then, replacement of PS~ takes place to load a PWS of the virtual machine monitor (V~.M~ in each of the PSW
registers 1 and 2. When the program exception is detected, an interruption (INT) input of the state indicate latch 6 becomes "1'1 and thè state indicate latch 6 outputs ~ indicating the virtual machine monitor ~VMM~ state. The state indicate latch 6 i.s adapted to output "1" on the VM side and "0" on the VMM
side by a return (RTN~ instruction w~ich is issued for the tran-sfer of control to the virtual machine ~VM~ after completion of simulation by the virtual machine monitor (V~l. The virtual machine monitor ~V~ controls the bit 0 of the operand address register and, when an address translation is required, _ g _ sets the vaue of the bit 0 to "1". By this setting, the state indicate latch 6 indicates the virtual machin2 monitor (VM~l state ('~1" at the output of the VMM side), and w~en the bit 0 of the operand addres.s register is "1", the operand address corresponding thereto is accessed,by which the AND gate 8 or 9 corresponding to the accessed operand address outputs "1", deriving from the OR gate 10 a signal Tx indicating the execution ; of an address translation usiny address translation information during the VM program operation. In other words, the operand address (logical address) performs an address translation by accessing, throu~h u-.ili~ation of address translation informa-`~; tion of ~he virtual machine, a translation lookaside buEfer ` (TCB) or a translation -table used in the virtual machine.
: .
~ Fig. 5 shows an address translation circuit according , , , to the present invention. In Fig. 5, reference numeral 11 indicates a curren~ address translation control information register; 12 designates a preceding address translation control in~ormation reg.ister; 13 identifies a sesment table orlgin identification (STO-ID~ selector; 14 denotes an address translation processing unit with a DAT table; 15 represents a prefix processing unit; 16 show3 an absolute address re-gister; 17 refers to a comparator; 18 indicates a bus for transferring the output from an i~entification tID~ register 28, described later, to the comparator 17 and a translation lookaside buffer (TLB~ 26 described later; 19 designat~s a bus for a real address translated by the address translation porcessing unit 14; 20 identifies one part of a logical address :
whicil is to be translated ar;d is used for addressing the TLB
26; 21 denotes one part of the logical address which is ~o be translated and is compared with data of a logical address field read from the TLB 26; 22 represents a l~w-order bit of the logical address; 23 sho~s a ~us for transEerring a logical address field of an entry read from the TLB 28 to a comparator 29 described later; 24 refers to a bus for transferring an iden-tification field of the entry read from the TLB 26 to the comparator 17; 25 indicates a bus for txansferring a real address field of the entry read from the TLB 26 to a register 31 des-cribed later; 26 designates a translation lookaside buffer (TLB) which is formed by a memory packaged in a central proces-sing unit (CPU~ for achieviny a dynamlc address translation at high speed; 27 identifies a buEfer register for receiving the entry read from the TLB 26; 28 denotes an ID reyister; 29 represents a comparator, 30 shows an P~D circuit; 31 refers to a real address register; 32 indicates a gate; 33 desiynates a signal indicating a failure of the translation-by the TLB 26; 34 identifies a signal indicating success of the translation by the TLB 26; 35 denotes an address information select signal; 36 represents an inverter; 37 repres~nts the output from the inverter 36; 38 shows a bus for transferring the content of the register 11 to the register 12; 39 indicates a decoder;
40 designates a bus for address control information selected by a signal Tx 35; 41 iden~ifies .~ ~us for txansferring the output from the real address regi,ter 31 to the prefix proces-sing unit 15 and tEle TLB 26; 42 denotes a register for holding V~P
a prefix value oE a proyram under execution; 43 represents a register for holding the content shifted thereto from the register 42 in the status transition from the virtual machine (VM~ to the virtual machine monitor (VM~I~; 44 shows a bus for transferring a prefi~ vaLue s~lected by the siynal Tx 35 to the prefix processing unit 15; 45 refers to a gate;
46 indicates a control signal ~hich ~ecomes "1" when the address translation by the dymanic address translation table ~DAT table~ succeeds; and 47 designates a logical address register.
In Fig. 5, the current address translation control infor-mation register 11 stores the translation bit (T bit) and the EC
bit of the current PSW and dynamic address translation control information of control registers CRo and CRl. The preceding address translation control information register 12 loads the content of the current address translation control information re.gister 11 in the case of the Status transition from the virtual machine (VM) to the virtual machine monitor ~VMM~. The ID
s01ector 13 is composed of a segment takle origin stack circuit and a control circuit therefor a.ld responds to the address control information of the register 2 to select ID information corresponding thereto. The address translation processing unit 14 with the DAT table is a processing control unit which performs dynamic address translation using the DAT table on a main memory in the case where the address translation by the TLB 26 has ended in a failure. As the address translation information employed in this case, use is made of the information of the register 11 ~L3~2 or 12 selected by t~e siynal Tx 35. The real address converted at the moment of completion of -the address translation by the DAT ta~le is ~ritten in the TLB ~6 togetl~er with one part of the logical address on the ~us 21 and the ID on the bus 18.
The prefix processing ~it 15 performs prefi~ processing using the value of a prefix register selected by the signal Tx 35. The address translated by the prefix processing unit 15 is set in a high-order bit of the register 16, and a low-order bit of the logical address 22 is set in a low-order bit of the register 6. By an address in the register 6, the main memory is accessed.
The comparator 17 compares the ID information read from the ID selector 13 with information read from the TLB 26 and out-puts "l" in the case of coincidence. The comparator 29 com-pares one part of the loyical address to be translated and the logical address field of read TLB entry and outputs ' in the case of coincidence~
The arrangement of Fig. 5 differs from the conventional arrangement in that the register for :Loading the address translation control information is selected by the address information select signal Tx 35. That is, when the signal Tx is "l", informa~ion of the preceding address translation con~rol information register 12 and information of the register 43 for holding the preceding prefix value are selected. This enables the virtual machine monitor (VMM~ to perform address translation using address information of the vir-tual machine (VM~.
~L3~
When the signal Tx is "0", information of the current address translation control information register 11 and infor-mation of the register 42 for holding the current prefi~ value are selected. The addressing in the prior art corresponds to the case of the signal Tx ~eing "0".
As described above, ~hen the pro~ram of the virtual machine monitor (V~ uses an operand in the program of the virtual machine ~VM) executed i~nediately before, the address translation corresponding to the operand can be achieved using the translation lookaside buffer.
Fig. 6 shows dynamic address translation control infor-mation loaded in the control registers CRo and CRl of the current address translation control information register 11. As depicted in Fig. 6, the control register CRl loads the ST length in bits O to 7 and the ST origin address in bi-t 8 to 25, and the control register CRo loads the page size (PS) in bits 8 and 9 and the segment size (SS) in bits 11 and 12.
No description will be given o,the control for ~a~ the dynamic address translation based on the information loaded in the control registers, since it i3 set forth in detail in "IBM System/370 Principles of Operation, G~ 22-700, File ~o.
S/370-Ol'i .
Fig. 7 shows the content of the prefix register 42. As depicted in Fig. 7, the prefix ~alue of program is ~eld in ~its 8 to 1~.
Fig~ 8 illustrates an address control circuit according to a second en~odiment of this invention. In Fig~ 8, the same reference numerals as -those in Fig. 4 indicate the same parts;
and reference numeral 50 ~e~i~Ra~e an instruction register, and 51 and 52 identify comparators. In this e~bodiment, it is determined whether to perfonm real address control semi-Eixedly or address translation control by the VMDAT latch 5 in response to the register number indicatea in a register indicate field of an instruction in the virtual machine monitor (VMM) state.
Let it be assumed, for example, that general purpose reyisters 0 to 3 are subjected to the address control of the current program status word and that yeneral purpose registers
The virtual machine has such advantages as mentioned previously, but in the case of running a program under the virtual machine, perEormance - 10 degradation is caused to some extend due to an overhead peculiar to the virtual machine, as compared with the case of running the same program under the operating system oE an ordinary computer heretofore employed. The overhead can be divided into direct and indirect ones as follows:
(1) Direct overhead This occurs mainly in the course of processing by software of the virtual machine monitor and this type of overhead is as follows:
(a) Overhead by simulation of privileged instruction.
As described above, each user program including the operating ~- system used therefore is assigned the 7'problem mode", privileged instruct-~ 20 ions issued by the operating system are all simulated by the virtual machine : monitor.
(b) Overhead for switching each user program.
(c) Overhead for supporting the virtual memory function of the operating system (d) Overhead for translation of channel programs.
, `::
`.~'~.:
A channel program for starting an input/output device by the operating system is a logical address to a host computer; therefore, the virtual machine monitor translates the logical address to a real address of the host computer.
~ . ~
(e) Overhead Eor supporting in~erruptionS
In the virtual machine, each interruption is indexed by t~e virtual machine monitor, so that if this interruption is required, it must be reflected in t~e operating system; this processing is carried out by the virtual machine monitor.
(f~ Overhead for supporting console function The virtual machine monitor supports the console function, including the debug function.
(2) Indirect overhead `
In the existing operating system, various algorithms are incorporated in the system of allocation and management of the system resource so as to enhance its availability, but when run under the virtual machine system, these algorithms may in some cases produce a contrary result~
Next, the prior art will be described in connection with the simulation of the privileged instruction Since each user program, including the operating system used therefor, i5 assigned the "pro~lem mode" as described above, the prlvileged instructions used by the operating system are all ~detected as "privileged-operation exceptions" and indexed in the virtual machine monitor (VM~1~. Then, the vir-tual machine monitor ~VM~1) simulates the privileged instruction in the following manner.
When a program interrupt of the "privileged-operation exception"
is detected, an old program status word (PSW~, an interruption code, ~tc. are loaded in a prefix area. After saving a general purpose register in a working area of the virtual machine monitor tVMM~, the virtual machine monitor (VM~I) reads from a virtual machine (VM) area an operation code of an instruction having issued the privileged-operation exception from the old program status word and, after an operand address computation corresponding to the operation code from the contents of a field of the instruction and the saved general purpose register, transfers control to the instnlction processing routine corresponding to the operation code.
In the instruction processing routine, a required operand is read from or written in, or read from and written in the virtual machine (VM) area.
The processing of some steps by the virtual machina moni-tor (VMM) is accompanied by read/write of an operand in the program area of the virtual machine (VM). The program of the virtual machine monitor (VMM) operates in the real address mode for supporting a virtual memory of the operating system. Accordingly, in the processing of these steps, when the program area of the virtual machine (VM) is accessed, the logical address of the operand is translated into a real address using an instruction explicitIy instructing an address translation (a load real address instruction) and then the main memory is accessed with the real address thus obtained. Since the load real address instruction usually does not use a translation looka-side buffer (TLB) for loading a pair of logical and real addresses, a segment table and a page table on the main memory are always accessed for dynamic address translation (DAT), resulting in an appreciable amount of ove-rhead.
Especially in the case of accessing a plurality of operands of different locations by one instruction, the overhead necessary '~
~L34~6~
for the d~lamic address transla~ion tDAT) becomes remarkable.
SUMMARY OF TH~ INVENTION
This invention has for its object to reduce the 'roverhead due to address translation during the simulation of a pri~ileged instruction".
T~e above objective can be achieved by providing an address control system for software simulation in a data processor which has a translation device for coordinating an address on a program with a main memory address and a function of simulating the exe-cution of an instruction of a program to be simulated by the execution of one or more instructions of a simulator program and which is provided with first means for holding information for dlscriminating the operating state of the simulator program and the operating state of the program to be simulated, second means for holding control information for coordinating the address on the program to be simulated with the address on the main program in the case o simulating the program to be simulated by the simulator program, third means for holding control information for coordinating the addres~ on the simulator program with the address on the main memory, and fourth means for indicating the selection of either the second or third ~eans is selected during the operation of the simulator program, ~.Therein the address translation is controlled by the first, second, third and fourth means~
~46~
BRIEF DESCBI_TI0N OF THE _RAI~INGS
Fig. 1 is a diagram showing the concept of a general machine system heretofore employed;
F~g. 2 is a diagram showing the concept of a virtual mach:Lne system;
Fig. 3 is a flow chart showing processing of a virtual machine monitor (VMM);
Fig. 4 is a block diagram illustrating the construction of an address control circuit according to a first embodiment oE this invention;
Fig. 5 is a block diagram illustrating the construction of an address translation circuit according to this invention;
Fig. 6, on the first sheet of drawings, is a diagram showing dynamic address translation (DAT) control information loaded in a control register;
Fig. 7, on the first sheet oE drawings, is a diagram showing the content of a prefix register;
~; Fig. ~ is a block diagram illustrating the construction of an ` address control circuit according to a second embodiment of this invention;
and Fig. 9 is a diagram showing an example of the content of a register during the execution of a move character instruction.
DESCRIPTION OF THE PP~EFERRED EMBODrMENTS
Fig. 1 schematically shows the concept of an ordinary computer system heretofore emp]oyed; and Fig. 2 schematically shows the concep~ of the virtual machine system. In Figs. 1 and 2, the real machine means compu-ter hardware In Fig. 2, the broken line blocks each correspond ~o the convention-al ordinary computer system and are each referred to as a virtual machine ~....
,. ..;
lg~
(VM). Under the virtual machine system, a plurality of Yirtual machines can be run simultaneously.
Fig. 3 shows a process char~ of the virtual machine monitor (VMM).
In the flowchart of Fig. 3, processing of steps 1, 2 and 3 is accompanied by read/write of an operand in the program area oE the virtual machine (VM).
The program of the virtual machine monitor (~M) operates in the real address mode for supporting a virtual memory of the operating system.
Accordingly, in the processing of the steps 1, 2 and 3, when the program area of the virtual machine ~VM) is accessed, the logical address of the operand is translated into a real address using an instruction explicitly instructing an address translation (a load real address instruction) and then the main memory is accessed with the real address thus obtained. Since the load real address instruction usually does not use a translation looka-side buffer (TLB~ for loading a pair oE logical and real addresses, a segment table and a page table on the main memory are always accessed for dynamic address translation (DAT), resulting in an appreciable amount of overhead.
Fig. 4 illustrates an address control circuit produced in accordance ; with a first embodiment of the present invention. In Fig. 4, reference numeral 1 indicates a first word of a program status word (PS~) register;
2 designates a second word of the PSW register; 3 :
:;
-8a-idcntifies an operand one-address register; 4 denotes an operand.
two-address register; 5 represents a virtual machine dynamic address translation (VMDAT~ latch, 6 shows a status indicate latch; 7 to 9 refer to AND gates; and 10 indicates an OR gate.
Upon detection of a proyram exception during O~ ~ O~ ~c.
user program (including an operating system~, an interruption occurs and, according to address tra.nslation control informa-tion in PSW controlling the dynamic address translation (DAT~
at that time, the VMDAT latch S is set. In concrete terms, duri.ng the operat.ion of-each`~ser program, when a bit (EC bi-t) indicating an extended control mode and a bit (T bit~ indicating an address translation are both 1l1", the VMDAT latch 5 is set at the moment of occurrence of status transition from the vir~ual machine (VM) state to the virtual machine monitor (VMM) sta-te ~hat is, at the moment of occurrence of an interruption in the VM state). Then, replacement of PS~ takes place to load a PWS of the virtual machine monitor (V~.M~ in each of the PSW
registers 1 and 2. When the program exception is detected, an interruption (INT) input of the state indicate latch 6 becomes "1'1 and thè state indicate latch 6 outputs ~ indicating the virtual machine monitor ~VMM~ state. The state indicate latch 6 i.s adapted to output "1" on the VM side and "0" on the VMM
side by a return (RTN~ instruction w~ich is issued for the tran-sfer of control to the virtual machine ~VM~ after completion of simulation by the virtual machine monitor (V~l. The virtual machine monitor ~V~ controls the bit 0 of the operand address register and, when an address translation is required, _ g _ sets the vaue of the bit 0 to "1". By this setting, the state indicate latch 6 indicates the virtual machin2 monitor (VM~l state ('~1" at the output of the VMM side), and w~en the bit 0 of the operand addres.s register is "1", the operand address corresponding thereto is accessed,by which the AND gate 8 or 9 corresponding to the accessed operand address outputs "1", deriving from the OR gate 10 a signal Tx indicating the execution ; of an address translation usiny address translation information during the VM program operation. In other words, the operand address (logical address) performs an address translation by accessing, throu~h u-.ili~ation of address translation informa-`~; tion of ~he virtual machine, a translation lookaside buEfer ` (TCB) or a translation -table used in the virtual machine.
: .
~ Fig. 5 shows an address translation circuit according , , , to the present invention. In Fig. 5, reference numeral 11 indicates a curren~ address translation control information register; 12 designates a preceding address translation control in~ormation reg.ister; 13 identifies a sesment table orlgin identification (STO-ID~ selector; 14 denotes an address translation processing unit with a DAT table; 15 represents a prefix processing unit; 16 show3 an absolute address re-gister; 17 refers to a comparator; 18 indicates a bus for transferring the output from an i~entification tID~ register 28, described later, to the comparator 17 and a translation lookaside buffer (TLB~ 26 described later; 19 designat~s a bus for a real address translated by the address translation porcessing unit 14; 20 identifies one part of a logical address :
whicil is to be translated ar;d is used for addressing the TLB
26; 21 denotes one part of the logical address which is ~o be translated and is compared with data of a logical address field read from the TLB 26; 22 represents a l~w-order bit of the logical address; 23 sho~s a ~us for transEerring a logical address field of an entry read from the TLB 28 to a comparator 29 described later; 24 refers to a bus for transferring an iden-tification field of the entry read from the TLB 26 to the comparator 17; 25 indicates a bus for txansferring a real address field of the entry read from the TLB 26 to a register 31 des-cribed later; 26 designates a translation lookaside buffer (TLB) which is formed by a memory packaged in a central proces-sing unit (CPU~ for achieviny a dynamlc address translation at high speed; 27 identifies a buEfer register for receiving the entry read from the TLB 26; 28 denotes an ID reyister; 29 represents a comparator, 30 shows an P~D circuit; 31 refers to a real address register; 32 indicates a gate; 33 desiynates a signal indicating a failure of the translation-by the TLB 26; 34 identifies a signal indicating success of the translation by the TLB 26; 35 denotes an address information select signal; 36 represents an inverter; 37 repres~nts the output from the inverter 36; 38 shows a bus for transferring the content of the register 11 to the register 12; 39 indicates a decoder;
40 designates a bus for address control information selected by a signal Tx 35; 41 iden~ifies .~ ~us for txansferring the output from the real address regi,ter 31 to the prefix proces-sing unit 15 and tEle TLB 26; 42 denotes a register for holding V~P
a prefix value oE a proyram under execution; 43 represents a register for holding the content shifted thereto from the register 42 in the status transition from the virtual machine (VM~ to the virtual machine monitor (VM~I~; 44 shows a bus for transferring a prefi~ vaLue s~lected by the siynal Tx 35 to the prefix processing unit 15; 45 refers to a gate;
46 indicates a control signal ~hich ~ecomes "1" when the address translation by the dymanic address translation table ~DAT table~ succeeds; and 47 designates a logical address register.
In Fig. 5, the current address translation control infor-mation register 11 stores the translation bit (T bit) and the EC
bit of the current PSW and dynamic address translation control information of control registers CRo and CRl. The preceding address translation control information register 12 loads the content of the current address translation control information re.gister 11 in the case of the Status transition from the virtual machine (VM) to the virtual machine monitor ~VMM~. The ID
s01ector 13 is composed of a segment takle origin stack circuit and a control circuit therefor a.ld responds to the address control information of the register 2 to select ID information corresponding thereto. The address translation processing unit 14 with the DAT table is a processing control unit which performs dynamic address translation using the DAT table on a main memory in the case where the address translation by the TLB 26 has ended in a failure. As the address translation information employed in this case, use is made of the information of the register 11 ~L3~2 or 12 selected by t~e siynal Tx 35. The real address converted at the moment of completion of -the address translation by the DAT ta~le is ~ritten in the TLB ~6 togetl~er with one part of the logical address on the ~us 21 and the ID on the bus 18.
The prefix processing ~it 15 performs prefi~ processing using the value of a prefix register selected by the signal Tx 35. The address translated by the prefix processing unit 15 is set in a high-order bit of the register 16, and a low-order bit of the logical address 22 is set in a low-order bit of the register 6. By an address in the register 6, the main memory is accessed.
The comparator 17 compares the ID information read from the ID selector 13 with information read from the TLB 26 and out-puts "l" in the case of coincidence. The comparator 29 com-pares one part of the loyical address to be translated and the logical address field of read TLB entry and outputs ' in the case of coincidence~
The arrangement of Fig. 5 differs from the conventional arrangement in that the register for :Loading the address translation control information is selected by the address information select signal Tx 35. That is, when the signal Tx is "l", informa~ion of the preceding address translation con~rol information register 12 and information of the register 43 for holding the preceding prefix value are selected. This enables the virtual machine monitor (VMM~ to perform address translation using address information of the vir-tual machine (VM~.
~L3~
When the signal Tx is "0", information of the current address translation control information register 11 and infor-mation of the register 42 for holding the current prefi~ value are selected. The addressing in the prior art corresponds to the case of the signal Tx ~eing "0".
As described above, ~hen the pro~ram of the virtual machine monitor (V~ uses an operand in the program of the virtual machine ~VM) executed i~nediately before, the address translation corresponding to the operand can be achieved using the translation lookaside buffer.
Fig. 6 shows dynamic address translation control infor-mation loaded in the control registers CRo and CRl of the current address translation control information register 11. As depicted in Fig. 6, the control register CRl loads the ST length in bits O to 7 and the ST origin address in bi-t 8 to 25, and the control register CRo loads the page size (PS) in bits 8 and 9 and the segment size (SS) in bits 11 and 12.
No description will be given o,the control for ~a~ the dynamic address translation based on the information loaded in the control registers, since it i3 set forth in detail in "IBM System/370 Principles of Operation, G~ 22-700, File ~o.
S/370-Ol'i .
Fig. 7 shows the content of the prefix register 42. As depicted in Fig. 7, the prefix ~alue of program is ~eld in ~its 8 to 1~.
Fig~ 8 illustrates an address control circuit according to a second en~odiment of this invention. In Fig~ 8, the same reference numerals as -those in Fig. 4 indicate the same parts;
and reference numeral 50 ~e~i~Ra~e an instruction register, and 51 and 52 identify comparators. In this e~bodiment, it is determined whether to perfonm real address control semi-Eixedly or address translation control by the VMDAT latch 5 in response to the register number indicatea in a register indicate field of an instruction in the virtual machine monitor (VMM) state.
Let it be assumed, for example, that general purpose reyisters 0 to 3 are subjected to the address control of the current program status word and that yeneral purpose registers
4 to lS are subjected to the address translation control by the VMDAT latch.
In Fig. ~, it is checked by the comparator 51 whether or not the register number indicated by a part Bl of the instruc-tion register 50 is included in general purpose register numbers 4 to 15; and it is checked by the comparator 52 whether or not the register number indicated by a part B2 of the instruction register 50 is included in the general purpose register numbers 4 to ~5.
When the state indicate latch 6 indicates the virtuàl machine monitor (VMM) state ("1" at the output of the VMM
side) and the operand register number is included in the general purpose register numbers 4 to 15, the corre-sponding operand address is accessed~by which the output from the corresponding AND yate 8 or 9 becomes ~ deriving the address information select signal Tx from ~he OR gate 10~
The subsequent operation is the same as in the Eirst embodiment.
~13~3~
Fig. 9 shows an example of -the register content during the execution of the move character (MVC) instruction. The MVC instruction has the unction hy which data of an area on a main memory corresponding to the byte number indicated in a part V using, as an origin address, the value that the value of the part D2 is added to the value of the general purpose register indicated by the part B2 (ope~and 2~, is transEerred to an area oE the main memory using, as an origin address, -the value that the value of the part Dl is added to the value of the general pur-pose register indicated by the part Bl (operand l). Ir Fig. 9, the value of the part Bl is "l" and is not included in the general purpose register numbers 4 to 15, so that the output from the comparator 51 becomes "0" and the signallalso becomes "0", resulting in the operand l being subjected to the address translation control by the virtual machine monitor (VMM~.
Since the value of the part B2 is "4" and included in the general purpose register numbers 4 to 15, the second operand is subjected to the immediately preceding address translation control by the virtual machine (VM); when the value of the VMDAT latch is "0", a real address "00002567" is provided and when the value of the VMDAT latch is "1", a logical address "00002567" is provided. In this second embodiment, the cor-ralation between the register number and the address transla-tion control can be changed arbitrarily according to processing.
As has been described in ~he foregoing, according to this invention, when a simulator program simulates an instruction of a program to be simulated, the ~L3~
address translation of an operand ~ddress of the proyr~m to be simula-ted can be achieved using a translation lookaside buffer, so that the overhead for the address translation in the execution oE the simulator program can be greatly reduced.
Although the present inven~ion has been described above in con-nection wit~ the case where the execution of a privileged inst-ruction in the virtual machine is simulated by software called the virtual machine monitor (VMM~ program, it is evident -that the invention can easily be applied to the cases of simulating the execution of an instruction not only by the virtual machine but also by software.
It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.
In Fig. ~, it is checked by the comparator 51 whether or not the register number indicated by a part Bl of the instruc-tion register 50 is included in general purpose register numbers 4 to 15; and it is checked by the comparator 52 whether or not the register number indicated by a part B2 of the instruction register 50 is included in the general purpose register numbers 4 to ~5.
When the state indicate latch 6 indicates the virtuàl machine monitor (VMM) state ("1" at the output of the VMM
side) and the operand register number is included in the general purpose register numbers 4 to 15, the corre-sponding operand address is accessed~by which the output from the corresponding AND yate 8 or 9 becomes ~ deriving the address information select signal Tx from ~he OR gate 10~
The subsequent operation is the same as in the Eirst embodiment.
~13~3~
Fig. 9 shows an example of -the register content during the execution of the move character (MVC) instruction. The MVC instruction has the unction hy which data of an area on a main memory corresponding to the byte number indicated in a part V using, as an origin address, the value that the value of the part D2 is added to the value of the general purpose register indicated by the part B2 (ope~and 2~, is transEerred to an area oE the main memory using, as an origin address, -the value that the value of the part Dl is added to the value of the general pur-pose register indicated by the part Bl (operand l). Ir Fig. 9, the value of the part Bl is "l" and is not included in the general purpose register numbers 4 to 15, so that the output from the comparator 51 becomes "0" and the signallalso becomes "0", resulting in the operand l being subjected to the address translation control by the virtual machine monitor (VMM~.
Since the value of the part B2 is "4" and included in the general purpose register numbers 4 to 15, the second operand is subjected to the immediately preceding address translation control by the virtual machine (VM); when the value of the VMDAT latch is "0", a real address "00002567" is provided and when the value of the VMDAT latch is "1", a logical address "00002567" is provided. In this second embodiment, the cor-ralation between the register number and the address transla-tion control can be changed arbitrarily according to processing.
As has been described in ~he foregoing, according to this invention, when a simulator program simulates an instruction of a program to be simulated, the ~L3~
address translation of an operand ~ddress of the proyr~m to be simula-ted can be achieved using a translation lookaside buffer, so that the overhead for the address translation in the execution oE the simulator program can be greatly reduced.
Although the present inven~ion has been described above in con-nection wit~ the case where the execution of a privileged inst-ruction in the virtual machine is simulated by software called the virtual machine monitor (VMM~ program, it is evident -that the invention can easily be applied to the cases of simulating the execution of an instruction not only by the virtual machine but also by software.
It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of this invention.
Claims (4)
1. An address control system for software simulation in a data processor which has a translation device for coordinating an address on a program with a main memory address and a function of simulating the execution of an instruction of a program to be simulated by the execution of one or more instructions of a simulator program, said system comprising:
first means for holding information for discriminating the operating state of the simulator program and the operating state of the program to be simulated;
second means for holding control information for coordinat-ing the address on the program to be simulated with the address on the main program in the case of simulating the program to be simulated by the simulator program;
third means for holding control information for coordinating the address on the simulator program with the address on the main memory; and fourth means for indicating the selection of either the second or third means during the operation of the simulator program;
wherein the address translation is controlled by the first, second, third and fourth means.
first means for holding information for discriminating the operating state of the simulator program and the operating state of the program to be simulated;
second means for holding control information for coordinat-ing the address on the program to be simulated with the address on the main program in the case of simulating the program to be simulated by the simulator program;
third means for holding control information for coordinating the address on the simulator program with the address on the main memory; and fourth means for indicating the selection of either the second or third means during the operation of the simulator program;
wherein the address translation is controlled by the first, second, third and fourth means.
2. An address control system according to claim 1, wherein a general purpose register number for operand address computation is used as the fourth means.
3. An address control system according to claim 1, wherein information of one part of the operand address is used as the fourth means.
4. An address control system according to claim 2 or 3, wherein in the case where the translation device for coordinating the address on the program with the main memory address is established by an address translation device of a virtual memory system, when the first means indicates the operating state of the simulator program, the second means indicates an address translation mode and the fourth means indicates an address translation, the address translation is achieved using the address control information held in the second means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP148834/1978 | 1978-12-01 | ||
| JP14883478A JPS5576447A (en) | 1978-12-01 | 1978-12-01 | Address control system for software simulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1134052A true CA1134052A (en) | 1982-10-19 |
Family
ID=15461768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA341,030A Expired CA1134052A (en) | 1978-12-01 | 1979-11-30 | Address control system for software simulation |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4347565A (en) |
| JP (1) | JPS5576447A (en) |
| AU (1) | AU530696B2 (en) |
| CA (1) | CA1134052A (en) |
| DE (1) | DE2948285C2 (en) |
| FR (1) | FR2443100A1 (en) |
| GB (1) | GB2043309B (en) |
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| US3544969A (en) * | 1967-11-27 | 1970-12-01 | Standard Computer Corp | Language independent computer |
| US3983541A (en) * | 1969-05-19 | 1976-09-28 | Burroughs Corporation | Polymorphic programmable units employing plural levels of phased sub-instruction sets |
| US3665487A (en) * | 1969-06-05 | 1972-05-23 | Honeywell Inf Systems | Storage structure for management control subsystem in multiprogrammed data processing system |
| NL7407274A (en) * | 1973-05-31 | 1974-12-03 | ||
| US3955180A (en) * | 1974-01-02 | 1976-05-04 | Honeywell Information Systems Inc. | Table driven emulation system |
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- 1978-12-01 JP JP14883478A patent/JPS5576447A/en active Granted
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1979
- 1979-11-29 GB GB7941267A patent/GB2043309B/en not_active Expired
- 1979-11-30 CA CA341,030A patent/CA1134052A/en not_active Expired
- 1979-11-30 DE DE2948285A patent/DE2948285C2/en not_active Expired
- 1979-11-30 FR FR7929516A patent/FR2443100A1/en active Granted
- 1979-11-30 AU AU53360/79A patent/AU530696B2/en not_active Ceased
- 1979-11-30 US US06/098,989 patent/US4347565A/en not_active Expired - Lifetime
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|---|---|
| DE2948285A1 (en) | 1980-06-04 |
| US4347565A (en) | 1982-08-31 |
| AU530696B2 (en) | 1983-07-28 |
| DE2948285C2 (en) | 1984-07-12 |
| JPS5725860B2 (en) | 1982-06-01 |
| FR2443100B1 (en) | 1983-08-19 |
| JPS5576447A (en) | 1980-06-09 |
| AU5336079A (en) | 1980-06-05 |
| GB2043309B (en) | 1983-05-05 |
| GB2043309A (en) | 1980-10-01 |
| FR2443100A1 (en) | 1980-06-27 |
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