CA1092716A - Key register controlled accessing system - Google Patents

Key register controlled accessing system

Info

Publication number
CA1092716A
CA1092716A CA275,572A CA275572A CA1092716A CA 1092716 A CA1092716 A CA 1092716A CA 275572 A CA275572 A CA 275572A CA 1092716 A CA1092716 A CA 1092716A
Authority
CA
Canada
Prior art keywords
access
storage
key
address
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA275,572A
Other languages
French (fr)
Inventor
Richard E. Birney
Michael I. Davis
Robert A. Hood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1092716A publication Critical patent/CA1092716A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14Protection against unauthorised use of memory or access to memory
    • G06F12/1458Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615Address space extension
    • G06F12/0623Address space extension for memory modules

Abstract

KEY REGISTER CONTROLLED ACCESSING SYSTEM
ABSTRACT
Active address key (AAK) select circuits relate plural key register sections to respective machine-identifiable access types. On each received storage access request, the AAK select circuits outgate an AAK from the key register section corresponding to the machine-identi-fied type for the storage access request. One or more key register sec-tions are provided in an address key register (AKR) in a processor.
Other key register sections are provided with I/O subchannels which connect to the channels of a processor. Priority circuits control the sequence of storage access requests received by the AAK select circuits.
Different machine-identifiable access types which are sensed in the machine include the instruction fetch, source operand fetch, sink operand store/fetch, and I/O data store/fetch.

Description

~0~9~716
2 I. INTRODUCTION
3 This invention relates generally to access-type
4 control over the addressability in the main memory of a data processing system.
6 In particular, the invention relate3 to a key-register 7 controlled addressing system, in which different key-register 8 sections correspond to different addressabilities available 9 in the system, in which each addressability can access a storige area in the main memory with up to a full range of 11 programmable addresses. Furthermore, the invention relates 12 the different addressabilities to different types of machine-13 identified storage accesses. Any key loaded into a key-14 register section, when selected, becomes the high-order part of a logical machine address for all storage accesses of the 16 related machine-identified access type. This high-order part 17 accordingly defines a part of main memory in which all 18 accesses of the related machine-identified type are restricted;
19 therefore, this part of storage i8 automatically protected against different type~ of storage accesses using a different 21 key. These access restricted parts of main memory may be 22 fixed or relocatable, and may be contiguously or non-uontiguously 23 physically addressable.

~R

109~'71~;

1 I.A. RELATED UNITED STATES PATENTS
The subject application is related to other United States patents having different joint inventorships and owned by the same assignee. These other patents are:
1. United States Patent No. 4,042,913, issued August 16, 1977, to R.E. Birney et al, entitled "Address Key Register Load/Store Instruction System".
2. United States Patent No. 4,037,215, issued July 19, 1977, to R.E. Birney et al, entitled "Key Controlled Address Relocation Translation System".
3. United States Patent No. 4,042,911, issued August 16, 1977, to D.G. Bourke et al, entitled "Outer and Asyn-chronous Storage Extension System".
4. United States Patent No. 4,050,060, issued September 20, 1977, to R.E. Birney et al, entitled "Equated Operand Address Space Control System".
5. United States Patent No. 4,038,645, issued July 26, 1977, to R.E. Birney et al, entitled "Non-translatable Stor-age Protection Control System".
6. United States Patent No. 4,035,779, issued July 12, 1977, to R.E. Birney et al, entitled "Supervisor Address Key Control System".
7. United States Patent No. 4,037,207, issued July 19, 1977, to R.E. Birney et al, entitled "System for Con-trolling Address Keys Under Interrupt Conditions".
8. United States Patent No. 4,047,161, issued September 6, 1977, to M.I. Davis, entitled "Task Management Appara-tus".
9. United States Patent No. 4,041,462, issued August 9, 1977, to M.I. Davis et al, entitled "Data Processing System Featuring Subroutine Linkage Operations Using Hardware Controlled Stacks.

1 10. United States Patent ~o. 4,038,641, issued July 26, 1977, to M.A. Bouknecht, et al, entitled "Common Polling Logic for Input/Output Interrupt or Cycle Steal Data Transfer Requests".
11. United States Patent No. 4,038,642, issued July 26, 1977, to M.A. Bouknecht et al, entitled "Input/Output Interface Logic for Concurrent Operations".
12. United States Patent No. 4,053,950, issued October 11, 1977, to ~.G. Bourke et al entitled "Residual Status Reporting During Chained Cycle Steal Input/Output Operations".
13. United States Patent No. 4,050,094, issued September 20, 1977, to D.G. Bourke, entitled "Translator Look-ahead Con~rols.

:

~ BC9-76-006 -2a-..~ .

10927~6 1 I.B. PRIOR ART

Block a~signable protect keys have long been used in commercially available data processing systems, e.g.
IBM*S/360 and S/370 machines. However, these prior protect keys do not enable independent main store addressing for concurrent program~. Rather, these prior keys divide up a single addressing range provided for the system's main store among concurrent programs by assigning each program a part of the addressing range 19 The assigned key in its program status word (PSW), caused all accesses by the program to be in that part of main ~tore addressing range identified with the same key. Furthermore, prior protect key controls did not provide different keys for different types of accesses within a single program.
The integrity of system operations using this prior key protection technique resolves itself into the integrity of the key assignment process. For concurrently loaded programs, any uncoordinated dupli-*Registered Trade Mark of International Business MachinesCorporation .~

109'h',7~6 1 cation in key assignments among the PSW's, or in2 the assignments of keys among the blocks, could lead to 3 failures in system operation by allowing an access 4 intended for one program to occur in an address sub-range being used by another program, because each 6 program is permitted to be written with a full range 7 of addressability which could overlap the sub-range 8 addressability being used by other concurrently loaded g programs.
U.S.A. patent 3,828,327 (Berglund et al) describes 11 a prior storage control technique, which does not use 12 address keys. It uses the different system modes, e.g.
13 processor interrupt modes, I/O mode, etc., to control 14 whether or not address translation is to be used. Also, a high-order bit, which is not part of a programmable 16 address, is controlled by an I/O operation interrupt 17 when it is about to exceed its non-translatable 18 programmable memory space, so that the I/O accesses 19 can occur in the alternate memory space.
Another prior storage control technique, which 21 does not use address keys, is described in U.S.A.
22 patent 3,854,126. It uses different processor modes, 23 i. e. supervisor, user, kernal, to select a corresponding 24 set of registers, and each set has a pair of subsets, i. e. a data subset and an instruction subset. A
26 physically contiguous plurality of 64 byte blocks of 27 physical memory are assigned to the content of each 28 page address register in a set to define a variable-29 length page. That is, each processor mode has a dedicated pair of subsets; and in a mode-selected pair, 109'~7:~6 1 one subset assigns one part of memory for instructions, 2 and the o~her subset assi~ns another part of memory 3 for data. ~lhe high-order part of a programmed logical 4 address identifies a required register in the selected set, and the content of the selected register identifies 6 an assigned set of physically contiguous blocks which 7 comprise a variable-length page. An intermediate part 8 of the logical address provide a block displacement 9 address within the physically contiguous blocks comprising the page to select a particular hlock which 11 should contain the requested address. The low-order 12 part of the logical address provides a word displacement 13 within the selected block to access the addressed 14 information.
II SUMMARY OF THE INVENTION
16 The subject invention provides a plurality of key ~7 register sections for containing address keys. Some 18 of these register sections are provided in an address 19 key register (AKR) in a processor. Other key register sections are provided with respective I/O subchannels 21 which connect with the channels of the processor.
22 The invention relates the key register sections 23 to machine-identified types of storage accesses 24 available in the main memory. Different machine-identified access types include, for example, the 26 instruction fetch, source operand fetch, a sink operand 27 store, and a sink operand fetch. Since the last two types 28 are generally more efficiently accessed in the same 109'~716 1 memory area, they may be combined into a single sink 2 operand store/fetch access type. These access types may 3 be sensed by conventional circuits found in a processor.
4 The invention provides circuits which relate the key register sections to the circuits that sense the 6 different machlne-identified access types. One register 7 section has its assigned key outgated by a signal from 8 the CPU instruction fetch controls. Other register 9 sections have their assigned keys selectively outgated by signals from the instruction execution circuits 11 which sense different types of operand access requests, 12 such as a source operand fetch request signal, a sink 13 operand store request signal, a sink operand fetch 14 request signal, etc. Still other key register sections have their keys selectively outgated by I/O storage 16 access request signals from the subchannel commands.
17 Furthermore, events which interrupt normal programmed 18 operations of either a processor, channel or subchannel, 1~ can also be enabled by this invention to have respectively separate addressability, whenever required.
21 For example, the storage or retrieval of events, infor-22 mation or programs required hy the events, or their 23 results, which are related to a processor or subchannel 24 operation, can be provided a unique area in main memory 25` which cannot be disturbed by other system operations.
26 Processor events are defined to generate internal 27 interrupts. Subchannel events are defined to generate 28 external interrupts. Thus, interrupt handling program 29 routines can each be stored and fetched from a speclal address-protected area of memory.

109~716 1 This invention comprehends providing in a machine 2 the availability of special addressability for every 3 type of ~torage ~ccess which may be architected for 4 a machine. ~t therefore comprehends, whenever required, also providing special addressability for indirectly 6 addressed operands, and permits them to be likewise 7 subgrouped according to their source and sink relation-8 ships. Furthermore, the invention can enable a system 9 to provide separate addressability within its main memory subsystem among its different processors and 11 among its different channels and subchannels.
12 The invention can provide the hardware facilities 13 for providing all of the previously described separate 14 addressability in a data processing system. Yet, when ; 15 these hardware facilities are provided in a system, 16 this invention leaves the final choice of defining the 17 8eparate addressability to the system users. It is 18 very important to understand that this invention does 19 not force separate addressability upon the different storage access types. That is, the user is left 21 with the final choice of assigning specific key values 22 for respective access types when this invention is i 23 installed in a system. Hence, the key values and 24 their block assignments are left to the later time when the specific applications are to be run on a 26 system, at which time each user and the system can 27 decide how the addressability should be divided among 28 the access types being used, or whether some or all 109~716 1 of the access types should have the same addressability 2 by assigning them one or more common key values. The 3 addressability provided by this invention, can 4 readily be changed, wherever required, from one program to the next. ~f course, concurrently executing 6 programs will generally be given separate addressability 7 by being given separate instruction fetch key values 8 to enhance the integrity of their executions. Also, 9 data base components in main store often will also be given separate addressability to maintain their 11 integrity by being assigned a source operand key 12 value.
13 The subject invention supports a plurality of 14 address keys which can address assigned portions of main memory, in which each key-addressable memory 16 portion can have non-conflicting full program 17 addressability. (Full program addressability is 18 defined as the range of program addresses available 19 from the number of bit positions in a program-specified address.) The different key-addressable memory 21 portions can be located anywhere in the main memory, 22 and each key addressable portion can be aligned to a 23 physical area totally separate from all other key-24 addressable portions/ or partially overlapped with one or more other key-addressable portions. The size 26 of the main memory can be many times any single 27 programs addressability. When assigned to separate 28 physical areas, the key addressing is non-conflicting.

1 When assigned to overlapped physical areas, the information 2 is shared between the address keys having the overlapped 3 assignment, and it is non-conflicting if it is read-only 4 accessible.
S It is therefore a primary object of this invention 6 to provide an addressability control subsystem for data 7 processing systems which enables unique separation of 8 addressability among different data processing functions 9 which may concurrently use a common physical memory.
It is another object of this invention to provide 11 separate addressability among different data processing 12 functions which may concurrently use a common physical 13 memory.
14 It is another object of this invention to provide an addressability control subsystem which can be used to 16 provide total physical address-separation among user 17 functions, whether program or data, without requiring 18 the user to exercise control over the addressing range 19 used when developing programs for the system.
It is a further object of this invention to provide 21 an addressability control subsystem which permits fast 22 generation of memory addresses by not interposing time 23 consuming operations into the address generation process.
24 The key-selection operation provided by this invention to obtain address separation is over-lappable with conventional 26 address generation operations also required in the system.
27 Therefore, the addition of this invention to a data pro-28 cessing system does not increase the memory access time over 29 what the access time should be without this invention when the size of a main memory is significantly increased.

~09~716 1 These and other objects, features and advantages of the invention may be more fully understood and appreciated by considering the following detailed description in association with the accompanying drawings.
III. BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE lA-l generally illustrates an access-type regis-ter concept, in which an active address key (AAK) is selected by a storage request for a machine-identified storage access type for controlling the physical accessing of a main mem-ory.
FIGURE lA-2 generally illustrates an address key trans-lator concept, in which a main memory physical address is generated from a logical input address comprised of a machine-generated AAK and a program apparent address.
FIGURE lB illustrates diagramatically a plurality of machine identifiable storage access types which can be implemented in the invention.
FIGURE lC is a physical representation of a data pro-cessing system containing a unique expandable physical main memory, which can be operated with one or more typesof addressability protection.
FIGURE lD conceptualling illustrates the preferred embodiment described in this specification.
FIGURE 2A is a diagramatic representation of con-trolled address spaces obtainable in the detailed embodi-ment during operation of a processor and its I/O.
FIGURE 2B illustrates address space control for I/O
operations in the detailed embodiment of the invention executing an operate I/O instruction.

1~9~716 1 FIGURE 3A represents an I/O subchannel N which receives an address key (i.e. CS key) with each subchannel command (i.e. DCB) and provides the address key for each data access to memory for executing the command.
FIGURE 3B illustrates the pertinent parts of an I/O
channel which connects a plurality of subchannels to a storage priority select circuit.
FIGURE 3C illustrates a storage priority select cir-cuit which receives storage access requests and their res-pective address keys from a processor and its one or morechannels to select each active address key (AAK) and an associated program derived address, which are transferred to a translator for physical address generation and then to the main memory for accessing the information.
FIGURE 3D is a preferred embodiment of an AAK select circuit, which contains the equate operand spaces (EOS) features.
FIGURE 4 shows internals of a processor which support address key control.
FIGURE 5 shows the format for the contents of the pro- ~ -cessor's address key register (AKR) used in the detailed embodiment.
FIGURE 6 shows the format of the contents of each seg-mentation register found in the detailed embodiment.
FIGURE 7 is a detailed diagram of the ingate and out-gate controls for a bit position in the address key regis-ter (AKR).

BC9-76-006] -11-109~716 1 FIGURE 8A illustrates diagramatically the operation of the load/store segmentation register instruction, in which one or more designated segmentation registers can be loaded from, or stored to, main memory.
PIGURE 8B illustrates diagramatically the operation of the load/store AKR storage instruction, in which the AKR can be loaded from, or stored to, a word in main memory.

FIGURE 8C illustrates diagramatically the load/store AKR register instruction which can load or store the AKR

from or to a general purpose register (GPR).
FIGURES 9A and 9B illustrate in detail a preferred embodiment of the translator represented in FIGURE lC
which translates a 19 bit logical machine address into a 24 bit physical address for accessing the main memory or the system.
FIGURE 9C, 9D-1, 9D-2, 9E, 9F-l, and 9F-2 illustrate detailed circuits found within boxes shown in FIGURES 9A

and 9B.
FIGURE 9G illustrates the operation of look-ahead circuits shown in FIGURE 9C in selecting one of the inner, outer or asynchronous storage units, and the interpreta-tion of the 24 bit physical address by the selected unit during the access cycle.
FIGURE 10 illustrates a processor mode control cir-cuit used in the detailed embodiment for processor selection of either the non-translation storage protection mode or the translation storage protection mode.

1 FIGURE 11 illustrates protect control circuits used during the non-translation processor mode.
FIGURE 12 illustrates a format for a storage-to-storage type instruction which may be executed in a pro-cessor having the subject invention.
FIGURE 13A shows pertinent format components of an enable/disable instruction used for enabling or disabling the special addressability modes of the processor, such as non-translation storage protect (SP0),translation stor-age protect (TR), and equate operand spaces (EOS) address-ability control.
FIGURE 13B illustrates a sequence of states for an address key register in which the EOS state is implemented .
when an interrupt occurs.
FIGURE 14 illustrates circuitry for implementing an alternate translation protect mode for a processor, which is alternative to the AKR translation protect mode explained in connection with FIGURE lA.

FIGURE 15 illustrates an alternate address-key trans-lation technique which may be used in a processor as an alternative to the plural stack translation arrangement shown in FIGURE lA.
FIGURE 16 illustrates parallel BSM accessing with plural active address keys in a multiprocessing environ-ment.
FIGURE 17 illustrates processor controls for imple-menting the load/store segmentation register instructions shown in FIGURE 8A.
10~,'4'7~

1 FIGURE 18 illustrates AKR loading and storing opera-tions under class interrupt conditions.
IV. INTRODUCTION TO THE PREFERRED EMBODIMENT
FIGURE lA exemplifies the general inventive concept used in the preferred embodiment shown conceptually in FIGURE lD. FIGURE lA has an address key select circuit 20 which relates a particular type of storage access request (signalled by any of lines 21, 22, 23, 24 or 25) to a re-lated one of key register sections 31, 32, 33~ 34 or 35 which respectively contain a CS key, IS key, OPl key, OP2 key, and OP3 key. The related one of these keys is outgated as the Active Address key (AAK) by the AAK select circuits 20. The active address key controls the addressing of main memory of the system during the next memory access, i.e., fetching or storing of data in main memory. In this address-ing operation, the AAK provides the high order part of the logical address used by the machine for accessing the mem-ory.
The access request lines 21, 22, 23, 24 and 25 each signal a different type of access request, which are de-rived from the channels and processors capable of access-ing the same main memory. These request lines are respect-ively labeled in FIGURE lA as I/O access, I fetch, OPl access, OP2 access, and OP3 access. If only one access request signal occurs at any one time, then that access request signal immediately outgates its related address key register section to provide the AAK. If plural access request signals occur simultaneously, then priority cir-cuits in the AAK select circuits 20 determine the order in which each of the simultaneous access requests outgates its 109~71~i 1 related address key as the AAK. A priority order among simultaneous request signals is provided, such as a cycle steal I/O access request is granted first to outgate the CS key. The I fetch request is granted second to outgate the IS key as the AAK. The OPl access request is granted third to outgate the OPl key as the AAK; and the OP2 and OP3 access requests are granted in fourth and fifth order to outgate the OP2 key or OP3 key, respectively, as the AAK.
It can thereby be seen that the invention comprehends a particular relationship between types of access requests and particular key register sections.
The address key sections in a processor are grouped into an address key register (AKR), which contains: the IS key (ISK) register section which is related to each instruction fetch request to control the accessing of each instruction, and the OPl key (OPlK) through OP3 key (OP3K) register sections which are related to different types of operand accesses required for the execution of the instruc-tions.
Furthermore, each I/O subchannel has its respectiveCS key (CSK) register section. Plural I/O subchannels can also simultaneously request accesses to the main storage.
Hence, CSK priority select circuits are provided to present the CSK's in a predetermined sequential order when their requests occur simultaneously.
Still further, if multi-processors access the same main memory, priority-order circuits are provided to select an order among the respecting processor's AAK outputs.

BC9-76-006] -15-1o927~6 l FIGURE lA illustrates a processor/channel AAK system which uses a subset of the types of storage access requests which are architecturally available in the design of a data processing system. FIGURE lB shows a greater number of different storage access types. In any particular data processing system, this invention restricts the use-able storage access types to those which are machine identifiable. That is, circuitry is required within the machine which is capable of sensing each of the different types of storage access requests at the time that each access request is being made. In FIGURE lB, more access types are designated than are used in FIGURE lA. In FIGURE lB, ten storage access types are classified into three access categories: (l) instruction access, (2) operand access, and (3) the access category related to processor events. Each channel contains K number of sub-channels, and each subchannel has three storage access categories: (l) command access, (2) I/O data access, and (3) the access category related to I/O events.
Each access category provides at least one storage access type.
In a given machine, the only storage access types which can be used are the types which are manifested in the machine design by an identification signal, e.g. stor- ~
age request signal. Thus, the instruction access cate-gory is machine-identified by an instruction fetch request signal. The operand access category can be machine-identified by six different types of operand access types in FIGURE lB; these are sub-categorized 109~7~6 l into direct and indirect operand access types, in which the direct access sub-category includes accesses of addresses directly generated from the instruction, while the indirect access sub-category includes operands at addresses generated indirectly from the operand address in an instruction. Each sub-category has three different operand access types, which can be machine-identified as a source fetch request signal, a sink store request signal, and a sink fetch request sig-nal. Each of these six operand types may be architected into the design of a machine, and its machine-identifica-tion signals are determinable generally from the operation code of each instruction and its field(s) occupied by operand(s). The source fetch operand type applies to data which is used as a source of an instruction execution; it is not to be changed but is only used to generate the re-sults of instruction execution. On the other hand, the sink store operand type refers to an access which stores the results of execution of an instruction. The sink fetch operand type is a result of a prior instruction execution which result is to be accessed as the source of the current instruction execution. In many computer systems, it has been found more efficient to architect the sink store oper-and type and the sink fetch operand type into a single sink store/fetch operand type.
Processor event accesses are caused by the occurrence of internal processor events, such as data error, machine failure, addressing exception, etc., of which includes a 109'~716 1 long list of well known events which cause conventional processor interrupts, i.e. internal interrupts. For ex-ample, the processor event access category includes an access into an area of main memory containing an inter-rupt handler and other programs for handling the inter-rupt-related signals as well as storing the data related to the interrupt, such as log-out data.
Similarly, each channel has a plurality of sub-channels which perform a plurality of different types of accesses.
Thus, each subchannel is categorized as having an I/O data access category which can have an I/O fetch access type and an I/O store access type. Some machine architectures find it efficient to combine into a single type of access which is an I/O fetch/store access type. The subchannel event type of access is signalled by interrupts external to the processor, i.e. external interrupts. Many differ-ent types of external interrupts are conventionally used, such as the device end interrupt, device failure inter-rupt, I/O data error interrupt, etc.
In summary, the subject invention comprehends pro-viding the capability in a machine for obtaining separate addressability in main memory for each of the different types of storage accesses shown in FIGURE lB, which in-clude the eight different storage access types available to each processor and the four different storage access types available to each subchannel. This capability for separate addressability is provided 1o~7i6 l by means of a separate key register section for each of the respective storage access types designed into a machine.
However, the embodiment represented in FIGURE lA uses only four different processor access types which are re-presented in the illustrated example of an AKR having four different register sections. The number of key register sections in the ARR may be expanded to whatever number of access types are required in the architecture of a machine.
Thus, whatever the number of key register sections provided in the system,the AAK select circuits match up each machine-identified access type with a corresponding AKR register section or a CS register section by outgat-ing the selected register section when the respective access request is granted, so that the content of the selected register section becomes the active address key which the machine uses as an address component to control the addressability for that particular memory access. The address component provided by the AAK can have either (1) a direct physical address relationship in which the AAK
is concatonated with the program address, together provid-ing a physical address in main memory, or (2) a fixed pre-determined storage access relationship in the main memory, such as represented in the embodiment in FIGURE 11, or (3) it can have a relocatable address relationship for the key-identified storage areas while requiring program address sequencing within each area as in FIGURE 15, or (4) it can have a more flexible relocatable address rela-tionship having relocatability within the key-identified areas, such as represented in the embodiment in FIGURE lA.

109~71~

1 The maln memory input address provided by the machine in FIGURE lA is the combination of the AAK and the program apparent address. The program apparent address is the address apparent to the machine from a program being exe-cuted, such as the instruction fetch address in the in-struction address register (IAR), and the operand address(es) in the instructions of the program. When a program is written, the program only handles program apparent addresses.
The application programmer is cognizant of AAK operations only to the extent that he groups his operand data separ-ately from the program. The system programmer will gen-erally specify the processor event access areas and their contents, and the I/O programmer will generally specify the I/O command and event access areas and their contents.
In FIGURE lA, the AAK component occupies K number of bit positions in the high-order part of the combined input address, and the program apparent address occupies 16 bit positions to provide a total of 16+K bit positions in the input address of the machine.
In FIGURE lA, the input address, including the AAK
field, is a machine logical address which requires trans-lation for accessing a required location in the data pro-cessing system. On the other hand, in FIGURE 11 the in-vention comprehends using the AAK, for example, as a directly-useable restriction on the physical address, which is not translated.
IV A Plural Stack Translator The translator in FIGURE lA has a plurality of seg-mentation register stacks 0 through 2K. Each address 109~716 1 key register sections in the processor or subchannel con-tains at least a K bit key, which has a value that can address any one of the eight stacks. A stack address means 40 receives the AAK and decodes the stack address to select the required stack. Then the high-order bit positions 0 through P of the program apparent component of the input address selects a segmentation register (SR) within the selected stack. The content of the bit posi-tions 0 through 12 of the selected SR contains an assigned block number which provides bit positions 0 - 12 in the physical address of a particular physical block in the main memory, which is then accessed.
The remaining bit positions 13 - 23 of the twenty-four bit physical address provide the byte displacement (D) within the selected physical block, and they are the same a~ the byte displacement D in the input address determined by its low-order bits (PH) through 15. The access into the particular physical block is also con-trolled by flag bits in the remaining bit locations 13 through 15 in the selected SR. The format for any SR is shown in more detail in FIGURE 6 in which the validity bit (V) position 13 indicates whether the block number content i8 valid. If invalid, (i.e., V=0), the content of the selected SR cannot be used for generating a physi-cal address, and an addressing exception interrupt is generated. Flag bit position 14 indicates whether or not the content of the addressed block may be read only or not. If bit 14 is set to 1, no write access is permitted to the block, and fetch~only accesses 109h,716 1 are permitted. Bit 15 is not used. The second word com-prised of bits 16 through 31 is reserved and also is not used for the purposes of the subject embodiment.
IV.B. Extendable Main Memory FIGURE lC illustrates a configuration of a data pro-cessing system having a novel extendable main memory for handling translated addresses. The minimum main memory contains an inner store 51 which contains up to 64K bytes of storage. The first extension is the addition of an outer store 52 which can add 64K bytes of storage to ex-tend the main memory to 128K bytes. Then an extendable asynchronous store 53 can be added to extend the main memory to a maximum of 16, 777, 216 bytes (i.e. 224).
A translator 59 provides the address translation and contains interfaces which enable the extendable connections of the outer store 52 and asynchronous store 53 to the main memory configuration.
A main storage bus 56A connects a processor 54 and I/O channel 55 to the main memory configuration through a storage priority select circuit 55. The main storage bus 56A is also connected to translator 59 and to the inner storage 51.
Inner storage sequential signal lihe 54A connect inner storage 51 directly to storage priority select cir-cuit 56 to transfer inner storage cycle (ISC) signals, when they represent a 16 bit non-translated physical address generated by the processor operating in non-translate mode. When the processor is in translate mode, the ISC derives its five high-order bits from the trans-lator , 10~716 1 which compri~e a card select signal (that ~elcct~ a 2 particular card from up to four cards compri~ing 3 the inner storage) and CSY and CSX fields (that ~lect 4 a particular array on the selected card, which array contains 4,096 bits). The five high-order bits on 6 address bus lines 00-04 are transferred from the 7 translator to the proce~sor for usage by the proce--or 8 during an ISC. Bits 13 through 22 are provided by the g processor SAR to ~elect the particular word position on the array, and the remaining bit 23 selects a
11 particular byte in the word when a write operation i-
12 required. The byte addressing obtained by bit 23 i~
13 only used for write operations, since read operation-
14 are addre3sed on a word basis (a word comprises two bytes). During a write function, the last addres~ing 16 bit 23 is set to either 0 or 1 to address either the 17 left or right byte, respectively, in a word.
18 When the processor operates only with the inner 19 storage (i.e. without having the outer storage or asynchronous storage in the system), the processor 21 only addres~es the inner stora~e with physical 16 bit 22 addresses directly provided on bus 54A from the SAR.
23 The 16 bit addres~e~ provided by the processor extend 24 up to the phy~ical limit of the inner storage (i.e. to 64K). Protect keys are used with the 16 bit physical 26 addresses in this minimum configuration system in 27 accordance with the non-translate protect circuits in 28 FIGURE 11.

10~716 1 The protect key~ u-e the c~pability for ~eparate 2 addressability provided by the address-key regiJter 3 sections for the different storage acce~ type~ The 4 combination~ of the AAK circuits with the pr~tect key-i~ also an inventive feature described in this specifi-6 cation Thus, the broader invention of the active addre--7 key circuits to provide the capability of separat-8 addresssbility by storage access type is ~eparately g combin~ble with the non-relocatable protect keys or the relocatable addres~ keys 11 If it is de~ired to have relocatability, which 12 permits the main memory to be extended beyond the 13 64X limits of the inner storage unit, then the translator 14 needs to be added as shown in FIGURE lC The outer storage can then be added and connected to the transl~tor 16 by the outer ~torage sequence signal bus 58 to provide 17 the outer storage cycle (OSC) controls shown in FI6URE 9G
18 The translator also permits a further extension 19 Of the main memory behond the 128K limit of the inner and outer storage units by permitting the addition of 21 an asynchronous storage unit The asynchronous storage 22 unit uses the translated 24 bit address in a different 23 way than does the outer store, as is shown by the 24 asynchronous storage cycle (ASC) in FIGURE 9G With the ASC, bit positions 0 through 6 are used and these 26 bit-positions will contain at least one 1 bit because 27 it takes more than 16 bits to represent a number in 28 exce8s of 128K The use of bit positions 0 through 6 29 distinguishes the ASC from the OSC which does not use 109~71~i 1 bit positions 0 through 6; the OSC uses only bit~ 7 2 through 23. These char~cteri~tics of bit po~ition~
3 0 through 6 are used in setting a pair of look ahead 4 bit~ shown in FIGURE 9G, which have their circuit~ and operation described in more detail in connection with 6 FIGURES 9A and 9B.
7 The translator has a connection to main storage 8 bus interface through which it rece1ves the logical 9 addresses from the processor including the active addre~s key for tran81ation. The tran~lator al80 11 ha8 interface8 connected to the outer storage ~nd 12 a8ynchronous storage units.
13 IV.C. Space Control In The Preferred Embodiment 14 FIGURE 2A is a diagram which represents different storage access types controlled by the different type- of 16 proce880r in8truction8 and channel commands in relation 17 to corresponding data spaces used in the detailed em-18 bodiment. FIGURE 2A includes only a subset of the,access 19 types illustrsted in FIGURE lB. Thus, in FIGURE 2A, an instruct1on fetch is done in instruction address space 21 60 using the ISK. Two different operand access types 22 are ~hown in FIGURE 2A, which are defined by the data 23 spaces 61 and 62 which respectively use the OPlK and OP2X
24 register sections in an address key register (AKR).
IV.C.l. Processor Space Control '26 FIGURE 2A illustrates the storage accessing occurring 27 with different processor instruction types. A storage-28 to-storage instruction fetches data in the OPlX data 29 space 61 or the OP2K data space 62 and stores its results 10 ~ ~ 7 1 ~

1 into the OP2K data ~pace 62 A ~torage intermediate 2 instruction obtains its data from the ISK data space 3 60 and stores its result~ into the OP2K data epace 62 4 or into a general purpose register (GPR). A register-to-etorage instruction type moves data from a GP~ 63 6 to OP2K data space 62; while a etorage-to-register 7 instruction fetche~ data from the OP2X data space 62 8 and stores it into a GPR 63. A branch inetruction fotcho-g a target branch instruction also from the ISK addre-e ~pace 60.
11 IV.C.2. I/O Subchannel Space Control 12 Two different types of I/O subchannel commands 13 are shown in FIGURE 2A. One type called a direct 14 program control (DPC) I/O command provides an I/O
operation which i8 synchronous with the main program, 16 i.e. the main program does not continue until the I/O
17 operation i~ completed, in which both the I/O command 18 and the data access are in the OP2K address space 62.
19 The other type of I/O command provides the normal asynchronous type of I/O operations, generally known as 21 cycle steal (CS) I/O operations. In the eecond type, the 22 I/O program itself (i.e. the channel conm~nds) must be 23 located in the key=O address space 64 in FIGURE 2A, while 24 the data accesses performed by the channel program are controlled by k~ys specified in the respective channel 26 commands, so that each command (i.e. DCBJ has the 27 capability of defining a different address space 65...66.
28 That is, each I/O device has its own subchannel program-29 in which each command is capable of depositing a different 109~716 1 key value in an address key register section of each sub-channel, so that it is possible for each subchannel to access a different address space on each command. Thus, each channel has the capability of switching its accessed data space easily whenever needed.
FIGURE 2B illustrates in more detail the manner in which the I/O operations can control their address keys to define different data spaces in main memory.
In FIGURE 2B, an operate I/O instruction is in the main program to initiate an I/O operation, and hence the operate I/O instruction is in the ISK data space. The OP
part of the instruction indicates that it is an operate I/O instruction, and the R2 field designates a register which contents are combined with the address field, ADDR, to generate an address which directly or indirectly lo-cates an IDCB (indirect device control block) in the OP2K
address space. If indirect addressing is used, the in-direct address itself resides in the OP2K space. The IDCB
address is either direct or indirect depending on the setting of the I bit in the operate I/O instruction. Thus, the operate I/O instruction is in the ISK address space and the IDCB is in the OP2K address space.
The IDCB can be of two different types, (1) a CS
type, or (2) a DPC type. The command code, CMD, field in the IDCB identifies whether it is to initiate a CS
operation or DPC operation.

10S ~'716 1 If the IDCB is a DPC type, its second word contains immediate data which is either transferred to the device addressed or received from it depending on whether the command field indicates it is an I/O read or write opera-tion.
If the CMD field indicates the IDCB is a CS type, the second word in the IDCB contains the address of the subchannel program for the device addressed by the DA field in the IDCB. The first channel command (i.e. channel con-trol word) called a device control block-0 (DCB-0) is lo-cated at the address in the IDCB. A field in DCB-0 called chain address locates the next subchannel control word called DCB-l, which also contains a chain address that lo-cates the next DCB, etc., until the last DCB is indicated.
The entire channel program is therefore located in the key=0 address space in the detailed embodiment.
However, each DCB in its initial word location EA
contains a key field, which is the address key for data accessed by that particular DCB. For example, DCB-0 has a key field identified as the DCB-0 key, which identifies the address space for a contiguous block of logical ad-dresses beginning at the data address in the DCB-0 field located at EA+14. The DCB-0 key can have any key value.
Similarly, the next control word DCB-l contains a DCB-l key, which can have any key value to define the address space for the data addressed within the DCB-l. Hence the key value in DCB-l can be different from the key value in DCB-0, etc.

, ' ' ', ' :: ' 10~716 1 It can therefore be seen that this invention provides tremendous flexibility in address space control during operation of the I/O devices in the system. With non-translation mode protect keys, different key values can be used in the DCB's to obtain special protection for the I/O data accesses~
Furthermore, if the translation mode is being used in the system, all I/O data addresses are translated by the translator, e.g., in FIGURE lD, for each access in the same manner that processor addresses are translated.
FIGURE 3A illustrates the hardware for controlling the DCB key operations. Each I/O subchannel contains a small processor-like controller for controlling the opera-tions of a connected I/O device, which may be any type.
This processor-like controller controls the handling of the DCB key by the particular I/O subchannel. The DCB
key is received in a DCB key register 301 in the subchan-nei controller from the I/O data bus from the channel, while each DCB is being accessed in the key=0 address space.
A plurality of subchannels are generally connected to a single channel in the conventional manner. Any sub-channel can communicate with the channel by conventional handshaking signals provided between subchannels and their channel. This results in a poll capture by the subchannel requesting channel service. After the poll capture, the channel data bus transmits control signals and data be-tween the subchannel and the main memory. Thus, a signal by the poll capture controls to subchannel ROS

109~716 1 controls 311 causes required ROS words to be inputted into a ROS data register 313 to obtain the subchannel opera-tions necessary. One of the subchannel operations is a DCB fetch of the next address field in the current DCB
from the key=0 address space. The DCB fetch field in a ROS word is detected by a ROS decoder 314, which then pro-vides a DCB fetch control signal that activates AND gates 315(0), 315(1) and 315(2) which ingate the DCB key regis-ter 301, which is part of a register stack which receives the entire DCB. After the DCB fetch is completed, the DCB
is stored in the subchannel, the DCB fetch signal is dropped, and a not DCB fetch control signal is activated which conditions the DCB key register AND circuits 316(0), 316(1), 316(2) to outgate the DCB key, which is thereby provided as the CS key for the DCB data access operations.
The CS key is transmitted on the condition code bus to the channel in FIGURE 3B. Then the channel transmits the CS key to the CS key bus which connects to the storage priority select circuit in FIGURE 3C.
IV.C.3 Storage Priority Select Circuit In FIGURE 3C, the CS key on the channel bus is pro-vided to a channel select circuit 331 which receives the channel buses from all channels connected to the pro-cessor and gives priority to one of the CS keys from one of the channels.
Each subchannel controller in FIGURE 3B also has a plurality of control lines comprising a control bus and an I-/O address bus. The I/O address bus communicates iO r3 ~ ;~16 1 the data address derived from the DCB. The I/O control bus includes a CS request in line which signals when an address is on the I/O address bus.
The storage priority control circuit 56 receives the CS cycle request lines from each of the plural channels 1 through P connected to a processor. A particular CS
key is selected by circuit 332 at any given time, and it is then provided to channel select circuit 331 which trans-fers the CS key of the selected subchannel to AAK select eireuits 333, whieh also reeeive the proeessor address keys from the processor AKR buses. Under control of the storage priority cycle circuit 332, the AAK select cir-cuits 333 select one of its received address keys at a time as the system AAK. FIGURE 3D illustrates a detailed form of AAK select circuits 333.
IV.D. Preferred Processor Embodiment The processor AKR busses eonneet to outputs of the AKR in FIGURE 4, which illustrates in detail the perti-nent parts of the system proeessor, whieh may be eontend-ing with the CS keys for a storage aeeess. In FIGURE 3C,storage priority eyele eireuit 332 (whieh may be a eonven-tional priority eireuit) determines the order in whieh the aeeesses are granted among the eontending requests, and therefore the order in which the respeetively in-putted address keys beeomes the AAK output of the AAK
seleet eireuits in FIGURE 3D.
FIGURE 4 illustrates the eontrols in the proeessor whieh operate its AKR. Thus, the eontent of the AKR is loaded from the proeessor data path bus on the 10~"716 1 ingate (IG) controls, and the respective address keys are outgated to the processor data path bus by outgates (OG) controls. The IG and OG control signals are gen-erated by the processor ROS decoder. The content of the AKR is continuously outputted to the processor AKR
busses, ISK bus, OP2K bus, OPlK bus and EOS bus, which are inputted to the AAK select circuits 333 in FIGURE 3C, which is shown in detail in FIGURE 3D. The AAK select circuits perform the selection among these three pro-cessor keys in conjunction with any presented CS key to determine which particular one of the keys will become the AAK.
FIGURE 7 illustrates in detail the AKR control cir-cuitry by illustrating the ingate and outgate circuits with a single bit position in the AKR. Each of the other AKR bit positions has similar control circuits.
It is therefore seen in FIGURE 4 that the processor ROS decoder 405 has output lines which are activated by particular ROS words in the ROS data register 406 for con-trolling the ingating and outgating of the AAKR registersections, ISK, OPlK, and OP2K, as well as other processor operations.
IV.D.l. Last AAK Register The processor in FIGURE 4 also contains a last active address key register which is ingated by an AAK ingate 407, which receives the AAK bus output from FIGURE 3D and receives another input which is the inverted signal from a processor error latch 401. The output of the AAK IG
407 is inputted into a last AAK

109~716 1 register 408 during a processor storage cycle from FIGURE 17. Register 408 operates to store each AAK pro-vided on the AAK bus from the processor AKR, as long as error latch 401 indicates no error on an error disabling signal line.
However, on the occurrence of a machine check (MCK) or a program check (PCK) error in the processor, error latch 401 is set. This causes a deactivation of the AAK
IG 407 due to droping the error disabling signal to require retention of the last processor AAK (i.e. LKSA) existing at the time of the error until latch 401 is reset. The machine check (MCK) and program check (PCK) signal inputs are provided to a forced address decoder 402 (except dur-ing a segmentation register cycle) to force a ROS address to the ROS control 403 that causes a particular diagnos-tic program to be initiated for handling the error condi-tion either by retry of the erroneous function until it is corrected, or by executing a log-out operation when the error is determined to be permanent. The last AAK
register 408 thereby maintains the LKSA for providing the addre~sability last used while error recovery operating conditions are provided in the processor, so that after the error condition is cleared, the system is able to return to the normal addressability last used.
One of the final diagnostic operations occurring before any processor state can be changed is to store the entire status of the processor in a level status block (LSB) in main memory, including the content of the AKR. Then, an OG AAKR (outgate last AAK register) signal outgates the LKSA content of the last AAK

109~71~;
1 register to the processor data path and an IG OPlK sig-nal simultaneously occurs to put the LKSA into the OPlK
register section of the AKR for the diagnostic or error recovery operations. (See Section IV.H.3. herein.) When error recovery is completed, the last normal AKR value is reloaded from the LSB in memory for picking up normal operations.
IV.D.2. AKR Load/Store Instructions FIGURES 8B and 8C illustrate the instructions for con-trolling: (1) the loading of address keys into the AKRfrom either a word in main memory or a designated GPR, or (2) the storing of address keys from the AKR into either a word in main memory or into a designated GPR. FIGURE 8B
illustrates the load or store AKR storage instruction operation. This single instruction can control either the loading of the AKR from the main memory or the storing of the content of the AKR into the main memory.
FIGURE 8B illustrates the 16 bit format of the load/store AKR storage instruction, which is designated by its five bit OP code and its three bit modifier field in bit positions 13-15. The K field in bit positions 5-7 addresses a part or all of the AKR which is to be ingated or outgated. For example, the K values of 0, 1, 2 or 3 respectively designate the ISK register section, OP2K
register section, OPlK register section, or the entire AKR which is to be used by the instruction. A main memory logical address is generated by using the RB field at bit 10~716 1 positions 8 and 9 that designate a base regl~ter and 2 the AM ~access mode) bit~ 10 and 11 that de~ignate 3 whether a word i8 an ~ppended field to in~truction 4 which contains an address field, wherein the content~
S of the AM field and of the R~ register are combined 6 to generate the effective address in main memory of 7 the word which is to be either loaded or stored by 8 execution of the in~truction. Bit X at bit position 9 12 designates whether the instruction operation is a load or store. If X is set to 0, the content of tho 11 adqressed word is stored into the AKR portion de~ignat-d 12 by the K field. If the X bit is set to 1, then the 13 designated AXR portion i~ stored into the addressed 14 word.
Similarly, FIGURE 8C describes the operations 16 for the load/store AXR register instruction, which i~ -17 similar to the AKR ~torage instruction in FIGURE 8B
18 except that a GPR is substituted for the main store 19 word in the execution of the register instruction.
Thus, in FIGURE 8C, the R field at bit positions 8-10 21 designates a particular GPR which either loads or 22 stores one or more keys into the designated part(s) of 23 the AKR.
24 These respective operations are executed in the processor by signals on the respectively labeled IG
26 and OG output lines of the processor ROS decoder 405 27 in FIGURE 4 which actuate signals on the data path in 28 the processor to perform the operations described in 29 connection with FIGURE 8B.
BC9-76_006 109~716 1 IV.E._ Preferred Trailslator Embodlment 2 FIGURES 9A and 9B illustrate in dotail the 3 circultry in tran~lator 9 in FIGURE lC which perform~
4 the relocation translation operations described for FIGURE lA. Thi8 relocation translator circuitry 6 i~ capablo of oxtending the physical addro--ability 7 from 64X (216) bytes to 16 million (224) byto-, whlch 8 is an extenslon of an inner ~tore contalnlng 64K
g byto-Th- tran-lator lncrea~o~ the addre~-ablllty of 11 the maln momory by interpreting the AAK and the 16 12 bit program-apparent-address from either a processor 13 or a subchannel as a logical input address to the 14 translator, which translates it to a 24 bit physical addre8s which accesses the inner, outer, or asynchronou~
16 store components 17 The translatlon allows dynamic allocation of 18 phy~ical storage to logical address space~ and the 19 sharing of physical storage among logical address spaces Eight set~ of 32 segmentation registers 21 (SRs) exist for the respective eight values available 22 for the address keys for a total of 256 sQgmentation 23 regi~ters Once loaded, each SR stack can contain 24 a complete msp of a storage space having up to 64K
bytes, which may be scattered in 2K byte blocks of 26 physical memory A stack can address a ~pace having 27 less than 64K bytes by merely setting the invalid bit 28 in one or more of its SR'8 80 that only the SR~
29 having their invalid bits off designate the 2K blocks comprising the addressable space identified by an 31 assigned address key lOg~7~6 1 A ~eparate stack of segmentation registers are 2 provid~d for each Address key to allow fast ~witching 3 of log~cal address spaces without the need for saving 4 and re~toring the address space ~torage map of th~
system.
6 The relocation transl~tor in FIGUR~S 9A and 9B
7 supports an extension of the main memory by an outer 8 storage of up to 64KB in increments of 16KB cardu which g are designated as the fifth through eighth cards for the outer store. The inner store will contain the 11 firat through fourth cards, each likewise having the 12 16KB storage capacity. Storage increments beyond the 13 128KB capacity of the inner and outer storage require 14 the ~ddition of the asynchronous storage unit in FIGURE lC, which provides addresses above 128KB that 16 may extend up to a maximum of 16 million bytes of 17 physical memory.
18 The maximum static machine addressability ayailable 19 to all concurrent programs when all segmentation regi~ters are loaded with a different physical block address i8 21 219K bytes, which is determined by the 19 bit input 22 address seen in FIGURE lA when the 3 bit AAK is appended 23 to the 16 bit program apparent address to provide the 24 19 bit machine lcgical input addre~s to the translator.
A single program can have an addressability of from one 26 to three different address spaces defined in the threo 27 sections of the AKR, e.g. ISK, OPlK, and ~P2K, for a 28 total static addressability of from 64K to 192K bytes.

~0~ 7 ~

1 Thus, for a physical main store between 512K and 2 16M bytes, only up to 512K bytes can be addressed at 3 any given loading of the segmentation register~; thi~
4 i8 defined a8 the maximum static machine addre~sability.
Therefore, Addressing beyond the 512R byte static 6 maximum requires reloading of the segmentation regi~ter-7 by software to gain addressability to other area- in 8 the main store which may be loaded.
g The static addressability can easily ~e extondod by adding more bit~ to the size of the address key in 11 tho AXR and associated circuits to support a corre~pondingly 12 greater number of segmentation register ~tacks.
13 When a translator is installed in the ~ystem as 14 ~hown in FIGURE lA, its use is controlled by a bit 14 in the processor statu6 word (PSW) which is controlled 16 by output lines of the processor ROS decoder in FIGURE 4 17 under control of the enable/disable instruction illu-18 strated in FIGURE 13A. Bit 14 in the enable/disable 19 instruction indicates whether or not the translator is ~elected in the system and bit 7 indicates whether it 21 is to be enabled or disabled. The circuit in FIGURE
22 10 controls whether the translator is enabled or not.
23 If the translator is not enabled, and if the SP bit 24 i8 on in the instruction illustrated in FIGURE 13A, the non-translatable storage protection control circuit 26 shown in FIGURE 11 used. Where only small addre~ability 27 and fastest processing speed are needed, the tran~lator 28 may be disabled.

~0~"71~;

1 FIGURES 9A and 9B illustrate in detail the circuits buses, and interface lines in translator 59 in the sys-tem in FIGURE lC, as follows:
IV.E.l. Processor/Translator Interface (1) Storage address bus 901. It has 15 lines that connect the program logical address in the pro-cessor storage address register (SAR) to the translator. After address translation, the translated five most significant bits are sent back to the processor for usage in addressing inner storage 51 as necessary. The ten least significant bits (D field bits) do not require translation.
(2) Storage data bus 902 to storage. It includes 16 data lines plus two parity lines. It trans-fers storage data and segmentation register con-tents from the processor to the translator.
(3) Storage data bus 903 from storage. It includes 16 data lines plus two parity lines. It trans-fers storage data from the translator and the content of the segmentation registers (SRs) tothe processor.
(4) Active address key (AAK) bus. These three lines transfer the AAK from the storage priority select circuit in FIGURE 3C to the translator for select-ing the particular SR stack in the translator.

~09~716 1 (5) Storage write OP 0. A single line from the 2 proce~sor that signal~ the translator that a 3 write operation is to occur in the memory to 4 the left-most byte of the word of data currently on the ~torage data bus to storage. This line 6 i8 controlled by the zero state of the lowe~t-7 order bit 23 in the 24 bit physical addre~s.
8 (6J Storage write OP 1. A single line from the g processor to the translator to sîgnal that a write operation in memory is to be performed in the 11 right-most byte of the current word on 12 the storage data bus to storage. This signal 13 is also controlled by the one state of the 14 lowe~t-order bit 23 in the 24 bit phy~ical address.
16 (7) Translator enable. A single line which tran~mits 17 a processor signal to the translator to enable 18 the translator for performing its translate 19 functions. It is controlled by the enable/disable instruction.
21 (81 Storage request to translator. This single line 22 communicates a processor signal which requests 23 the tran~lator to translate the logical addre~s 24 on the storage address bus. One micro cycle (220 nanoseconds) is automatically skipped to let 26 the translator access the appropriate segmentation 27 register, obtain the physical address, and deter-28 mine whether a reference ~hould be made to the 29 inner, outer, or asynchronous storage.

1 0~716 1 (9) Timing pulses A, B, C, and D. These four lines transmit processor timing pulses of 55 NS which provide synchronism between the processor and translator.
(10) Gate translator SAR. This line signals that the translator has placed the five most significant bits of the translated physical storage address on the storage address bus 55NS after this sig-nal is activated. It indicates to the processor that it should gate address bus bits 00-04 of the translated address to the inner storage unit.
(11) Inner Storage cycle (ISC). This line provides a translator generated signal which alerts the processor to provide storage sequencing signals to the inner storage 51 with each new physical address. If an outer or asynchronous storage cycle (OSC or ASC) is to be used, this line is made inactive, so that inner storage is not selected.
(12) Translator storage busy. This line carries a translator generated signal which indicates to the processor to stop its clock. This line is activated only on references to the asynchronous storage unit 53. When the translator has ob-tained the appropriate response from the asyn-chronous storage unit 53, this line is deacti-vated, and the clock starts again to complete the storage cycle. This stopping of the stor-age clock by an asynchronous storage unit opera-tion is what makes its operations asynchronous and its access cycle longer than the access cycle in either the outer or inner storage units 51 or 52.

109"716 1 ~13) Translator Installed. This line carries a 2 translator generator ~ignal which inform~ the 3 processor that translator 59 ha~ been installed 4 in the system.
(14) Translator ISA (invalid storage address).
6 This line carries a translator generated signal 7 to the processor that informs it that the current 8 logical address issued to the translator is 9 invalid, and a program check (PCK) then occurs.
(15) Translator protect check. This line carrie~
11 a translator generated signal to the proces~or 12 that indicates that an attem~t has been made to 13 write storage in the problem state in a block 14 having its ~egmentation registers read only bit 14 set to 1 which indicates the read only state
16 is permitted.
17 (16) Supervisor ~tate or Cycle Steal cycle. This
18 line carries a processor generated signal to the
19 translator that it should ignore the ~ead only bit 14 in the addressed segmentation regifiter, 21 becau~e the current storage access request i8 by 22 either the supervisor or an I/0 subchannel.
23 (17) EOC (end of cycle) sequence. This line carries 24 a processor generated signal which informs the translator that it is finishing its storage cycle.
26 (18) Segmentation register cycle. This line carries a 27 processor generated signal which alerts the 28 translator that the segmentation registers will 29 be activated. The storage write oP 0 and storage ~C9-76_006 ~O'J'~71~
1 OP 1 lines are used also to indicate whether the cycle is a read or write cycle as part of a store segment register instruction or a load segment register instruction, respectively.
IV.E.2. Translator/Outer Storage Interface The translator (XLATOR) to outer storage unit inter-face in FIGURE 9B and includes the following lines:
(1) Card Select lines. These four lines are res-pectively identified as the 80K, 96K, 112K and 128K card select lines to select a 16K byte card in the outer store.
(2) TCSX, and TCSY lines. These six lines signal the X and Y Y coordinates on the selected card to select a particular array on the card.
(3) Write Byte 0 and Write Byte 1 lines. These lines are write strobes to the four outer storage cards for writing a byte.
The translator, upon obtaining the physical storage address from the appropriate segmentation register, deter-2~ mines whether a reference is to be made to the inner,outer or asynchronous storage and will sequence the Xlator/
outer storage I/F lines only if an outer storage cycle is indicated. The jumpers installed with the outer storage controls in FIGURE 9B indicate which of the four cards are installed in the outer storage unit.
IV.E.3. Translator/Asynchronous Storage Interface The lines in the translator (XLATOR) to asynchronous storage interface in FIGURES 9A and 9B are as follows:
(1) Asynch Storage Parity/Data Out. These 16 data lines and two parity lines comprise the stor-age data bus to the asynch storage unit.

10~'71~;

1 (2) Asynch Storage Parity/Data In. These 16 data lines and two parity lines comprise the stor-age data bus from the asynchronous storage unit to the processor and channel.
(3) Asynch Storage Lower SAR Out. These 13 lines carry the 13 most significant bits in the physi-cal address which comprise the block address in the asynchronous storage unit. They comprise the upper SAR bits 0-12 shown in the asynch stor-age cycle in FIGURE 9G.
(4) Asynch Storage Upper SAR Out. These 10 linescarry the 10 least significant bits 13-22 in the ASC, but not bit 23 in the ASC in FIGURE 9G.
Bits 13-22 address a word in the select block.
(5) Write Byte 0. This line carries the lowest bit position 23 in the physical address to indicate whether the left most byte in the addressed word is to be a store operation during the asynchron-ous storage cycle.
(6) Write Byte 1. This line informs the asynchronous store that the right most byte in the currently addressed word is to have a store operation dur-ing the asynchronous storage cycle.
(7) Asynch Storage Select Out. This line indicates to the addressed storage module to begin a stor-age cycle. This select out line is only activated during an asynchronous storage cycle and when no logical instruction storage address or protect check has been detected by the translator.

lOg'~71~

1 (8) I/F Clock and I/F Clock 90. These two identified 2 ~ clock cycles have a 440 NS period with a 50~ duty cycle.
3 These clock cycles are 90 out of phase with each 4 other and are only active while the select out line is active. These clock cyclefi may b~ u-ed by 6 the asynchronous ~torage unit for timing within the 7 unit, for resolving refresh contention, for 8 latching data, and for generating responses at thQ
g appropriate timefi.
(9) Response In. This line receives a signal from 11 the asynchronous storage unit that the addres~ed 12 location i~ installed.
13 ~10) Write Strobe. This line ifi activated during the 14 later part of a write cycle to the selected asynchronoufi storage module, after refiponse in 16 fiignal ifi received by the translator. The write ~trobe 17 line is activated only while the select out l$ne 18 ifi activated.
19 (11) Normal Asynch Storage EOC (end of cycle). Thi~
line providefi a fitrobe pulfie if the response in 21 line receives a signal from the async~ronous 22 store. It is used afi an ac~nowledgement by the 23 fielected asynchronoufi store to accomplish 24 refietting of any latches set up during the cycle and to prevent refielection during the fiame cycle 26 durinq the fall of the fielect out signal.
27 IV.E.4. Segmentation Register Selection 28 The segmentation register control circuits are shown 29 in detail in FIGURE 9C. A SR is selected by a funneling technique. First, the required register position ifi 10~ ~7 1~

1 selected in all etacks by addressing all register~ with 2 the high-order bits 0-4 in the program apparent 3 loqical address, ~o that the selected register in each 4 ~tack are the output~ of the eight stacks. Then the AAK bit~ are used to stack select among the selected 6 registers being outputted from the eight stacks to 7 narrow the Qelection to the particular register 8 required. This is done by first applying the state g of AAK bit 2 among the selected SR' 8 to narrow the election to four SR' 8 ~ either from the odd or even 11 ~tack~. The AAK bit 1 true (T) and complement (C) 12 line~ are then applied to select one of two groups of 13 stack outputs which will be either the outputs of st~ck-14 0,1 and 4,5 or of stacks 2,3 and 6,7. (The comma (,) means "or" between its stack numbers in this notation.) 16 Thus, a pair of registers will be outputted, which 17 will be from either stacks 0,1 and 4,5 if AAK bit 1 18 has 9tate 0, or the pair will be from stacks 2,3 and 19 6,7 if AAX bit 1 has state 1. The resultant pair is further narrowed to a single register by the state of 21 the SR hi-low select bit (AAK bit 0) applied to two-way 22 funnel 921 in FIGURE 9A which selects between the 23 selected pair of stacks to output only a single 24 stack which provides the selected remaining register, which is the required register.
26 IV.E.5. Seqmentation Register Load/Store Controls 27 FIGURE 8A illustrates the operation of the load/~tore 28 segmentation register (SR) instructions. FIGURE 17 29 illustrates processor storage controls and FIGURES 9A and 109~71~;

1 9B contain the pertinent translator control~ u~ed in 2 executing the6e instruction~.
3 In FIGURE 8A, the load SR ins~ruction control~ the 4 setting of a physical block address into a selected SR
s from an addre6sed word in main memory. The ~tore SR
6 instruction controls the copying of the content of a 7 selected SR into an addressed word in main memory.
8 The 16 bit format of each load/store segmentation g register instruction is designated by a five bit OP cod~
and a three bit modifier field in bit position~ 0-4 and 11 13-15, respectively.
12 Bit X at bit position 12 in the SR instruction 13 designates whether the instruction operation is a load 14 or store. If X is 6et to 0, the content of the addressed word in memory iB loaded into the selected segmentation 16 register. If the X bit is set to 1, then the selected 17 ~egmentation register has its contents stored into the 18 addressed word.
19 The R field in bit positions 5-7 addresses a general purpose register (GPR) which contains the address of the 21 ~elected segmentation register to be loaded or stored.
22 In the GPR, the key field in bit positions 5-7 is a stack 23 number which identifies the selected stack, and GPR bit 24 positions 0-4 contain a segmentation register number which identifies the selected SR which is to be loaded or stored.
26 The addressed word in main memory i8 located by a 27 logical address generated by using the RB field at bit 28 positions 8 and 9 that decignate a base register, and the 29 AM (access mode) field in bits 10 and 11 designate whether 1.0'~'71~

1 an AM word is to follow the instruction. The content~
2 of the AM word (if any) and of the R~ register are combined 3 to generate the effective address ~i.e. program apparent 4 address) of the main memory word which is to be either loaded or stored by execution of the instruction.
6 If the sy~tem i8 in translate mode, the generated effoctive 7 addres~ is inputted to the trznslator in FIGURES 9A and 9B
8 along with the AAK to comprise an input logical machine g address. The translator outputs the 24 bit phy~ical address for accessing the addreJsed memory word. Thu~
11 it is possible for the SR which is to be loaded to have 12 its content used in a translation operation beforo the 13 SR load instruction chanqes its content to a different 14 phy9ical block address.
If the processor i8 not in translate mode, the 16 generated effective address i8 the physical address in 17 main memory.
18 Bit~ 13 and 14 in the addressed word in main memory 19 contain the settings of the valid bit V and read-only bit R to be loaded into the SR to control its operation 21 whenever used for a reguested translation.
22 FIGURE 17 illustrates processor storage controls 23 used in executing the load/store segmentation register 24 instructions. These controls in the processor generate a segmentation register cycle which is u~ed by the 26 translator in FIGURES 9A and 9B to perform a SR load 27 or store. A load/store segmentation register instruction 28 acce~es microcode in the processor which generates a 29 L/S segmentation register request signal followed by a signal for a processor request for a storage cycle. The 10~7~;

1 first signal sets a SR re~uest next latch 481 in FIGURE 17, and second record signal is received by an AND gate 482 while it is being conditioned by the true (T) output of latch 481. A SR phase latch (PH) is set for a cycle by activation of AND gate 482 to activate AND gate 484 when the translator is installed. The output of AND gate 484 sets a SR request latch 486 to indicate that a segmentation register needs to be accessed. The true output (T) of latch 486 then enables an AND gate 488 to provide a SR
cycle, provided that no CS cycle request exists, since CS cycles get highest priority. The SR cycle gets second highest priority, and a normal processor storage cycle gets lowest priority by means of AND gate 493 that gener-ates a processor storage cycle signal on line 494 only when no SR request signal is inputted to it from the com-plement (C) output of latch 486. The other input of AND
gate 493 is connected to the true (T) output of the pro-cessor cycle latch.
When AND gate 488 is enabled by the true (T) output of latch 486 during the execution of a SR load or store instruction, its other input is receiving the true (T) output signal from a processor cycle latch 490 which is actuated whenever there is a storage cycle request by the processor. Thus, latch 490 is set by an output from an AND circuit 491 which has one input conditioned by a not cycle steal (CS) cycle signal (which occurs while there is no I/O storage access request pending). The other input of AND gate 491 is conditioned by the true output of a processor storage request latch 492 which is set whenever there is a processor request for a storage cycle.

10~71fi 1 During the existence of the SR cycle signal on line 923, the SR to be selected is addressed by the current address in the processor SAR. Then the SR selection opera-tion occurs in the manner described in the discussion of the translator in the section herein entitled "Segmenta-tion Register Selection".
As previously mentioned, whether a load or store op-eration occurs depends on the setting of the X bit in the instruction; to do this, the X bit selects a load or store microroutine from the processor ROS. For a SR load, the microroutine will first generate a processor storage re-quest during which the SR instruction addressed word in main memory is fetched and put into the processor SDR.
Then the microroutine issues the L/S SR request signal followed by another processor request for a storage cycle, which causes the circuit in FIGURE 17 to operate as ex-plained above to generate a SR cycle which selects the SR and causes the SDR content to be moved into the selected SR.
The store SR instruction operates similarly but with a reverse microroutine sequence. That is, it first actuates the circuit in FIGURE 17 to generate a SR cycle during which the SR is selected and its content moved into the SDR. Then the microroutine issues a normal processor stor-age request which causes the SDR content to be moved into the addressed location in the main memory.
IV.E.6. Look Ahead Translator Unit Controls The address translation operation uses one processor clock cycle of access time for selecting and reading out ~.09~7~

1 a segmentation register (SR), when generating the block address part of the physical address from bits 0-4 of the logical address. ~nother processor clock cycle of access time would be needed, if it were not for the look-ahead feature, for decoding the read-out block address, in order to select the interface bus to the required one of the memory units, i.e. inner store, outer store, or asynchronous store, to which the physical block address bus be transmitted. The lookahead feature eliminates the need for any extra time for selecting the required inter-face bus, and eliminates the need for decoding the read-out block address to determine the required storage unit.
Hence, it reduces the translated access time by a pro-cessor clock cycle. During the translation operation, the D bits in positions 5-15 of the logical address are being continuously provided on the main storage bus from the processor SAR, and hence the D bits do not add any extra time to the translation operation; they are simul-taneously applied to all three storage units.
The lookahead feature provides two bit positions labeled lookahead bits, with each segmentation register (SR) in each of the eight stacks in FIGURE 9A. Each SR
is constructed as shown in FIGURE 6. The lookahead two bits are generated and set into an SR at the time a block number is loaded into the segment register by the processor storage controls shown in FIGURE 17, which perform the operations shown in FIGURE 8A. The lookahead bits indi-cate which one on the inner, outer 10!~71~;

1 or asynchronous storage unit contains the block correspond-ing to the block number in the SR. After the lookahead bits are set and the SR's are loaded, the lookahead bits are used with each translated storage access to permit the required storage unit to be determined and selected in parallel with the hardware translation of the input logical address. The block number, but not the lookahead bits, are readable by a program using an SR store instruc-tion.
The lookahead bits are coded in the manner shown in FIGURE 9G. The left lookahead bit is set to 1 if the assigned block is in the inner storage unit. If the left bit is set to 0, the assigned block is in either the outer storage or asynchronous storage unit. The setting of the right lookahead bit indicates whether outer or asynchronous storage units contains the block. If the right bit is 0, the block is in the asynchronous storage unit.
The lookahead bits are used only by the hardware and are not seen by the programmer or system user. They exist only for the purpose of speeding up the memory access and are not part of the translation operation.
The hardware for setting the lookahead bits is found in FIGURE 9C. It includes decoders 901 and 902, both of which receive the high order portion of the assigned block number being loaded into an SR by execution of a segment register instruction in the 10'~71~;

1 manner described for FIGURE 8A. The selected SR is in one of the stacks 0-7 in FIGURE 9C. The block number is provided by the load segmentation register instruction, which accesses the program assigned block number from the storage word in main memory addressed by the instruc-tion, which block number is put into the SDR in FIGURE 4.
Then the processor provides the assigned block number from the SDR to the processor data bus, which in FIGURE 3C con-nects to the storage data bus to storage in FIGURE 9A
which provides the SR input to be loaded into any address-ed segment register in stacks 0-7. The SR load path is shown in detail in FIGURE 9C in which the SR input lines 00-07 are used to generate the lookahead bit signals.
Lines 00-06 are connected to the input of the all zeros decoder 902, and lines 00-07 are connected to the input of the all-zeros decoder 901. Each all-zeros decoder will output a 1 state lookahead signal if it receives all zeros, and it outputs a 0-state signal if any input is a one. Thus, if decoder 901 senses all zeros in bit positions 00-07, it outputs a 1 bit into the left-most lookahead bit position for the addressed SR in the stacks;
but if any of input bits 0-7 contain a 1, then the left-most lookahead bit is set to 0. Decoder 901 indicates if the physical block whose address is being loaded is located in the inner storage unit or not, which deter-mines if an ISC signal is to be provided.

10~ 71~i 1 If decoder 902 senses all zeroes in SR input bit positions 0-6, then the right lookahead bit of the addressed SR is set to one. Ihe rational is that if the let lookahead bit indicates that the inner storage unit is not the pertinent unit, and if bits 0-6 are all zeros, then decoder 902 indicates whether or not a 1 bit exists in bit position 7 of the physical address to be loaded, which indicates whether the assigned block is in the outer storage unit, or is in the asynchronous stor-age unit.
Accordingly, any SR being loaded has its lookahead bits set to indicate the particular storage unit contain-ing its assigned block.
The SR load operation occurs during an SR cycle, which is signalled on line 923 to funnel 922 in FIGURE 9A
from the basic controls shown in detail in FIGURE 9D-2.
The stack address is inputted to funnel 922 on lines 05-07 of the storage address bus 901 in FIGURE 9A.
The SR register address is provided on lines 00-04 of the storage address bus 901 through the PH register to the SR stacks 0-7 in FIGURE 9A. These address signals are put on lines 00-07 of storage address bus 901 from FIGURE 3C which receives the processor address bus from the SAR in FIGURE 4. The SAR receives its content from the GPR selected by the load SR instruction in FIGURE 8A, in which GPR bits 0-7 are the SR address bits on lines 00-07 of 1.0~ 71~

1 bus 901. (The GPR i9 selected in level stack 431 2 in FIGURE 4 by a level ~tack address developed from 3 the GPR field in the load SR instruction.) 4 Funnel 922 then outputs the stack address of the selected SR on its output lines, AAK bit 2, AAK bit 1, 6 and SR hi-lo select line 935. Line 935 provides an 7 input to ba~ic controls in FIGURE 9~. These circuit~
~ are shown in detail in FIGURE 9D-2, which generate the g dignals on lines 932 and 933 which are connected to the segmentation register 6tacks 0-7 as the lowest-order 11 ~tack address bit, which also corresponds to the true 12 and complement form of the signal on line 07 of 13 storage address bus 901. The signals on the AAK
14 bit 1 lines correspond to the true and complement form of the signals on bus line 06; and the signal 16 on the AAK bit 2 line corresponds to the signal on 17 bu8 line 05.
18 On a memory access in translate mode, a stack 19 register is selected by the same type of funneling described in the section entitled "Segmentation 21 Register Selection". The funnel selected SRs each 22 have their two lookahead bits read out at the same 23 time that their other 16 bits are read out. The 24 lookahead bits u~e the ~eparate funnel 931 because it operates faster than the wider funnel 921 which 26 selects the block address bits for the same SR. The 27 output of 931 i8 a selected one of three output lines 28 which signal a selected storage cycle, an ISC, OSC or 29 ASC. The processor use6 the ISC signal lines 54A from 10.'..~

1 the proceqsor through the storage priority ~elect 2 circuit~ 56 ~o the inner storage unit 51 in FIGURE lC.
3 Since lines 54A exist whether or not the ~y~tem h~ a 4 translator, the inner storage cycle control line of funnel 931 is connected to the proces~or to actuat-6 an ISC addressing operation. The outer storage cycle 7 and asynchronous storage cycle lines go to FIGURES 9E
8 and 9F-l, re-pectively, to control the addro~s 9 selection in thelr respective unit~.
IV.F. Equate Operand Spaces Feature 11 A feature is provided called the equate operand 12 spaces (EOS) feature which provides a state that is 13 set into the AKR to control a ~pecial addressability 14 condition, in which all operand fetches are forced to occur within the OP2K address space, and the addros~
16 space defined by the OPlK address key is ignored even 17 though *he key in the OPlK register section of the AXR
18 is not changed.
19 The EOS state of the system is enabled by the enable instruction shown in FIGURE 13A when its EOS bit 21 13 is set. When thi~ instruction is executed, the 22 set EOS bit causes the EOS regi~ter section in the 23 respective AKR to be correspondingly set by being 24 ingated from the processor ROS decoder in FIGURE 4. None of the key settings in the AKR is changed when the EOS
26 state i~ activated. However, the address space defined 27 in the OPlK section will not be accessed as long as the 28 EOS state is on in the AKR. The hardware arrangement 29 in FIGURE 3D implements the EOS feature, in which 10~

1 activation of the EOS line from the AKR force~ the 2 AAX to output the OP2K key whenever there i8 an access 3 request for either an OPl or OP2 operand cau~ed by 4 by the execution of an instruction in the processor.
Whenever the EOS state i8 disabled by execution of a 6 disable instruction having it~ EOS bit 13 set off, the key 7 value in the OPlK register section becomes operatlonal again 8 and i8 accessed by any OPl operand request.
9 IV.G. Addre~ Space Management By Key Settings in AXR
When the EOS feature is disabled, the function of the 11 three address keys in the AKR is as follows:
12 Each address key loaded in the AKR defines an accessable 13 address space. Each address space is a range of logically 14 continuous storage accessable by the effective logical addre~s without inter~ention by any programmed resource 16 management function. Each logical address space contains 17 up to 64K bytes. All instruction fetches will occur 18 within the address space defined by the ISK. All reads 19 concerning data operand 1 (as defined in the storage-to-~torage instruction architecture) will occur in the 21 address space defined by the OPlX. (~y architectural 22 definition, no writes occur for operandl.) Likewise, 23 all reads and writes concerning data operand 2 (as 24 defined in each instruction's architecture) will occur in the address space defined by the OP2K.
26 For example, if ISK=OPlK=OP2K, the machine will execute 27 with all storage accesses within the ame addre~s 64K
28 logical address space. If ISK is not equal to OPlK but 29 OPlK=OP2K, the machine will operate with instruction fetche~ occurring in the ISK addres~ space and data ~C9-76- 006 ~0~ 7 1~i 1 accesses occurring in the OP2 address space. If ISX
2 ~OPlK~OP2K, then instruction fetch occurs in the ISK
3 Addre~s space, each operand 1 fetch occurs in the OPlK
4 space, and each operand 2 fetch or store occurs in the OP2K addres~ Qpace, wherein the three spaces are different.
6 The data flow for classes of instruction in which three 7 address spaces are different is illustrated in FIGURE 2A.
8 The values of the keys in the AKR can only be set g when the processor is in supervisor mode, i.e. the load AKR in8tructions are privileged.
11 IV.H. AKR Loading Under Interrupt Conditions 12 When interrupts occur to the proce~sor, the values 13 Of the address keys in the AKR are set in anticipation 14 of addre s spaces which may be required by the interrupt handling programming support. There are a plurality of 16 different types of interrupts in the system, each of 17 which ~ay have its special programming support which may 18 require a particular loading of address keys. Processor 19 interrupts include supervisor call interrupts, I/O device interrupts, machine check/program check interrupts, program 21 trace interrupts, console interrupts and power thermal 22 warning interrupts. These processor interrupts are some-23 time8 called class interrupts.
24 All interrupt routines are presumed to reside in the address space with key=O; therefore, the ISK must 26 be loaded with O when an interrupt occurs. Since operand 27 data necessary for handling a specific interrupt may 28 reside in another address space, the address key relevant 29 to the particular interrupt data may be loaded into the OPlK register section. The time when the OPlK key is 109 ~

1 set i8 when a cla58 interrupt occurs (i.e. input~ to 2 the forced addres~ing circuit 402 in FIGURE 4) in 3 anticipation of performing a storage-to-storage move 4 of relative information from the interrupting addre~s space (i.e. OPlX ~pace) to OP2K address space with 6 key~O. For example, when a class interrupt occurs, a 7 level statuQ block (LSB) is stored into the OP2X ~pace 8 having key=O (i.e. OP2X~O) using fetches of data from g the OPlK space. The AKR content is also stored into the LSB with a store AKR instruction.
11 Other circum~tances in which all key values in the 12 AXR are set to zero are: system reset, and initial program 13 load, during which the EOS, translator, and storage 14 protect features are all disabled.-IV.H.l. SVC Interrupt 16 The SVC interrupt operations discussed below 17 as~ume that the supervisor programs are in the key~O
18 address.space and that the user program iB in some other 19 address space, i.e. key~O. It is also assumed that a communication of data is required between the user and 21 the supervisor. The data must be obtained from the u~er's 22 addres~ space to the supervisor's address space, and23 transferred back to the user's address space.
24 FIGURE 13B illu~trates loading operations for the AKR under a supervisor call (SVC) interrupt condition.
26 It is assumed during the initial user state that each of the 27 three user keys is set to a key value of 2, and that the 28 EOS field is set to zero. When a supervisor call instruction 29 is executed in the processor of FIGURE 4, forced address 1~3 ~'7~ ~

1 circuit causes a sequence of ROS words to be fetched nnd 2 executed which causes the proces~or to be put in 3 supervi~ory state. A1BO an LSB is stored, the contents 4 of OP2K are outgated to the contents of OPlX, providing addressability to the ~dr~ss space having the data 6 involved in the generatlon of the interrupt, and the 7 outgate zero (OG O) line from the processor ROS decoder 8 i8 activated to the processor data path and ingated into g the OP2R and ISK po6itions of the AXR.
Data iB passed from the user area to the supervisor 11 area, then the enable instruction in FIGURE 13A with it~
12 bit 13 on is executed to provide EOS state 4 ~hown in 13 FIGURE 13~. This causes all storage accesses to occur 14 in the address space having key O while the ~up~rvi~or program is being executed in the EOS state, without 16 losing the addressability to the OPlK address space.
17 Whenever the supervisor wishes to transfer information 18 into the OPlK area, the processor issues a disable 19 instruction which effectively resets the EOS section Of the AKR; and t~is restores addressability to the 21 OPlK space. Then state 6 in FIGURE 13B is provided by 22 interchanging the OPlK and OP2K field~ in order for the 23 supervisor to obtain store addressability to the OPlK
24 area. The supervisor may then pass the data from the supervisor area to the u~er area. Then the AKR is 26 returned to the user state 7 in FIGURE 13B by loading Z7 the initial AKR state from the LSB.
28 FIGURE 18 illustrates the operations which occur 29 whenever an SVC instruction i9 issued. These operations BC9-76~006 10!~716 1 include saving the old content and loading a new con-tent into the AKR as followsf in which the following numbered paragraphs correspond to the circle numbered paths in FIGURE 18. The processor execution of the SVC
instruction preceeds as follows:
(1) At the beginning of execution of the SVC
instruction, the AKR content is gated to the work area register (WAR) via the processor data path bus by actuation of the OG AKR sig-nal and IG WAR signal from the ROS decoder.
This operation is indicated by the move of the AKR content into the TEMPA in FIGURE 18, OPlK, OP2K and ISK are each assumed to have been set to key=3.
(2) Outgate OP2K and ingate OPlK.
(3) Set OP2K=ISK=0.
(4) The content of the LSR (level status register)is stored in the temporary register ~TEMPB').
(5) In the LSR', its supervisor state bit is en-abled, its summary mask bit is disabled and its trace bit is disabled.
(6) The IAR (instruction address register) is then incremented by two, which causes the IAR to address the next storage location, which lo-cates the beginning of the data or a pointer to the data.
(7) The processor detection of the SVC causes stor-age address location 0010 in address space key=0 to be fetched. This space is 109~71~;

1 predefined to include an addre~s (i.e. pointer) to a level storage block, i.e., LSB, al50 in the key=0 address space.
(8) The LSB pointer in location 0010 is moved into the SAR in FIGURE 4.
(9) At the LSB storage location addressed by the SAR, the IAR, TEMPA, TEMPB, and general pur-pose registers 0-7 are stored into the level status block (LSB).
(10) The SVC number (identifying the particùlar type of SVC instruction) is copied into Rl from the SVC instruction in address space 3.
(11) The content of storage location 0012 is moved into the IAR.
(12) Execution begins for the supervisor routine addressed from location 0012. This is the routine called for by SVC number 2.
The resulting AKR load state at the start of the SVC
routine is:
OPlK OP2K ISK
OP2K' 0 0 (Note: OP2K' is pre-vious OP2K content.) The other class interrupts will have a similar type of operation with a resulting load state of the AKR, which is as follows:
IV.H.2. Device Interrupt:
(1) Reset trace, disable EOS, and set supervisor states.
(2) Set ISK = OPlK = OP2K = 0 10~71~

1 (3) Put the address of a device data block into Register 1.
(4) Put in Register 7 the interrupt ID word re-ceived from the interrupting I/O device.
The resulting AKR load state is:
OPlK OP2K ISK
O O O
IV.H.3. Machine Check, and Program Check/Soft Exception Interrupts;
(1) Reset trace, disable summary mask, disable EOS, and set supervisor states. Store LSB in key 0 address space.
(2) Set ISK = OPK2 = 0 ~3) Store in OPlK the LSKA.
(4) Store content of SAR in Register 7 (except for trace).
The resulting AKR load state is:
OPlK OP2K ISK
LKSA 0 0 (Note: LKSA is last key in register 408 in FIGURE 4 when an interrupt occured.) IV.H.4. Console Interrupt/Power Thermal Warning Interrupt:
(1) Reset trace, disable summary mask, disable EOS, and set supervisor states.
(2) Store LSB using Address key 0.
(3) Set ISK = OPlK = OP2K = 0.
-The resulting AKR load state is:
OPlK OP2K ISK

10~ '~71~;

1 IV.H.5. Trace Interrupts;
(1) Reset trace, disable summary mask, disable EOS, and set supervisor states. Store LSB in key 0 address space.
(2) Transfer ISK into OPlK.
(3) Set OP2K=ISK=0.
The resulting AKR load state is:
OPlK OP2K ISK
ISK' 0 0 (Note: ISK' is the ISK
at time of interrupt.) V. Non-Translation Storage Protection Circuits The non-translation storage (NTS) protection control circuits shown in FIGURE 11 are used when the relocation translator shown in FIGURES 9A and 9B is either not enabled or is not installed in the system. This invention provides an upward compatibility relationship between the translator address-key protect feature and the non-translatable storage protect feature. That is, programs and data used in a system operating with the NTS protect feature can be used without change on a machine having the relocation translator. This migration relationship between the two types of protection circuits is very important to system users who wish to begin with a relatively small storage system that is inexpensive and later grow to a larger system having an extended memory.
When the relocation translator is enabled, the NTS
protection is enabled, the relocation translator 109~71.~i 1 is disabled. The state of the NTS protection feature is controlled by the enable/disable instructions shown in FIGURE 13A.
The NTS protection circuits provide against undesired access of a main memory location by either a processor or an I/O operation using an untranslated address. With the NTS protect feature, the main memory is divided into 2K
blocks of 2048 bytes. Each block of main memory is pro-vided with a storage key register in a stack 401 in FIGURE 11. Each register is associated with a predeter-mined block in the inner storage unit selected by the high-order five bits in a 16 bit physical address, which is the program apparent address directly generated by a program executing on a system. With the NTS protect fea-ture, the program apparent address is the physical address;
but when the translator is enabled, the program apparent address is part of an input logical address. Each regis-ter has at least 3 bit positions for an assigned storage key and a read only bit R, and it may also have a valid bit V (not shown). The three bit storage key have bit positions 0, 1 and 2 which may be loaded by conventional load storage key instructions, e.g. like in the IBM
System/360 system.
A comparator part of the NTS protect circuit opera-tion is similar to the storage key protect circuit opera-tion performed on conventional systems .10~ 71~

1 such as an IBM S/360 or S/370. However, the other coopera-tive parts of the NTS protect feature provide an inventive arrangement in this specification including its combina-tion with the unique AAK select circuits 333 in EIGURE 3D.
The comparator operation uses the high-order bits 0-4 in the 16 bit physical address to index the stack register associated with the inner storage block. The storage key in the indexed register is accessed. The AAK is then com-pared with the stack selected storage key in the compare equal circuit 402 in FIGURE 11. If they compare equal, the access is allowed, provided the NTS protect feature is enabled and the access is a fetch or it is a write and read only bit which is off. Accordingly, the NTS protect feature provides access type protection, e.g. it can pro-vide separate protection for OPlK, OP2K, ISK address spaces in a non-translated environment.
Further unique features of the NTS protect circuits are in its control of shared storage areas, defined by a particular key value, and of accesses by the I/O subchan-nels. The user has access to the particular key areasdefined for the user in the AKR in the processor, and all users may use key=7 in any register section of the AKR to define a common access area shared by the users. Cir-cuit 405 controls the accesses to the shared areas.
The unique I/O operation access control in the NTS
protect mode is provided by circuits 404 and 405, iO~'~71~i 1 which permit any I/0 cycle steal acces~ reque~t to be 2 made in the key area defined in his AXR, or in tho 3 common ~torage area having key~7. without any I/0 4 cycle steal access being inhibited by the read only bit in the accesAed storage key register. Thu~, an 6 I/0 write access i~ permitted regardle~s of the 7 setting of the read-only bit in the selected reglstor B in stack 401.
g If the processor iB in supervisory state, i.e.
bit 8 is set in the LSR in FIGURE 4, the ~torage key 11 protect controls are bypassed and all acce~se~ are 12 allowed into any block in main store.
13 In summary, the address space control provided by 14 the AKR is ueed whether the NTS protect feature iB enablea or whether the optional translator feature is used.
16 Accordingly the AAK will be a CS key or a ~ey in the AXR
17 ~elected by execution of each processor instruct~on a-18 determined by the type of operand being fetched or by 19 an instruction i8 being fetched.
When the NTS protect feature is enabled, one or 21 more of the following conditions must be true to authorize 22 an attempt of access storage.
23 (1) The machine i6 in supervisory state.
24 (2) The storage key of the address block is 7.
If attempting to write storage, the read 26 read only bit must be off (e.g. zero).
27 (3) The storage key of the addre~s block must equal 28 the AAK. If attempting to write storage, the 29 read only bit must be off.

10~'71~i 1 If none of the above conditions (1), (2) or (3) is obtained, the output of inverter 407 in EIGURE 11 provides a storage access suppression signal which generates a pro-gram check (PCK) interrupt that will set the corresponding bit in the processor state word register.
Therefore, the supervisory state has free access to all of main memory. An access to a storage area having a storage protect key of 7 is permitted regardless of the AAK
value or the values in the AKR when the system is not in supervisory state, providing that the read only bit for the accessed block is not violated.
It is therefore apparent that within any single addressable area defined by an address key, some blocks of that area can be maintained in a read only state and other blocks of the area made writeable by setting or not setting the read only bit for the blocks in the addressable area. The read only bit can be set by the supervisory pro-gram which loads the stack registers.
During initial program load (IPL), the NTS protect feature and translator feature are both disabled so that the main memory can be written into at any location during the initial loading process. Upon the successful comp]e-tion of IPL, either protect feature can be enabled, and the machine enters the supervisor state with all address keys in the AKR being set to zero.
In addition to the common AAK features between the NTS protect feature and translator feature, they 10'~'71~i 1 have a number of features which are dissimilar such as:
(1) With the NTS protect feature, the supervisory state will allow access to all of main memory irrespective of the storage keys. In a trans-lator system, the supervisory state may only access the memory area defined by the AAK.
(2) The total storage defined by the address keys on a NTS protect system is less than or equal to 64X bytes. The total static storage defin-able by the address keys on a translator system may be up to 512K bytes at any instant of time.
(3) On a translator system, the address space de-fined by the address keys starts at logical address zero. On an NTS protect system, the address space defined by the address keys will start on various 2X byte boundaries, but the address key still provides access-type control.
(4) The instructions used to load and store the storage key registers in the processor are dif-ferent from the instructions used to load and store segmentation registers in the translator.
(5) An I/O device on a translator enabled systemcan not receive protect checks; however, an I/O
device on an NTS protect enabled system can receive a protect check for an access at an address which is not in the CS key defined area or key=7 area.

10~ '71~

1 (6~ Due to the address mapplng feature flexibility 2 on the translator, certain mappings from logical 3 to physical address space are difficult to 4 emulate in the NTS protect mode, e.g. a common are~ exclu~ive to only two ~ddres~ key~.
6 VI. Alternate Translate Protect Mode 7 FIGURE 14 illustrates control circuit~ for an 8 alternate translate protect mode (APM) usable in a data 9 processing system. The APM mode is alternative to the previou~ly described translate mode using the plural 11 sectioned AKR in FIGURE lD. The alternate mode does not 12 provide the storage-access-type controlled processor 13 addressability obtained with FIGURE lD, but it permit~
14 separate addres~ability for I/0 storage accesses. The alternate mode does provide AAK addressability discrimination 16 for the processor among its different programs and data 17 having different u~er address keys, while also permitting 18 user interaction with supervisory program operations, 19 whenever necessary, without having to change the content of a user key register (UKR) 460.
21 In FIGURE 14 only a single address key is loadable 22 into the processor's UKR register 460, 80 that all 23 storage accesses for executing user program(s) and 24 data must be done within the single addressability defined by the user key value in UKR 460, which is 26 a non-zero key value, since the zero key value is 27 reserved for the memory area containing the system 28 supervisor programs and data. I/0 accesses are 29 controlled by the CS key loadable by a subchannel into a CS key register 465.

10'~'71~i 1 The APM mode iY controlled for a processor by 2 a bit position A in the level statuq regi~ter (LSR) 470.
3 When the supervisor state is on, bit S is set; and 4 when the APM mode is on, bit A is set.
When both bits S and A are set, a first type of 6 processor operation is provided ! in which interaction 7 i8 enabled for a supervisor program (contained in 8 the key=0 area~ with the current user key area g (identified by the current user key in UKR 460). That is, the supervisor program is permitted to execute 11 from the key=0 area and access operands in the user 12 address key area. However the supervisor can not access 13 other addressabilities in main memory defined by other 14 key values, This supervisor interaction with restricted addressability, for example, enables its interrupt 16 handling programs to access a currently interrupted u~er 17 program and data without the danger of the supervisor 18 program di~turbing the integrity of non-pertinent areas 19 of main memory if something goes wrong in the supervisor operation. Also any executing user program is never 21 permitted to access the supervisor memory area, becau~e 22 any user program only has addressability to the user's 23 own area, identified by the user's key.
24 A second type of processor operation occurs when the supervisor bit S is on and the APM bit A is off. Then 26 the supervisory program can operate from the key=0 area 27 without disturbing the current user key in ~KR 460. In 28 this case, all I-fetches and operand accesses can only 10~ 71~

1 be made in the key=O area, with no supervisor inter-2 action permitted with any user area. That i8, the 3 supervisor then has no access to the u~er key area 4 identified by the current content of UKR 460, or ~o any other key area. This special type of system operation 6 eliminates the need to load and reload key=O into 7 UKR 460.
8 A third type of processor operation i~ provided 9 when the supervisor bit S is off, regardless of the state of APM bit A. In this case, all instruction fetche~ and 11 operand acce~ses can only be in the user key area. That 12 is, no accesse~ are permitted into the key=O area of 13 main memory.
14 The APM mode is controlled in the processor by the hardware shown in FIGURE 14. An AND gate 462 is 16 enabled by setting on both the S and A bits in LSR 470 17 to provide the first type of processor operation 18 defined above. Then gate 462 is actuated by each 19 I-fetch request from the processor in FIGURE 4 to provide an output through OR circuit 466 and an inverter 21 467 to disable AND circuit 461 during the instruction 22 fetch operation. While AND circuit 461 is disabled, it 23 provides an all-zeros output signal representing key=O
24 to the AAK bus. Thus, the I-fetch is only allowed in the supervisor key=O area.
26 When there is no I-fetch request, such as between 27 I-fetch requests, AND gate 462 is not actuated and 28` inverter 467 provides an enabling signal to AND gate ~0~71~

1 461 to output the u~er address key in UKR 460 to 2 the AAK bus, so that a fetched executing supervisory 3 program instruction can access operands in the user 4 key area being addressed by the key in UKR 460.
If the APM bit A i8 off while the supervisor ~6 bit S is on in the LSR, AN~ gate 464 is continuously 7 enablèd to continuou~ly disable AND gste 461 via inverter 8 467, ~o that gate 461 continuously outputs koy-0 to 9 the AAK bus. This provides the second type of processor operation described above, in which only 11 the supervisor program can operate with all operand 12 and I-fetches restricted to the key=0 area, regardless 13 of the user key in AKR 460.
14 If the S bit is off in LSR 470, AND gates 462 and 464 are continuously disabled 80 that inverter 16 467 provides a continuously enabling output to AND
17 gate 461, which then continuously passes the user 18 address key to the AAK bus. This provides the 19 third type of processor operation defined above, and causes all storage accesses for both the processor and 21 I/0 to be in the main memory area addressed by the user 22 key in UKR 460. The supervisor cannot operate, until bit 23 S i8 set on.

Claims (12)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as fol-lows:
1. A protected storage system having a processor using a plurality of storage protect keys, the processors including storage access sensing means in the processor for sensing different types of machine-identifiable storage requests, including means for sensing instruction access requests for generating an instruction access type signal, and means for sensing operand access requests for generat-ing at least one type of operand access signal, a plurality of key register sections respectively corresponding to the access types of machine-identifiable storage requests sensed by the storage access sensing means, key selection means actuated by each access type sensed by the storage access sensing means for outputting a cor-responding key register section, whereby the outputted con-tent of the corresponding key register section contains a key for protecting a corresponding storage area in the protected storage system containing the information required by the corresponding storage request.
2. A protected storage system as defined in Claim 1, in which the operand access request sensing means includes means for sensing plural access types of operands, and means for generating respective operand-type access signals for indicating respective access types of operands sensed by said operand access-type sensing means, a key register section corresponding to each respective access type of operand, the key selection means receiving at least some of the operand access type signals and selecting a key register section that corresponds to the operand access type sensed by the sensing means.
3. A protected storage system as defined in Claim 2 for being operated by execution of storage-to-storage type instructions, in which an execution unit of the processor includes the operand-type access request sensing means, which further comprises first means for sensing a fetch-only type of storage operand field in an instruction and generating a first-operand type access request signal, second means for sensing a fetch or store type of operand field in an instruction and generating a second-operand type access request signal.
CLAIMS 2 and 3 4. A protected storage system as defined in Claim 1, further comprising an I/O key register section in each subchannel for receiving a key provided by a program, storage access request sensing means with each subchannel for sensing an I/O type access signal for an I/O storage access request by the subchannel, priority selection means for receiving I/O
storage access request signals from the I/O sub-channels, and for receiving instruction and operand access type request signals from at least one processor, the priority selection means granting memory access priority to simultaneously received request signals in a predetermined order to initiate memory access operations, the key selection means connected to the output of the priority selection means for selecting the output of each key register section having a corres-ponding access-type request signal granted memory access priority by the priority selection means.
CLAIM 4
5. A protected storage system as defined in Claim 4, further comprising means for outputting the key content of any I/O key register upon its subchannel providing a cycle-steal storage access request signal, the priority selection means granting highest priority to the cycle-steal storage access request signal, the key selection means passing the key content being outputted from an I/O register for controlling the address-ing of the storage system to provide address protection for an I/O buffer area in the storage system.
6. A protected storage system having a processor using a plurality of storage protect keys, the processor com-prising storage access sensing means in the processor for sensing different types of machine-identifiable storage requests, including means for sensing instructions access requests for generating an instruction access type signal, and means for sensing operand access requests for generat-ing at least one type of operand access signal, a plurality of key register sections respectively corresponding to the access types of machine-identifiable storage requests sensed by the storage access sensing means, key selection means actuated by each access type sensed by the storage access sensing means for outputting a key in a corresponding key register section, means for storing relocatable addresses corresponding to storage areas assigned to respective keys, and means for selecting one of the means for storing relocatable addresses in response to a key outputted from a selected key register section, whereby the outputted key uniquely selects a cor-responding storage area in the protected storage system for fetching or storing the instruction or operand required by a corresponding request for storage access.
7. A protected storage system as defined in claim 6, in which the means for sensing operand access requests in-cludes means for sensing plural types of operand accesses, whereby each operand access type is associated with a different key register section in the processor.
8. A protected storage system as defined in claim 7 for being operated by execution of storage-to-storage type instructions, which further comprises first means for sensing a fetch-only type of storage operand field in an instruction and generating a first-operand type access request signal, second means for sensing a fetch-or-store type of operand field in an instruction and generating a second-operand type access request signal, whereby the first-operand and second-operand type access request signals respectively outgate different key register sections.
9. A protected storage system as defined in claim 6, further comprising a channel having a plurality of subchannels, an I/O key register section in each subchannel for receiving a key provided by a program, each sub-channel being a data path connecting an I/O control unit to the protected storage system, storage access request sensing means with each sub-channel for sensing an I/O type access signal for an I/O
storage access request by the subchannel, priority selection means for receiving I/O storage access request signals from the I/O subchannels, and for receiving instruction and operand access type request sig-nals from at leat one processor, the priority selection means granting memory access priority to simultaneously received request signals in a predetermined order to initiate memory access operations, the key selection means connected to the output of the priority selection means for selecting the output of each key register section having a corresponding access-type request signal granted memory access priority by the priority selection means.
10. A protected storage system as defined in claim 8, further comprising means for outputting the key in any I/O key register when its subchannel provides a cycle-steal storage access request signal, the priority selection means granting highest priority to the cycle-steal storage access request signal, the key selection means passing the key content being outputted from an I/O register for controlling the address-ing of the storage system to provide address protection for an 1/0 buffer area in the storage system.
11. A protected storage system as defined in Claim 9 or Claim 10, in which a plurality of I/O devices are connected to the processor through a plurality of chan-nels, further comprising storage access request means in each subchannel for generating an I/O access-type of signal for requesting an I/O storage access request for each subchannel, the priority selection means actuating the key selection means in response to the I/O access type of request signal to select an I/O key register section with the I/O subchannel for outgating the key contained therein for protecting a storage area assigned to the respective I/O device subchannel.
12. A protected storage system as defined in Claim 9 or claim 10 in a computer system having a plurality of chan-nels, in which the priority selection means further comprises means for receiving storage access request signals from all of the channels and granting priority on a chan-nel priority bus to the channel access request signals in a predetermined priority, a channel selection circuit for gating a key content currently being provided by a selected channel to an input of the key selection means, and the key selection means passing the key content of each selected channel.
CA275,572A 1976-04-30 1977-04-05 Key register controlled accessing system Expired CA1092716A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/681,984 US4037214A (en) 1976-04-30 1976-04-30 Key register controlled accessing system
US681,984 1976-04-30

Publications (1)

Publication Number Publication Date
CA1092716A true CA1092716A (en) 1980-12-30

Family

ID=24737703

Family Applications (1)

Application Number Title Priority Date Filing Date
CA275,572A Expired CA1092716A (en) 1976-04-30 1977-04-05 Key register controlled accessing system

Country Status (10)

Country Link
US (1) US4037214A (en)
JP (1) JPS52132738A (en)
AT (1) AT375204B (en)
AU (1) AU508001B2 (en)
BR (1) BR7702822A (en)
CA (1) CA1092716A (en)
DE (1) DE2716051C2 (en)
FR (1) FR2349918A1 (en)
GB (1) GB1557122A (en)
SE (1) SE417551B (en)

Families Citing this family (135)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4162529A (en) * 1975-12-04 1979-07-24 Tokyo Shibaura Electric Co., Ltd. Interruption control system in a multiprocessing system
US4037207A (en) * 1976-04-30 1977-07-19 International Business Machines Corporation System for controlling address keys under interrupt conditions
US4340932A (en) * 1978-05-17 1982-07-20 Harris Corporation Dual mapping memory expansion unit
US4246638A (en) * 1978-09-14 1981-01-20 Thomas William J Method and apparatus for controlling usage of a programmable computing machine
JPS55119745A (en) * 1979-03-07 1980-09-13 Hitachi Ltd Information processing unit
US4408292A (en) * 1979-09-27 1983-10-04 Sharp Kabushiki Kaisha Data print control in an electronic cash register
US4328542A (en) * 1979-11-07 1982-05-04 The Boeing Company Secure implementation of transition machine computer
US4355355A (en) * 1980-03-19 1982-10-19 International Business Machines Corp. Address generating mechanism for multiple virtual spaces
US4500952A (en) * 1980-05-23 1985-02-19 International Business Machines Corporation Mechanism for control of address translation by a program using a plurality of translation tables
US4434502A (en) 1981-04-03 1984-02-28 Nippon Electric Co., Ltd. Memory system handling a plurality of bits as a unit to be processed
JPS593774A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Access processing system
JPS5958700A (en) * 1982-09-29 1984-04-04 Fujitsu Ltd Memory protection judge method
US4500961A (en) * 1983-06-03 1985-02-19 Motorola, Inc. Page mode memory system
US4589092A (en) * 1983-12-12 1986-05-13 International Business Machines Corporation Data buffer having separate lock bit storage array
US4709326A (en) * 1984-06-29 1987-11-24 International Business Machines Corporation General locking/synchronization facility with canonical states and mapping of processors
US4777588A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance
US4682283A (en) * 1986-02-06 1987-07-21 Rockwell International Corporation Address range comparison system using multiplexer for detection of range identifier bits stored in dedicated RAM's
JPS6376034A (en) * 1986-09-19 1988-04-06 Hitachi Ltd Multiple address space control system
US5361341A (en) * 1987-10-02 1994-11-01 Sgs-Thomson Microelectronics, S.A. Device for enabling the use of the contents of memory areas of an electronic microprocessor system
US4945480A (en) * 1988-02-10 1990-07-31 International Business Machines Corporation Data domain switching on program address space switching and return
US5023773A (en) * 1988-02-10 1991-06-11 International Business Machines Corporation Authorization for selective program access to data in multiple address spaces
US4979098A (en) * 1988-02-10 1990-12-18 International Business Machines Corporation Multiple address space token designation, protection controls, designation translation and lookaside
US5220669A (en) * 1988-02-10 1993-06-15 International Business Machines Corporation Linkage mechanism for program isolation
US5247647A (en) * 1988-07-28 1993-09-21 International Business Machines Corp. Detection of deletion of stored data by concurrently executing processes in a multiprocessing data processing system
US5390310A (en) * 1991-09-30 1995-02-14 Apple Computer, Inc. Memory management unit having cross-domain control
US5627987A (en) * 1991-11-29 1997-05-06 Kabushiki Kaisha Toshiba Memory management and protection system for virtual memory in computer system
US5548746A (en) * 1993-11-12 1996-08-20 International Business Machines Corporation Non-contiguous mapping of I/O addresses to use page protection of a process
FR2728363A1 (en) * 1994-12-20 1996-06-21 Sgs Thomson Microelectronics DEVICE FOR PROTECTING ACCESS TO MEMORY WORDS
US5724551A (en) * 1996-05-23 1998-03-03 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries include storage keys for controlling accesses to the buffers
US6807620B1 (en) * 2000-02-11 2004-10-19 Sony Computer Entertainment Inc. Game system with graphics processor
US6934817B2 (en) 2000-03-31 2005-08-23 Intel Corporation Controlling access to multiple memory zones in an isolated execution environment
US6760441B1 (en) 2000-03-31 2004-07-06 Intel Corporation Generating a key hieararchy for use in an isolated execution environment
US7013484B1 (en) 2000-03-31 2006-03-14 Intel Corporation Managing a secure environment using a chipset in isolated execution mode
US7194634B2 (en) 2000-03-31 2007-03-20 Intel Corporation Attestation key memory device and bus
US6996710B1 (en) 2000-03-31 2006-02-07 Intel Corporation Platform and method for issuing and certifying a hardware-protected attestation key
US6769058B1 (en) 2000-03-31 2004-07-27 Intel Corporation Resetting a processor in an isolated execution environment
US6507904B1 (en) 2000-03-31 2003-01-14 Intel Corporation Executing isolated mode instructions in a secure system running in privilege rings
US7356817B1 (en) 2000-03-31 2008-04-08 Intel Corporation Real-time scheduling of virtual machines
US6678825B1 (en) 2000-03-31 2004-01-13 Intel Corporation Controlling access to multiple isolated memories in an isolated execution environment
US7073071B1 (en) 2000-03-31 2006-07-04 Intel Corporation Platform and method for generating and utilizing a protected audit log
US6957332B1 (en) 2000-03-31 2005-10-18 Intel Corporation Managing a secure platform using a hierarchical executive architecture in isolated execution mode
US6990579B1 (en) 2000-03-31 2006-01-24 Intel Corporation Platform and method for remote attestation of a platform
US6795905B1 (en) 2000-03-31 2004-09-21 Intel Corporation Controlling accesses to isolated memory using a memory controller for isolated execution
US7082615B1 (en) 2000-03-31 2006-07-25 Intel Corporation Protecting software environment in isolated execution
US7013481B1 (en) 2000-03-31 2006-03-14 Intel Corporation Attestation key memory device and bus
US6754815B1 (en) 2000-03-31 2004-06-22 Intel Corporation Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set
US7111176B1 (en) 2000-03-31 2006-09-19 Intel Corporation Generating isolated bus cycles for isolated execution
US7089418B1 (en) 2000-03-31 2006-08-08 Intel Corporation Managing accesses in a processor for isolated execution
US6633963B1 (en) 2000-03-31 2003-10-14 Intel Corporation Controlling access to multiple memory zones in an isolated execution environment
US6976162B1 (en) 2000-06-28 2005-12-13 Intel Corporation Platform and method for establishing provable identities while maintaining privacy
US7389427B1 (en) 2000-09-28 2008-06-17 Intel Corporation Mechanism to secure computer output from software attack using isolated execution
US7793111B1 (en) 2000-09-28 2010-09-07 Intel Corporation Mechanism to handle events in a machine with isolated execution
US7215781B2 (en) * 2000-12-22 2007-05-08 Intel Corporation Creation and distribution of a secret value between two devices
US7035963B2 (en) 2000-12-27 2006-04-25 Intel Corporation Method for resolving address space conflicts between a virtual machine monitor and a guest operating system
US6907600B2 (en) 2000-12-27 2005-06-14 Intel Corporation Virtual translation lookaside buffer
US7818808B1 (en) 2000-12-27 2010-10-19 Intel Corporation Processor mode for limiting the operation of guest software running on a virtual machine supported by a virtual machine monitor
US7225441B2 (en) 2000-12-27 2007-05-29 Intel Corporation Mechanism for providing power management through virtualization
US7117376B2 (en) * 2000-12-28 2006-10-03 Intel Corporation Platform and method of creating a secure boot that enforces proper user authentication and enforces hardware configurations
US7233998B2 (en) 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US6809734B2 (en) 2001-03-22 2004-10-26 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
US7516334B2 (en) * 2001-03-22 2009-04-07 Sony Computer Entertainment Inc. Power management for processing modules
US6526491B2 (en) 2001-03-22 2003-02-25 Sony Corporation Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US6826662B2 (en) 2001-03-22 2004-11-30 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
US7231500B2 (en) * 2001-03-22 2007-06-12 Sony Computer Entertainment Inc. External data interface in a computer architecture for broadband networks
US7093104B2 (en) * 2001-03-22 2006-08-15 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
US7272831B2 (en) 2001-03-30 2007-09-18 Intel Corporation Method and apparatus for constructing host processor soft devices independent of the host processor operating system
US7096497B2 (en) * 2001-03-30 2006-08-22 Intel Corporation File checking using remote signing authority via a network
US20020144121A1 (en) * 2001-03-30 2002-10-03 Ellison Carl M. Checking file integrity using signature generated in isolated execution
US7191440B2 (en) * 2001-08-15 2007-03-13 Intel Corporation Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor
US7024555B2 (en) 2001-11-01 2006-04-04 Intel Corporation Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment
US7103771B2 (en) * 2001-12-17 2006-09-05 Intel Corporation Connecting a virtual token to a physical token
US20030126454A1 (en) * 2001-12-28 2003-07-03 Glew Andrew F. Authenticated code method and apparatus
US20030126453A1 (en) * 2001-12-31 2003-07-03 Glew Andrew F. Processor supporting execution of an authenticated code instruction
US7308576B2 (en) * 2001-12-31 2007-12-11 Intel Corporation Authenticated code module
US7480806B2 (en) * 2002-02-22 2009-01-20 Intel Corporation Multi-token seal and unseal
US7631196B2 (en) 2002-02-25 2009-12-08 Intel Corporation Method and apparatus for loading a trustable operating system
US7124273B2 (en) * 2002-02-25 2006-10-17 Intel Corporation Method and apparatus for translating guest physical addresses in a virtual machine environment
US7069442B2 (en) 2002-03-29 2006-06-27 Intel Corporation System and method for execution of a secured environment initialization instruction
US7162644B1 (en) 2002-03-29 2007-01-09 Xilinx, Inc. Methods and circuits for protecting proprietary configuration data for programmable logic devices
US7028149B2 (en) 2002-03-29 2006-04-11 Intel Corporation System and method for resetting a platform configuration register
US20030191943A1 (en) * 2002-04-05 2003-10-09 Poisner David I. Methods and arrangements to register code
US20030196096A1 (en) * 2002-04-12 2003-10-16 Sutton James A. Microcode patch authentication
US20030196100A1 (en) * 2002-04-15 2003-10-16 Grawrock David W. Protection against memory attacks following reset
US7076669B2 (en) * 2002-04-15 2006-07-11 Intel Corporation Method and apparatus for communicating securely with a token
US7058807B2 (en) * 2002-04-15 2006-06-06 Intel Corporation Validation of inclusion of a platform within a data center
US7127548B2 (en) 2002-04-16 2006-10-24 Intel Corporation Control register access virtualization performance improvement in the virtual-machine architecture
US7139890B2 (en) * 2002-04-30 2006-11-21 Intel Corporation Methods and arrangements to interface memory
US7024519B2 (en) * 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US6820177B2 (en) * 2002-06-12 2004-11-16 Intel Corporation Protected configuration space in a protected environment
US7142674B2 (en) * 2002-06-18 2006-11-28 Intel Corporation Method of confirming a secure key exchange
US7392415B2 (en) * 2002-06-26 2008-06-24 Intel Corporation Sleep protection
US20040003321A1 (en) * 2002-06-27 2004-01-01 Glew Andrew F. Initialization of protected system
US7124327B2 (en) 2002-06-29 2006-10-17 Intel Corporation Control over faults occurring during the operation of guest software in the virtual-machine architecture
US6996748B2 (en) 2002-06-29 2006-02-07 Intel Corporation Handling faults associated with operation of guest software in the virtual-machine architecture
US7296267B2 (en) * 2002-07-12 2007-11-13 Intel Corporation System and method for binding virtual machines to hardware contexts
US7165181B2 (en) 2002-11-27 2007-01-16 Intel Corporation System and method for establishing trust without revealing identity
US20040117532A1 (en) * 2002-12-11 2004-06-17 Bennett Steven M. Mechanism for controlling external interrupts in a virtual machine system
US7073042B2 (en) * 2002-12-12 2006-07-04 Intel Corporation Reclaiming existing fields in address translation data structures to extend control over memory accesses
US20040117318A1 (en) * 2002-12-16 2004-06-17 Grawrock David W. Portable token controlling trusted environment launch
US7318235B2 (en) * 2002-12-16 2008-01-08 Intel Corporation Attestation using both fixed token and portable token
US7318141B2 (en) 2002-12-17 2008-01-08 Intel Corporation Methods and systems to control virtual machines
US7793286B2 (en) * 2002-12-19 2010-09-07 Intel Corporation Methods and systems to manage machine state in virtual machine operations
US7900017B2 (en) * 2002-12-27 2011-03-01 Intel Corporation Mechanism for remapping post virtual machine memory pages
US20040128465A1 (en) * 2002-12-30 2004-07-01 Lee Micheil J. Configurable memory bus width
US7076802B2 (en) * 2002-12-31 2006-07-11 Intel Corporation Trusted system clock
US7415708B2 (en) * 2003-06-26 2008-08-19 Intel Corporation Virtual machine management using processor state information
US7287197B2 (en) * 2003-09-15 2007-10-23 Intel Corporation Vectoring an interrupt or exception upon resuming operation of a virtual machine
US7424709B2 (en) 2003-09-15 2008-09-09 Intel Corporation Use of multiple virtual machine monitors to handle privileged events
US7739521B2 (en) 2003-09-18 2010-06-15 Intel Corporation Method of obscuring cryptographic computations
US7610611B2 (en) * 2003-09-19 2009-10-27 Moran Douglas R Prioritized address decoder
US7177967B2 (en) 2003-09-30 2007-02-13 Intel Corporation Chipset support for managing hardware interrupts in a virtual machine system
US7366305B2 (en) * 2003-09-30 2008-04-29 Intel Corporation Platform and method for establishing trust without revealing identity
US7237051B2 (en) 2003-09-30 2007-06-26 Intel Corporation Mechanism to control hardware interrupt acknowledgement in a virtual machine system
US20050080934A1 (en) 2003-09-30 2005-04-14 Cota-Robles Erik C. Invalidating translation lookaside buffer entries in a virtual machine (VM) system
US7636844B2 (en) 2003-11-17 2009-12-22 Intel Corporation Method and system to provide a trusted channel within a computer system for a SIM device
US20050108171A1 (en) * 2003-11-19 2005-05-19 Bajikar Sundeep M. Method and apparatus for implementing subscriber identity module (SIM) capabilities in an open platform
US20050108534A1 (en) * 2003-11-19 2005-05-19 Bajikar Sundeep M. Providing services to an open platform implementing subscriber identity module (SIM) capabilities
US8156343B2 (en) 2003-11-26 2012-04-10 Intel Corporation Accessing private data about the state of a data processing machine from storage that is publicly accessible
US8037314B2 (en) 2003-12-22 2011-10-11 Intel Corporation Replacing blinded authentication authority
US7802085B2 (en) 2004-02-18 2010-09-21 Intel Corporation Apparatus and method for distributing private keys to an entity with minimal secret, unique information
US20050216920A1 (en) * 2004-03-24 2005-09-29 Vijay Tewari Use of a virtual machine to emulate a hardware device
US8224639B2 (en) 2004-03-29 2012-07-17 Sony Computer Entertainment Inc. Methods and apparatus for achieving thermal management using processing task scheduling
US7356735B2 (en) * 2004-03-30 2008-04-08 Intel Corporation Providing support for single stepping a virtual machine in a virtual machine environment
US7620949B2 (en) 2004-03-31 2009-11-17 Intel Corporation Method and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment
US7490070B2 (en) 2004-06-10 2009-02-10 Intel Corporation Apparatus and method for proving the denial of a direct proof signature
US20050288056A1 (en) * 2004-06-29 2005-12-29 Bajikar Sundeep M System including a wireless wide area network (WWAN) module with an external identity module reader and approach for certifying the WWAN module
US7305592B2 (en) 2004-06-30 2007-12-04 Intel Corporation Support for nested fault in a virtual machine environment
US7840962B2 (en) 2004-09-30 2010-11-23 Intel Corporation System and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time
US8146078B2 (en) 2004-10-29 2012-03-27 Intel Corporation Timer offsetting mechanism in a virtual machine environment
US8924728B2 (en) 2004-11-30 2014-12-30 Intel Corporation Apparatus and method for establishing a secure session with a device without exposing privacy-sensitive information
US8533777B2 (en) * 2004-12-29 2013-09-10 Intel Corporation Mechanism to determine trust of out-of-band management agents
US7395405B2 (en) 2005-01-28 2008-07-01 Intel Corporation Method and apparatus for supporting address translation in a virtual machine environment
US7809957B2 (en) 2005-09-29 2010-10-05 Intel Corporation Trusted platform module for generating sealed data
US8014530B2 (en) 2006-03-22 2011-09-06 Intel Corporation Method and apparatus for authenticated, recoverable key distribution with no database secrets
CN104933105B (en) * 2015-05-29 2019-02-12 北京奇虎科技有限公司 The analysis method and device of database access request

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3377624A (en) * 1966-01-07 1968-04-09 Ibm Memory protection system
US3576544A (en) * 1968-10-18 1971-04-27 Ibm Storage protection system
GB1329721A (en) * 1970-05-26 1973-09-12 Plessey Co Ltd Data processing devices
GB1410631A (en) * 1972-01-26 1975-10-22 Plessey Co Ltd Data processing system interrupt arrangements
US3854126A (en) * 1972-10-10 1974-12-10 Digital Equipment Corp Circuit for converting virtual addresses into physical addresses
US3825903A (en) * 1973-04-30 1974-07-23 Ibm Automatic switching of storage protect keys
US3828327A (en) * 1973-04-30 1974-08-06 Ibm Simplified storage protection and address translation under system mode control in a data processing system
US3916385A (en) * 1973-12-12 1975-10-28 Honeywell Inf Systems Ring checking hardware

Also Published As

Publication number Publication date
AU508001B2 (en) 1980-03-06
FR2349918A1 (en) 1977-11-25
US4037214A (en) 1977-07-19
SE7704963L (en) 1977-10-31
DE2716051C2 (en) 1982-06-09
FR2349918B1 (en) 1981-06-19
GB1557122A (en) 1979-12-05
JPS5738999B2 (en) 1982-08-18
SE417551B (en) 1981-03-23
ATA253877A (en) 1983-11-15
AT375204B (en) 1984-07-10
JPS52132738A (en) 1977-11-07
BR7702822A (en) 1978-04-04
AU2474677A (en) 1978-11-09
DE2716051A1 (en) 1977-11-10

Similar Documents

Publication Publication Date Title
CA1092716A (en) Key register controlled accessing system
US4038645A (en) Non-translatable storage protection control system
US4037215A (en) Key controlled address relocation translation system
US4042911A (en) Outer and asynchronous storage extension system
US4050094A (en) Translator lookahead controls
KR100303947B1 (en) Multiprocessor system and its initialization function distributed and self-diagnostic system and method
EP0099125B1 (en) Multicomputer system having dual common memories
EP0387644B1 (en) Multiprocessor system with global data replication and two levels of address translation units
EP0306702B1 (en) Virtual input/output commands
US4891752A (en) Multimode expanded memory space addressing system using independently generated DMA channel selection and DMA page address signals
US4035779A (en) Supervisor address key control system
US4042913A (en) Address key register load/store instruction system
US5638532A (en) Apparatus and method for accessing SMRAM in a computer based upon a processor employing system management mode
CA1087754A (en) Equate operand address space control system
JPH0260012B2 (en)
JP3629507B2 (en) System and method for providing shared memory using shared virtual segment identification in a computer system
US4037207A (en) System for controlling address keys under interrupt conditions
EP0196244A2 (en) Cache MMU system
EP0532690B1 (en) Method and apparatus for managing page zero memory accesses in a multi-processor system
GB2127994A (en) Memory management unit for digital computer
US5410662A (en) Programmable control of EMS page register addresses
CA1283221C (en) Microprocessor having separate instruction and data interfaces
JPH0652507B2 (en) Microcomputer development equipment
GB2161001A (en) Distributed microcode address for computer
JPS5897770A (en) Access controlling system for vector instruction

Legal Events

Date Code Title Description
MKEX Expiry