CA1070795A - Priority interrupt mechanism - Google Patents
Priority interrupt mechanismInfo
- Publication number
- CA1070795A CA1070795A CA244,791A CA244791A CA1070795A CA 1070795 A CA1070795 A CA 1070795A CA 244791 A CA244791 A CA 244791A CA 1070795 A CA1070795 A CA 1070795A
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- Canada
- Prior art keywords
- priority
- level
- processes
- processor
- requesting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Abstract
ABSTRACT OF THE DISCLOSURE
Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process.
additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.
Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process.
additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.
Description
B ~ROUND OF THE INVENTION
Field of the Invention This invention relates to data processing systems and more particularly to an apparatus and a method for interrupting and assigning process~s to a processor on a priority bias.
Description of the Prior Art In a general purpose computer system and particularly in ~ ;
a multiprogram-multiprocessing computer environment, processes ~ -are continuously vying with each other for control of one or more processors. In most prior art digital computers, there are some means of interrupting a program executing on a processor upon demand from an internal or external signal. Generally, the processor of the computar system is interrupted by the occurrence ~` of certain predetermined events which require immediate attention - by the processor. Generall~ in most machines, the interrupt is accomplished by selecting an address of another instruction in another program to execute a new routine, and is generally accomplished totally by software. Before execution of the new program is commenced however, certain registers containing information about the interrupt program must be saved in order to be able to return to the interrupted program at the exact point of interruption. The saving of these registers during the - period of interrupt and again the reloading of the registers when the interrupted program is ready to resume is time consuming, but tolerable in a mono processor, mono program environment.
However, in a multiprogram-multiprocessor environment, the over-head burden for housekeeping becomes intolerable. Accordingly, operational registers are provided which are unique to each stored program so that a change of control between programs
Field of the Invention This invention relates to data processing systems and more particularly to an apparatus and a method for interrupting and assigning process~s to a processor on a priority bias.
Description of the Prior Art In a general purpose computer system and particularly in ~ ;
a multiprogram-multiprocessing computer environment, processes ~ -are continuously vying with each other for control of one or more processors. In most prior art digital computers, there are some means of interrupting a program executing on a processor upon demand from an internal or external signal. Generally, the processor of the computar system is interrupted by the occurrence ~` of certain predetermined events which require immediate attention - by the processor. Generall~ in most machines, the interrupt is accomplished by selecting an address of another instruction in another program to execute a new routine, and is generally accomplished totally by software. Before execution of the new program is commenced however, certain registers containing information about the interrupt program must be saved in order to be able to return to the interrupted program at the exact point of interruption. The saving of these registers during the - period of interrupt and again the reloading of the registers when the interrupted program is ready to resume is time consuming, but tolerable in a mono processor, mono program environment.
However, in a multiprogram-multiprocessor environment, the over-head burden for housekeeping becomes intolerable. Accordingly, operational registers are provided which are unique to each stored program so that a change of control between programs
- 2 -, 10~ 5 requires no intervention by an executive program to unload or reload the registers. ~See United States Patent No.
3,226,694 issued December 28, 1965 to Harry D. Wise, entitled Interrupt System).
As the ~ultiprogrzmming-multiprocessing environment became more complex, it became necessary to assign priorities to processes so that a process requesting control of a processor could in~errupt another process having a lower priority. How-ever, because of the software nature of the interrupt, it often was necessary to interrupt a high priority process to determine whether or not the requesting process did in fact have a higher or lower priority than the executing process. Often it was discovered that the requesting process had a lower priority than the executing process whereupon the executing process continued to run. However, during the time that was consumed to determine which one of the two, the executing or requesting process had higher priority, a higher priority process had in fact been interrupted by a lower priority process, merely to make the determination.
What is needed, therefore, is a hardware mechanism to monitor and determine if an executing process has higher or lower priority than a requesting process, prior to the actual interrupt of the executing process.
OBJECTS OF THE INVENTION
It is a primary object of the invention therefore to provide an improved interrupt mechanism for a general pur-pose computer system.
It is anather object of thc in~ention to provide a hard-ware mechanism for a general purpose computer system to continuously _ 3 _ 1~37~7~5 monitor interrupt-requesting processes and determine whether or not an executing process has a higher or lower priority than the process requesting control of the processor prior to tha actual interruption of the executing process.
. . - ~
Still another object of the invention is to provide ~ -a mechanism for a general purpose computer system that permits a portion of a given process to be executed at one priority level whereas another portion of the same process is executed at another priority level.
It is yet another object of the invention to determine a priority level based on port or peripheral unit number of a general purpose computer system when two or more interrupt re-quests haYing th~ same priority level are simultaneously seeking processor control.
SUMMARY OF T~E INVENTION
In accordance with the above and other objects of the învention, a priority interrupt mechanism is provided to con-tinuously monitor internal or external interrupt requests from processes desiring control of the processor and determine whether or not the requesting processes have a higher level o priority than the executing process.
Interrupts in the processor are assigned to one of eight priority levels (although any number of priority levels may be utilized~ with level zero being the highest priority level and level seven being $he lowest. In order to minimize the time required to answer an interrupt request, the processor provides a complete set of registers for each of the eight levels. When an interrupt causes the initiation of a new process, the current process is left intact in the registers assigned to the curreTIt level. Control may be returned to the interrupted process ~07~3795 simply by reactiva-ting that process level. The need to safe-store and restore interrupt processes is eliminated, along with ~he accompanying overhead.
According to one aspect of the invention there is provided, in a data processing system having a plurality of processors coupled to an interface unit via predetermined processor communication channels each processor being selectively controlled by selected ones of a first group of processes, said data processing system also having a plurality of peripheral devices also coupled to said interface unit via predetermined peripheral channels for communi.cating with each other and with said processors, said data processing system further having monitoring means for monitoring request signals from a plurality of a second group of processes requesting control and vying with each other for control of one of said processors via one of said processor communication channels, each process and each peripheral channel being associated with a predetermined level of priority, a priority interrupt mechanism included in said interface unit for determining, ~efore interrupting one of said selected first processes, the highest priority peripheral channel of a highest priority second process of said second group of processes request~ng control of one of said processor communica-tion channels, and for further determining whether or not said one of said first processes on sai.d one of said processors has ; a higher priority than said highest priority peripheral channel of the highest priority second process requesting control of said one of said processors, said priority mechanism comprising:
a. first means responsive to said monitoring means for directing said request signals from said second group of processes to one of said processor communication channels ; -5-~7~7~5 ~ `:
requested by said second group of processes;
b. second means, coupled to said first means, for determining the highest priority of said request signals from said second group of processes;
c. third means for storing the priority level of said currently executing firc;t process on said selectively controlled one of said processors;
d. fourth means coupled to said second means for deter-mining the highest priority level of each peripheral channel of said second group of processes requesting assignment to one of said selected processors; and, e. fifth means, coupled to said second, third and fourth means, for determining the higher priority level between said ; currently executing first process and the highest priority peripheral channel of said second process having said highesk priority request.
According to another aspect of the invention there .is provided, in a data processing system having a plurality of peripheral units and one processor for sequentially executing instructions of a first one of a plurality of processes having a first level of priority, each of said processes having a priority level based on the relative importance of said ; plurality of processes, and with any o said processes generat-; ing signals for requesting control of said one processor, said : one processor having a plurality of sets of registers each of said sets of registers associated with. a predetermined priority level and with a first of said sets of reigsters which has a level of priority equal to said first level of priority of said first one of said plurality of processes, storing signals represenking instructions of said first one of said processes, ~ -6-- ~07~795 said data processing system further including at least one peripheral channel for each one of said peripheral units for communication between said peripheral units and said processor, each peripheral channel having a priority level based on the relative importance o the peripheral unit associated with the peripheral channel, and ~ith any of said peripheral channels also generating signals for requesting assignment to said one processor, a priority apparatus for determining priority among said requesting processes and among said peripheral channels before said processor is interrupted, said priority apparatus comprising:
a. first means for determining the highest priority level o~ said peripheral channels requesting assignment to said one processor;
b. second means coupled to said first means for determin-ing the highest priority level among said requesting processes;
c. third means, coupled to said first and second means and to said first of said sets of registers, for comparing the priority level of said requesting processes requesting peripheral channels and said first one of said plurality of processes; and d. fourth means, coupled to said third means for notifying said processor that a process having a prirority level among the requesting processes higher than the priority level of said first one of said plurality of processes desires to interrupt said first one of said plurality of processes.
BRIEF DESCRIPTION OF THE DR~INGS
Figure 1 is a schematic block diagram of a typical computer system utili.zing the invention.
Figure 2 is a schematic block diagram of the invention.
Figure 3 is a schematic loyic block diagram of the ~ -6a-., ~LO~t;~S , ~
priority interrupt mechanism of the invention.
Figure 4 is a schematic logic block diagram of the dispatcher mechanism of the invention.
Figure 5 is a logic block diagram of the priority tree utilized in the invention.
Figure 6 is a logic block diagram of a one of two data multiplexor utilized in the invention.
Figure 7 is a logic block diagram o a one of four data multiplexor utilized by the invention.
Figure 8 is a logic block diagram of a one of eight data multiplexor utili2ed by the invention.
DESCRIPTION OF THE PREFERRED EM ODIMENT OF THE INVENTION
Reerring now to Figure 1, there is shown a typical computer system utilizing the invention. The System Inter~ace Unit (SIU) 100, containing the priority interrupt and dispatcher unit mechanisms 101 and 102 respectively, provides connections between the elements of the computer processing system. In addition to providiny for access of local or remote memory 121, 122 and 122a, 123 respectively by the active module processors 103 106, configuration panel 124 etc., the SIU 100 provides for direct addressing of the high and low speed multiple~ors 107 and 112, 113 respectively and control adapters 108, 109, 134 and 135 by the ~rocessors 103-106.
The interrupt unit 101 and the dispatcher unit 102, to be more fully described ;nfra, control the interrupt discipline and perform processor dispatching as required.
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Each processor 103-106 typically contains 16 registers 130-133 for each level of priority assigned to a process or a total of 128 register processors capable of storîng 128 words. -(These registers are sometimes referred to in this specification as the scratchpad memo3y}. Each processor is a general purpose computer processor with a conventional complement of register-registerS register-memory, immediate, branch, bit field and shift instructions. These processors may be used as input/output processors CIop) whose functions include initiation and termination of I/O command sequences, fetching, checking and translating channel programs, and direct control of low speed peripheral devices such as unit record and data communications equipment. Processors 103-106 are attached to and communicate with the SIU 100 via ports ~1, G, P and ~ respectively.
The processor local memories 121, 122 communicate with the processors lQ3-106 via the interface unit SIU and ports ~O
and LMl. Each of the local memories 121, 122 is organized as a - read-write store 136, 137 respectively, plus read only memory ROM 138, 139 with an optional cache memory 140, 141. Width of the local memory interface LMo, LMl is 36 bits plus 4 bits for parity. Local memory size is typically 256K or 512K bytes wherein each K is equal to 1024 bytes.
The remote memory adapters 122, 123 are utilized when the SIV with its processors and peripherals are part of a largeT
general purpose computer system. The Remote Memory Adapters (REMA~ 122a, 123 then provide a means of exchanging control and data transfers between the processors 103-106 and a Central System Interface Unit of the larger general purpose computsr system not shown herein. Up to 2 ports ~, ~ and ~ , ~ for each of the REMA units 122a, 123 respectively are provided, each 7(~'~95 por-t having a 40-bit data path for input and 40 bits for output between the computer system shown and described herein and a larger computer system not shown herein. The REMA units 122a, 123 are connected and communicate with the SIU 100 viai ports RMQ and RMl A high speed multiplexor 107 provicles direct control of data transfers between high speed peripheral devices (disk drive 110, tapio drive 111) and remote 122a, 123 or local memory 121, 122. The high speed multiplexor 107 interfaces between 10 the SIU and the peripherals via ports A-F.
Each low speed multiplexor 112, 113 permits direct control by a processor 103-106 of a low-speed device such as card punch 118, printer 119 and console 120, via ports J and K and device adapter interface unit DAI 115, 116 and 117 respectively.
There are typically 16 registers 130-133 for each level in the 128-word processor scratchpad registers of each processor 103-106. Since level zero may ne~7er be interrupted, the process state register for level zero is never transferred 20 to the scratchpad memory; however, register 0 of level 0 is utilized ko hold a control block base which contains the base address in memory of the exception control block or the interrupt control block which in turn is utilized to provide the address of an interrupting or interrupted process.
The interrupt mechanism invention constantly monitors both the current process level of the processor and all requests for interrupt from any module attached to any port A-L
or LMol LMl, RMo~ of system interface unit ~IU 100 of Figure 1. Each interrupt request specifies the null~ber of the 30 processor to be interrupted, the priority (level number) of the ~; ~ -8-9s request, and addresses to identiy the interrupt requestor.
This information is held in each module which may request interrupts, and for most modules it can be set using program-mable interface commands.
Whenever an interrup~ request is present at a level higher than the current level, the SIU 100 raises the higher level interrupt present line to the cognizant processor. If several interrupt requests are present at an equal level, the interrupt invention determines which request is to be passed on to the processor on the basis of priorities established by port number or peripheral unit number.
Referring now to Figure 2 there is shown a block diagram of the inkerrupt and dispatcher mechanism which are shown and described in greater detail on Figures 3-5. An interface unit 201 may typically be the system interface unit (SIU~ of Figure 1 which provides the interfacing paths and control for all the communication between processors and all -~
system modules. Interrupt requests to the processors 103-106 may come from any units attached ports A through L and LMo~RMo. An interrupt request presented to the interface 201 is accompanied by such pertinent information as the interrupt level, processor number and interrupt control block number. A
parity check is performed on this information in unit 201 to determine that the correct information is presented to the priority interrupt hardware and if an error is discovered, a kill-interrupt signal is raised on line 201a. Additionally, since processors 103 and .
, -8a-~o~u~
104 on ports ~l and G respectively and processors 105 and 106 Oll ports F and G may operate as processor pairs respectively, a comparison of the interface number on which ~hey are opera~-ing is made to determine that the appropriate processors are paired together. Typically processor 103 is paired with 104 and when paired in this manner is called processor 0 in this disclosure; alternately processors 105 and 106 are paired to-gether and aTe regarded as processor 1 in this disclosure when so paired. Accordingly, the interrupt level number upon being checked for correctness is presented to the level decode units 202, 204. If an error is discovered during this check, the interrupt requost is aborted until the error is cleared; however, if no error is prese~ted, then the processor switch 203 selects one of the two processor paths 0 or 1 for processor pair 0 or 1 in accordance to the process number and C~IG path bit present-ed to it. The change path (C~IG~ control bit provides software with a means to cause the path 0 or the path 1 logic (Figure 2) to be used in order to get an interrupt request to either processor. Its a redundancy feature that will allow an interrupt to a processor even i~ there ls a hardware failure in the path 0 or path 1 logic i.e. change and use the other logic tree. (See references B and C incorporated herein by reference). For illustration purposes it is assumed that processor path 0 has been selected by the switch 203. The level decode un~t 202 decodes the interrupt level which is presented to it as a 3 bit binary number and presents the decoded information to OR gate circuitry 205. As will be more fully described infra, the OR circuitry 205 collects all the level numbers from all the ports attached to the SIU 100 ~7~7~
and provides level numbers if they are present in any of the ports to the level priority circuitry 206. The level priority circuitry 206 to be more fully described infra with respect to Figure 5 determines the highest level priority number which ;
is present and if the ilighest level priority number present is 0, (i.e. 0 has the highest priority level and 7 has the lowest priority level), then ~he interrupt signal is presented immediate-ly to the path 0 control logic so that ~he processor is immediately interrupted. HoweverJ if none of th0 ports have presented a 0 interrupt level but some of the ports have lower interrupt level number presentJ for example, priority three through seven, it is obvious that according to the convention adopted he:rein that 3 has the highest level priority for the next clock cycle.
A comparison is then made in comparator 207 to determine if the level 3 priority interrupt, which some ports are requesting in this example, is higher or lower than the level number of the process currently executing. Carrying the present example further for illustration purposes, assume that the interrupt level number 3 has a higher priority than the currently executing process which is somewhere below 3, i.e. 4J 5, etc.
~loweverJ because there are many ports in the SIU which have many requestor units coupled to it, more than 1 unit can simultaneously be asking for an interrupt and more than 1 unit can simultaneously have the same priority level number. Obvious-ly the processor requested cannot be assigned to more than one processor simultaneously; accordlngly, a determination is made to determine which process is to receive control of the processor requested when two or more ports simultaneously make an identical level request i.e. in this example a level 3 request. De~ermina-tion is made in accordance to predetermined and fixed prio-rities ~t7~79S
assigned to the different ports of the SIU. Accordingly, a multi-plexor 207 is presented with all those port identifications A
through L, RMo or RM that have requested processor O for the highest priority level task, in this exa~ple level 3. Since all those ports A through ~Ml have different priorities in the hierarchy of performing tasks and this priority is predetermined, then a determination is made in port-priority unit 208 which port A through L or L~o~RMl is entitled to receive control of the processor when more than 1 of these ports have made the same level priority task request. Once the final determination of this priority is made and the appropriate processor notified that a higher priority task is waiting to be performed, then no further actions are r~quired of the priority interrupt mechanism until such time as the requested processor asks for the interrupt data. The data from the highest priority port which has the highest priority level interrupt request is available to a passive input (PIP) cross bar 219 through either a V switch or a W switch mechanism 210, 218, 215, 217 respective-ly on a request from the processor via request logic 209, 216.
The V switch control mechanism 210 develops control signals for providing data to V switch 218 from ports A, C, E, F, J, RMo and an old interrupt. Similarly the W switch control unit 215 develops signals to provide data to W switch 217 from ports L, B, D, G, H, K, RMl Depending therefore which set of control signals have been developed for the highest priority port which has the highest priority interrupt request either the V switch or the W switch 218, 217 respectively will make data available to the processor via the PIP cross bar 219 via control logic 220.
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Referring now to Figure 3 a detailed logic block diagram of the interrupt mechanism is shot~. In order to clarify the invention and not clutter up the explanation with hardware which is merely repetitive as to the requesting port or as to the request-ed processor, Figure 3 shows the interrupt mechanism for ane pro-cessor pair P0 comprising processors ~ and G, 103 and 104 respective-ly; the interrupt mechanism for processor pair Pl comprising processors F and E, 132 and 133 respectively is similar to Pigure 3. Moreover, the hardware directly interfacing with the SIU 100 and the priority interrupt unit for each processor P0, Pl is :
enclosed by dash line 300 and is repeated once f.~r ports G and ~l ~rocassor 0) an~ once for ports E and ~ (processor 1). It is to be understood therefore that theIe are as many port 1nterface units 300 as above described and moreover that there are also as many priority interrupt networks as there are processor pairs.
In order to initiate a processor interrupt, an inter-rupt request signal IR is applied to an AND gate 307 from the port making the request which is associated with this particular one 2a of the port interface units 300. Concurrently the requesting port supplies a level priori.ty number LN for the request to gate 301 ancl also a processor number to gate 304. However, since the SIU 100 is not permitted to respond to any request from any module which is not logically operational, an LOP signal is also applied to AND gate 307. With both the interrupt request IR
signal and the 10P signal high AND gate 307 is enabled and provides a high input signal to one înput terminal of each of AND gates 305 and 306 respectively. It also permits the leve].
number data which is a 3 bit binar~ number applied to gate 301 ~)7637~5 to be checked for parity in parity checkin~ unit 302 by pro-vidin~ an enabling signal to it. Since only two processor pairs are considered herein, although the invention may utilize any number of processor pairs, a one bit binary number is sufficient to select processor pair P0 or processor pair Pl as desired. Accordingly, when the one bit processor number PM
is applied to gate 304, one output terminal 306a of gate 304 uill be low. (All amplifier and an inverter may be used in practice). With the signal on output terminal 305a high, a high input si~nal is provided on one input terminal of AND gate 305 thus enabling AND gate 305 and selecting decode unit 308 for processor Pl. By ~he same token, since ~he other output terminal 306a of gate 30~1 is low, the input signal on thq other input ter~llinal of AND gate 306 is low, and AND gate 306 ls not enabled; thus decode unit 309 is not activated for processor PO. By providing a different input code Eor the processor number PN, the procedure would be reversed and the decode unit 309 for processor P0 would be selected over the decode unit 308 oE processor Pl. Upon the salection of the c~ppropriate processor 2a pair, two checks are performed. As has already been noted, a parity check is performed in parity check unit 302 on the 3 bit level nunlber LN and the 1 bit PN. ~Parity generator and checker circuits are commercially available through such companies as Texas Instruments Inc., see pages 9-309 of the Integrated Circuits Catalog for Design Engineers, published by Texas Instruments Inc.). If an error is detected, the interrupt reques~
is aborted, whereas if no error is detected, the level number da*a is sent ~o decode unit 308 or 309 of the selected processor pair Pl or P0. For purposes of simplification, we are assuming in this discussion that processor P0 has been selected in which case level number data is sent to decode unit 309. Another check is performed by the compare unit 303 to verify that every output line on the interface in the SIU from one member of a processor pair, agree with the corresponding line from the other member of pair. If they do not agree at any clock time, an error state is entered and the interrupt request is aborted.
Having selected the appropriate processor and the approp-riate decode unit and having checked the information and the pro-cessor pair for correctness, the 3 bit level number is d~coded in either decode unit 308, 309. In this instance since it is assumed that processor pair P0 has been requested, that decode unit 309 will be performing the decoding. (Decoders are commercially available from such companies as Texas Instruments Inc., see pages 9-149 through 9-213 af the Integrated Circuits Catalog or Design Engineers published by Texas lnstruments Inc., of Dallas, Texas).
The level number from a given requesting unit having been decoded by its appropriate decode unit 309 will be applied in its decoded state to a series of OR gates 310-311. ~Note that for each processor pair P0 and Pl there are as many OR gates as there are predetermined levels of priority of interrupting requests.
In this example since there are 8 levels of priority the O level being the highest priority, there will be 8 OR gates 310-311 for processor pair O and 8 OR gates similar to these for processor pair Pl). The output of each OR gate when enabled provides a signal which is indicative of the level of interrupt with which that particular OR gate is associated. Each OR gate 310-311 has as many inputs as there are ports on the system interface unit -~7g5 SIU 100. If there is a highest level interrupt (i.e. a level n interrupt) on any of the ports of the SIU 100, OR gate 310 which in this example is associated with the level O interrupt, OR gate 310 will provide a high output signal. Since a level O interrupt requires immediate attention, the signal from OR
gate 310 will be stored in flip-flop 312 until the next clock period whereupon it is then presented to the appropriate processor pair PO via the appropriate ports G, ~1 in the SIU.
However, if there is a priority request lower than level O as indicated by a high output signal on any of the OR gates between 310 up to and including gate 311, then a determination must be ma~e as follows: first determines the highest priority request on uny pvrt during the clock cycle that a request is made, and secondly after having determined the highest priority request determine whether or not that highest priority request is higher than the pr;ority of the process currently executing on the processor. Accordingly, all the output signals from the series of OR gates 310-311 are applied to a priority tree 315, which will be describ0d more fully infra with respect to Figure 5, 2n via a series of OR gates 313, 314. Note that the output level signals representing levels 1-7 are applied one each to an OR
gate in the series of OR gates 313-314. Also note that an additional input signal is applied to one each of the series of OR gates 313-314 which represent old levels of priority of processes which were interrupted at some ~ime previous in order to perform a higher priority task. Therefore, it is apparent that not only are the signals representing a level of priority for a new requesting process applied to the priority tree9 but also those signals representing a level of pri.ority of processes that have been previously interrupted and were unable to complete ~ 7~1795 their task. Accordingly the priority tree 315 evaluates all levels of priority present and past, and selects only the highest level exis~ing during the current clock cycle. At any point in time only one high output signal representing the highest level of priority exists. This ex-isting level of priority is then encoded in encoder 316 into a 3 bit binary number representing the highest level of priority currently existing in the requesting and interrupted processes. This priority number is: a) strobed into a 3 bit holding register 320 for temporary storage in case that the processor decides to enter the new level and; b) it is compared in comparator 32~ with the 3 bit binary number representing the level of priority of the currently executing procoss which is sto~ed in register 321. If a priority level number o~ a requesting process or a prior interrupted process is higher than the priority level number of the currently executing process, then a signal is applied to flip-flop 325 which is then transmitted to the appropriate processor pair, in this instance processor pair P0, via ports G, H. Note that the processor has not been interrupted but rather a signal has been conveyed to it, that there is a process waiting which has a higher prio~ity level nu~ber than the currently executing process whereupon the processor itself then takes the appropriate action durîng the next clock cycle.
It should be noted that up to this point in the dis-cussion, the port which îs requesting a processor to perform a higher priority task than the currently executing task has not as yet been identified. It could be that, since there are mul- ;~
tiple ports, more than one port is request;ng the same priority level interrupt as another port~ Therefore, hardware is provided ~07~37~S
to detect such a condition and determine which port is entitled to receive control of the processor. The hardware provided to determine this is in the form of a decode unit 317 which decodes the previously encoded 3 bi~ binary number. The hardware also includes a series of multiplexors 318-319, each multiplexor associated with a given priority level number, and each multi-plexor having as inputs the decoded priority level numbers from all the ports in the SIU 100. (Multiplexors are commercially available from the above mentioned Texas Instruments Inc., of Dallas, Texas). Hence~ priority numbers have been assigned not only on the basis of priority level of the requesting task or process, but also priority numbers have been assigned in a pr~determined fashion to each port of the SIU 100. Generally, the highest priority numbers have been reserved ~or those ports to which are attached data moving devices such as high speed multiplexors into or out of a system, and the lower priority numbers have been assigned to those ports which are associated with low priority attachments such as memories. Accordingly, when the highest priority level of a requesting process is decoded in decoder 317 that signal will be applied to the multiplexor indicating that level of decoded priority. The multiplexor which may typically be a 1 of 8 or 1 of 13 or whatever is needed to cover the number of ports on the SIU 100, will identify all those ports which have the highest level priority request during the currently executing clock cycle.
I~e signals from all those ports having the current highest priority request are then applied to a priority tree 326. Also the output signals from decoder 317a and the series of multi-plexors 322-323 representing priority of prior interrupted ~LV7(~75~5 ~
processes are applied to priority tree 326. Priority tree 326 therefore considers all ports with the highest lev01 of priority that are currently requesting an interrupt or that have been interrupted at a prior clock cycle cmd have not completed their tasks. Priority trea 326 from this input information then seleots that port having the highest priority which also has the highest level priority request on it. An output signal from priority tree 32~ representing that port is then applied to encode unit 328; the encoded result is then temporarily stored in flip-flops 329 or 330 and applied to the appropriate V switch or W switch of processor P0 or Pl. Flip-flop 327 is used to hold the fact that the hîghest level request from the highest priority port is either a new request or an old request which is ~o be resumed. This informat;on is supplied to the processor when the processor is ready for the next process.
A release instruction Cnot shown herein) ~REL) is used to exit processes entered as the result of an interrupt. After a REL the SIU selects for execution the highest priority process waiting for the processor.
This process may be one that was previously interrupted, or a new process to be initiated as the result of an interrupt request. At the same priority level, previously interrupted pro-cesses have priority over new interrupt requests. Through hardware ~see reference B supra) and software loading of the PCR, ~shown in refarence C supra), a processor may present ~o the SIU an inter-rupt at any level, 0-7. Howaver, in order to provide a well-defined response to a REL executed at any level, the PCR bit request-ing a level 7 interrupt is always set.
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If a new process is to be entered as a result of a REL, the processor response is similar to that triggered by a normal interrupt, including acceptance of an interrupt word from the SIU
and access to an ICB (see reference C supra). If a prevlously interrupted process is to be re-entered, the SIU supplies only the level number and the fact ~hat an old process is to be re-entered. Since the process state at the time of its interruption is intact in the register scratchpad, this is the only information required to restart the process.
Referring now to Figure 4 there is shown the dispatcher mechanism which dispatches the data from the appropriate port to the processor requesting such data. The priority interrupt mechanism of Figuro 3 having identified that there is either a level 0 request or a request that has a higher level of priority than the currently executing process has provided a signal apprising the appropriate processor of this condition~ The appropriate processor then requests the data which must be dispatched to the correct processor via a V data switch 218 or a W data switch 217 through the passi~e input cross bar PIP 219.
Accordingly, a control mechanism 400 is provided to develop the control signals for selecting the W data output unit 400a or tho V data output unit 400b. Note by referring to Figure 1 and Figure
As the ~ultiprogrzmming-multiprocessing environment became more complex, it became necessary to assign priorities to processes so that a process requesting control of a processor could in~errupt another process having a lower priority. How-ever, because of the software nature of the interrupt, it often was necessary to interrupt a high priority process to determine whether or not the requesting process did in fact have a higher or lower priority than the executing process. Often it was discovered that the requesting process had a lower priority than the executing process whereupon the executing process continued to run. However, during the time that was consumed to determine which one of the two, the executing or requesting process had higher priority, a higher priority process had in fact been interrupted by a lower priority process, merely to make the determination.
What is needed, therefore, is a hardware mechanism to monitor and determine if an executing process has higher or lower priority than a requesting process, prior to the actual interrupt of the executing process.
OBJECTS OF THE INVENTION
It is a primary object of the invention therefore to provide an improved interrupt mechanism for a general pur-pose computer system.
It is anather object of thc in~ention to provide a hard-ware mechanism for a general purpose computer system to continuously _ 3 _ 1~37~7~5 monitor interrupt-requesting processes and determine whether or not an executing process has a higher or lower priority than the process requesting control of the processor prior to tha actual interruption of the executing process.
. . - ~
Still another object of the invention is to provide ~ -a mechanism for a general purpose computer system that permits a portion of a given process to be executed at one priority level whereas another portion of the same process is executed at another priority level.
It is yet another object of the invention to determine a priority level based on port or peripheral unit number of a general purpose computer system when two or more interrupt re-quests haYing th~ same priority level are simultaneously seeking processor control.
SUMMARY OF T~E INVENTION
In accordance with the above and other objects of the învention, a priority interrupt mechanism is provided to con-tinuously monitor internal or external interrupt requests from processes desiring control of the processor and determine whether or not the requesting processes have a higher level o priority than the executing process.
Interrupts in the processor are assigned to one of eight priority levels (although any number of priority levels may be utilized~ with level zero being the highest priority level and level seven being $he lowest. In order to minimize the time required to answer an interrupt request, the processor provides a complete set of registers for each of the eight levels. When an interrupt causes the initiation of a new process, the current process is left intact in the registers assigned to the curreTIt level. Control may be returned to the interrupted process ~07~3795 simply by reactiva-ting that process level. The need to safe-store and restore interrupt processes is eliminated, along with ~he accompanying overhead.
According to one aspect of the invention there is provided, in a data processing system having a plurality of processors coupled to an interface unit via predetermined processor communication channels each processor being selectively controlled by selected ones of a first group of processes, said data processing system also having a plurality of peripheral devices also coupled to said interface unit via predetermined peripheral channels for communi.cating with each other and with said processors, said data processing system further having monitoring means for monitoring request signals from a plurality of a second group of processes requesting control and vying with each other for control of one of said processors via one of said processor communication channels, each process and each peripheral channel being associated with a predetermined level of priority, a priority interrupt mechanism included in said interface unit for determining, ~efore interrupting one of said selected first processes, the highest priority peripheral channel of a highest priority second process of said second group of processes request~ng control of one of said processor communica-tion channels, and for further determining whether or not said one of said first processes on sai.d one of said processors has ; a higher priority than said highest priority peripheral channel of the highest priority second process requesting control of said one of said processors, said priority mechanism comprising:
a. first means responsive to said monitoring means for directing said request signals from said second group of processes to one of said processor communication channels ; -5-~7~7~5 ~ `:
requested by said second group of processes;
b. second means, coupled to said first means, for determining the highest priority of said request signals from said second group of processes;
c. third means for storing the priority level of said currently executing firc;t process on said selectively controlled one of said processors;
d. fourth means coupled to said second means for deter-mining the highest priority level of each peripheral channel of said second group of processes requesting assignment to one of said selected processors; and, e. fifth means, coupled to said second, third and fourth means, for determining the higher priority level between said ; currently executing first process and the highest priority peripheral channel of said second process having said highesk priority request.
According to another aspect of the invention there .is provided, in a data processing system having a plurality of peripheral units and one processor for sequentially executing instructions of a first one of a plurality of processes having a first level of priority, each of said processes having a priority level based on the relative importance of said ; plurality of processes, and with any o said processes generat-; ing signals for requesting control of said one processor, said : one processor having a plurality of sets of registers each of said sets of registers associated with. a predetermined priority level and with a first of said sets of reigsters which has a level of priority equal to said first level of priority of said first one of said plurality of processes, storing signals represenking instructions of said first one of said processes, ~ -6-- ~07~795 said data processing system further including at least one peripheral channel for each one of said peripheral units for communication between said peripheral units and said processor, each peripheral channel having a priority level based on the relative importance o the peripheral unit associated with the peripheral channel, and ~ith any of said peripheral channels also generating signals for requesting assignment to said one processor, a priority apparatus for determining priority among said requesting processes and among said peripheral channels before said processor is interrupted, said priority apparatus comprising:
a. first means for determining the highest priority level o~ said peripheral channels requesting assignment to said one processor;
b. second means coupled to said first means for determin-ing the highest priority level among said requesting processes;
c. third means, coupled to said first and second means and to said first of said sets of registers, for comparing the priority level of said requesting processes requesting peripheral channels and said first one of said plurality of processes; and d. fourth means, coupled to said third means for notifying said processor that a process having a prirority level among the requesting processes higher than the priority level of said first one of said plurality of processes desires to interrupt said first one of said plurality of processes.
BRIEF DESCRIPTION OF THE DR~INGS
Figure 1 is a schematic block diagram of a typical computer system utili.zing the invention.
Figure 2 is a schematic block diagram of the invention.
Figure 3 is a schematic loyic block diagram of the ~ -6a-., ~LO~t;~S , ~
priority interrupt mechanism of the invention.
Figure 4 is a schematic logic block diagram of the dispatcher mechanism of the invention.
Figure 5 is a logic block diagram of the priority tree utilized in the invention.
Figure 6 is a logic block diagram of a one of two data multiplexor utilized in the invention.
Figure 7 is a logic block diagram o a one of four data multiplexor utilized by the invention.
Figure 8 is a logic block diagram of a one of eight data multiplexor utili2ed by the invention.
DESCRIPTION OF THE PREFERRED EM ODIMENT OF THE INVENTION
Reerring now to Figure 1, there is shown a typical computer system utilizing the invention. The System Inter~ace Unit (SIU) 100, containing the priority interrupt and dispatcher unit mechanisms 101 and 102 respectively, provides connections between the elements of the computer processing system. In addition to providiny for access of local or remote memory 121, 122 and 122a, 123 respectively by the active module processors 103 106, configuration panel 124 etc., the SIU 100 provides for direct addressing of the high and low speed multiple~ors 107 and 112, 113 respectively and control adapters 108, 109, 134 and 135 by the ~rocessors 103-106.
The interrupt unit 101 and the dispatcher unit 102, to be more fully described ;nfra, control the interrupt discipline and perform processor dispatching as required.
-6b-79:S
Each processor 103-106 typically contains 16 registers 130-133 for each level of priority assigned to a process or a total of 128 register processors capable of storîng 128 words. -(These registers are sometimes referred to in this specification as the scratchpad memo3y}. Each processor is a general purpose computer processor with a conventional complement of register-registerS register-memory, immediate, branch, bit field and shift instructions. These processors may be used as input/output processors CIop) whose functions include initiation and termination of I/O command sequences, fetching, checking and translating channel programs, and direct control of low speed peripheral devices such as unit record and data communications equipment. Processors 103-106 are attached to and communicate with the SIU 100 via ports ~1, G, P and ~ respectively.
The processor local memories 121, 122 communicate with the processors lQ3-106 via the interface unit SIU and ports ~O
and LMl. Each of the local memories 121, 122 is organized as a - read-write store 136, 137 respectively, plus read only memory ROM 138, 139 with an optional cache memory 140, 141. Width of the local memory interface LMo, LMl is 36 bits plus 4 bits for parity. Local memory size is typically 256K or 512K bytes wherein each K is equal to 1024 bytes.
The remote memory adapters 122, 123 are utilized when the SIV with its processors and peripherals are part of a largeT
general purpose computer system. The Remote Memory Adapters (REMA~ 122a, 123 then provide a means of exchanging control and data transfers between the processors 103-106 and a Central System Interface Unit of the larger general purpose computsr system not shown herein. Up to 2 ports ~, ~ and ~ , ~ for each of the REMA units 122a, 123 respectively are provided, each 7(~'~95 por-t having a 40-bit data path for input and 40 bits for output between the computer system shown and described herein and a larger computer system not shown herein. The REMA units 122a, 123 are connected and communicate with the SIU 100 viai ports RMQ and RMl A high speed multiplexor 107 provicles direct control of data transfers between high speed peripheral devices (disk drive 110, tapio drive 111) and remote 122a, 123 or local memory 121, 122. The high speed multiplexor 107 interfaces between 10 the SIU and the peripherals via ports A-F.
Each low speed multiplexor 112, 113 permits direct control by a processor 103-106 of a low-speed device such as card punch 118, printer 119 and console 120, via ports J and K and device adapter interface unit DAI 115, 116 and 117 respectively.
There are typically 16 registers 130-133 for each level in the 128-word processor scratchpad registers of each processor 103-106. Since level zero may ne~7er be interrupted, the process state register for level zero is never transferred 20 to the scratchpad memory; however, register 0 of level 0 is utilized ko hold a control block base which contains the base address in memory of the exception control block or the interrupt control block which in turn is utilized to provide the address of an interrupting or interrupted process.
The interrupt mechanism invention constantly monitors both the current process level of the processor and all requests for interrupt from any module attached to any port A-L
or LMol LMl, RMo~ of system interface unit ~IU 100 of Figure 1. Each interrupt request specifies the null~ber of the 30 processor to be interrupted, the priority (level number) of the ~; ~ -8-9s request, and addresses to identiy the interrupt requestor.
This information is held in each module which may request interrupts, and for most modules it can be set using program-mable interface commands.
Whenever an interrup~ request is present at a level higher than the current level, the SIU 100 raises the higher level interrupt present line to the cognizant processor. If several interrupt requests are present at an equal level, the interrupt invention determines which request is to be passed on to the processor on the basis of priorities established by port number or peripheral unit number.
Referring now to Figure 2 there is shown a block diagram of the inkerrupt and dispatcher mechanism which are shown and described in greater detail on Figures 3-5. An interface unit 201 may typically be the system interface unit (SIU~ of Figure 1 which provides the interfacing paths and control for all the communication between processors and all -~
system modules. Interrupt requests to the processors 103-106 may come from any units attached ports A through L and LMo~RMo. An interrupt request presented to the interface 201 is accompanied by such pertinent information as the interrupt level, processor number and interrupt control block number. A
parity check is performed on this information in unit 201 to determine that the correct information is presented to the priority interrupt hardware and if an error is discovered, a kill-interrupt signal is raised on line 201a. Additionally, since processors 103 and .
, -8a-~o~u~
104 on ports ~l and G respectively and processors 105 and 106 Oll ports F and G may operate as processor pairs respectively, a comparison of the interface number on which ~hey are opera~-ing is made to determine that the appropriate processors are paired together. Typically processor 103 is paired with 104 and when paired in this manner is called processor 0 in this disclosure; alternately processors 105 and 106 are paired to-gether and aTe regarded as processor 1 in this disclosure when so paired. Accordingly, the interrupt level number upon being checked for correctness is presented to the level decode units 202, 204. If an error is discovered during this check, the interrupt requost is aborted until the error is cleared; however, if no error is prese~ted, then the processor switch 203 selects one of the two processor paths 0 or 1 for processor pair 0 or 1 in accordance to the process number and C~IG path bit present-ed to it. The change path (C~IG~ control bit provides software with a means to cause the path 0 or the path 1 logic (Figure 2) to be used in order to get an interrupt request to either processor. Its a redundancy feature that will allow an interrupt to a processor even i~ there ls a hardware failure in the path 0 or path 1 logic i.e. change and use the other logic tree. (See references B and C incorporated herein by reference). For illustration purposes it is assumed that processor path 0 has been selected by the switch 203. The level decode un~t 202 decodes the interrupt level which is presented to it as a 3 bit binary number and presents the decoded information to OR gate circuitry 205. As will be more fully described infra, the OR circuitry 205 collects all the level numbers from all the ports attached to the SIU 100 ~7~7~
and provides level numbers if they are present in any of the ports to the level priority circuitry 206. The level priority circuitry 206 to be more fully described infra with respect to Figure 5 determines the highest level priority number which ;
is present and if the ilighest level priority number present is 0, (i.e. 0 has the highest priority level and 7 has the lowest priority level), then ~he interrupt signal is presented immediate-ly to the path 0 control logic so that ~he processor is immediately interrupted. HoweverJ if none of th0 ports have presented a 0 interrupt level but some of the ports have lower interrupt level number presentJ for example, priority three through seven, it is obvious that according to the convention adopted he:rein that 3 has the highest level priority for the next clock cycle.
A comparison is then made in comparator 207 to determine if the level 3 priority interrupt, which some ports are requesting in this example, is higher or lower than the level number of the process currently executing. Carrying the present example further for illustration purposes, assume that the interrupt level number 3 has a higher priority than the currently executing process which is somewhere below 3, i.e. 4J 5, etc.
~loweverJ because there are many ports in the SIU which have many requestor units coupled to it, more than 1 unit can simultaneously be asking for an interrupt and more than 1 unit can simultaneously have the same priority level number. Obvious-ly the processor requested cannot be assigned to more than one processor simultaneously; accordlngly, a determination is made to determine which process is to receive control of the processor requested when two or more ports simultaneously make an identical level request i.e. in this example a level 3 request. De~ermina-tion is made in accordance to predetermined and fixed prio-rities ~t7~79S
assigned to the different ports of the SIU. Accordingly, a multi-plexor 207 is presented with all those port identifications A
through L, RMo or RM that have requested processor O for the highest priority level task, in this exa~ple level 3. Since all those ports A through ~Ml have different priorities in the hierarchy of performing tasks and this priority is predetermined, then a determination is made in port-priority unit 208 which port A through L or L~o~RMl is entitled to receive control of the processor when more than 1 of these ports have made the same level priority task request. Once the final determination of this priority is made and the appropriate processor notified that a higher priority task is waiting to be performed, then no further actions are r~quired of the priority interrupt mechanism until such time as the requested processor asks for the interrupt data. The data from the highest priority port which has the highest priority level interrupt request is available to a passive input (PIP) cross bar 219 through either a V switch or a W switch mechanism 210, 218, 215, 217 respective-ly on a request from the processor via request logic 209, 216.
The V switch control mechanism 210 develops control signals for providing data to V switch 218 from ports A, C, E, F, J, RMo and an old interrupt. Similarly the W switch control unit 215 develops signals to provide data to W switch 217 from ports L, B, D, G, H, K, RMl Depending therefore which set of control signals have been developed for the highest priority port which has the highest priority interrupt request either the V switch or the W switch 218, 217 respectively will make data available to the processor via the PIP cross bar 219 via control logic 220.
~07~79S
Referring now to Figure 3 a detailed logic block diagram of the interrupt mechanism is shot~. In order to clarify the invention and not clutter up the explanation with hardware which is merely repetitive as to the requesting port or as to the request-ed processor, Figure 3 shows the interrupt mechanism for ane pro-cessor pair P0 comprising processors ~ and G, 103 and 104 respective-ly; the interrupt mechanism for processor pair Pl comprising processors F and E, 132 and 133 respectively is similar to Pigure 3. Moreover, the hardware directly interfacing with the SIU 100 and the priority interrupt unit for each processor P0, Pl is :
enclosed by dash line 300 and is repeated once f.~r ports G and ~l ~rocassor 0) an~ once for ports E and ~ (processor 1). It is to be understood therefore that theIe are as many port 1nterface units 300 as above described and moreover that there are also as many priority interrupt networks as there are processor pairs.
In order to initiate a processor interrupt, an inter-rupt request signal IR is applied to an AND gate 307 from the port making the request which is associated with this particular one 2a of the port interface units 300. Concurrently the requesting port supplies a level priori.ty number LN for the request to gate 301 ancl also a processor number to gate 304. However, since the SIU 100 is not permitted to respond to any request from any module which is not logically operational, an LOP signal is also applied to AND gate 307. With both the interrupt request IR
signal and the 10P signal high AND gate 307 is enabled and provides a high input signal to one înput terminal of each of AND gates 305 and 306 respectively. It also permits the leve].
number data which is a 3 bit binar~ number applied to gate 301 ~)7637~5 to be checked for parity in parity checkin~ unit 302 by pro-vidin~ an enabling signal to it. Since only two processor pairs are considered herein, although the invention may utilize any number of processor pairs, a one bit binary number is sufficient to select processor pair P0 or processor pair Pl as desired. Accordingly, when the one bit processor number PM
is applied to gate 304, one output terminal 306a of gate 304 uill be low. (All amplifier and an inverter may be used in practice). With the signal on output terminal 305a high, a high input si~nal is provided on one input terminal of AND gate 305 thus enabling AND gate 305 and selecting decode unit 308 for processor Pl. By ~he same token, since ~he other output terminal 306a of gate 30~1 is low, the input signal on thq other input ter~llinal of AND gate 306 is low, and AND gate 306 ls not enabled; thus decode unit 309 is not activated for processor PO. By providing a different input code Eor the processor number PN, the procedure would be reversed and the decode unit 309 for processor P0 would be selected over the decode unit 308 oE processor Pl. Upon the salection of the c~ppropriate processor 2a pair, two checks are performed. As has already been noted, a parity check is performed in parity check unit 302 on the 3 bit level nunlber LN and the 1 bit PN. ~Parity generator and checker circuits are commercially available through such companies as Texas Instruments Inc., see pages 9-309 of the Integrated Circuits Catalog for Design Engineers, published by Texas Instruments Inc.). If an error is detected, the interrupt reques~
is aborted, whereas if no error is detected, the level number da*a is sent ~o decode unit 308 or 309 of the selected processor pair Pl or P0. For purposes of simplification, we are assuming in this discussion that processor P0 has been selected in which case level number data is sent to decode unit 309. Another check is performed by the compare unit 303 to verify that every output line on the interface in the SIU from one member of a processor pair, agree with the corresponding line from the other member of pair. If they do not agree at any clock time, an error state is entered and the interrupt request is aborted.
Having selected the appropriate processor and the approp-riate decode unit and having checked the information and the pro-cessor pair for correctness, the 3 bit level number is d~coded in either decode unit 308, 309. In this instance since it is assumed that processor pair P0 has been requested, that decode unit 309 will be performing the decoding. (Decoders are commercially available from such companies as Texas Instruments Inc., see pages 9-149 through 9-213 af the Integrated Circuits Catalog or Design Engineers published by Texas lnstruments Inc., of Dallas, Texas).
The level number from a given requesting unit having been decoded by its appropriate decode unit 309 will be applied in its decoded state to a series of OR gates 310-311. ~Note that for each processor pair P0 and Pl there are as many OR gates as there are predetermined levels of priority of interrupting requests.
In this example since there are 8 levels of priority the O level being the highest priority, there will be 8 OR gates 310-311 for processor pair O and 8 OR gates similar to these for processor pair Pl). The output of each OR gate when enabled provides a signal which is indicative of the level of interrupt with which that particular OR gate is associated. Each OR gate 310-311 has as many inputs as there are ports on the system interface unit -~7g5 SIU 100. If there is a highest level interrupt (i.e. a level n interrupt) on any of the ports of the SIU 100, OR gate 310 which in this example is associated with the level O interrupt, OR gate 310 will provide a high output signal. Since a level O interrupt requires immediate attention, the signal from OR
gate 310 will be stored in flip-flop 312 until the next clock period whereupon it is then presented to the appropriate processor pair PO via the appropriate ports G, ~1 in the SIU.
However, if there is a priority request lower than level O as indicated by a high output signal on any of the OR gates between 310 up to and including gate 311, then a determination must be ma~e as follows: first determines the highest priority request on uny pvrt during the clock cycle that a request is made, and secondly after having determined the highest priority request determine whether or not that highest priority request is higher than the pr;ority of the process currently executing on the processor. Accordingly, all the output signals from the series of OR gates 310-311 are applied to a priority tree 315, which will be describ0d more fully infra with respect to Figure 5, 2n via a series of OR gates 313, 314. Note that the output level signals representing levels 1-7 are applied one each to an OR
gate in the series of OR gates 313-314. Also note that an additional input signal is applied to one each of the series of OR gates 313-314 which represent old levels of priority of processes which were interrupted at some ~ime previous in order to perform a higher priority task. Therefore, it is apparent that not only are the signals representing a level of priority for a new requesting process applied to the priority tree9 but also those signals representing a level of pri.ority of processes that have been previously interrupted and were unable to complete ~ 7~1795 their task. Accordingly the priority tree 315 evaluates all levels of priority present and past, and selects only the highest level exis~ing during the current clock cycle. At any point in time only one high output signal representing the highest level of priority exists. This ex-isting level of priority is then encoded in encoder 316 into a 3 bit binary number representing the highest level of priority currently existing in the requesting and interrupted processes. This priority number is: a) strobed into a 3 bit holding register 320 for temporary storage in case that the processor decides to enter the new level and; b) it is compared in comparator 32~ with the 3 bit binary number representing the level of priority of the currently executing procoss which is sto~ed in register 321. If a priority level number o~ a requesting process or a prior interrupted process is higher than the priority level number of the currently executing process, then a signal is applied to flip-flop 325 which is then transmitted to the appropriate processor pair, in this instance processor pair P0, via ports G, H. Note that the processor has not been interrupted but rather a signal has been conveyed to it, that there is a process waiting which has a higher prio~ity level nu~ber than the currently executing process whereupon the processor itself then takes the appropriate action durîng the next clock cycle.
It should be noted that up to this point in the dis-cussion, the port which îs requesting a processor to perform a higher priority task than the currently executing task has not as yet been identified. It could be that, since there are mul- ;~
tiple ports, more than one port is request;ng the same priority level interrupt as another port~ Therefore, hardware is provided ~07~37~S
to detect such a condition and determine which port is entitled to receive control of the processor. The hardware provided to determine this is in the form of a decode unit 317 which decodes the previously encoded 3 bi~ binary number. The hardware also includes a series of multiplexors 318-319, each multiplexor associated with a given priority level number, and each multi-plexor having as inputs the decoded priority level numbers from all the ports in the SIU 100. (Multiplexors are commercially available from the above mentioned Texas Instruments Inc., of Dallas, Texas). Hence~ priority numbers have been assigned not only on the basis of priority level of the requesting task or process, but also priority numbers have been assigned in a pr~determined fashion to each port of the SIU 100. Generally, the highest priority numbers have been reserved ~or those ports to which are attached data moving devices such as high speed multiplexors into or out of a system, and the lower priority numbers have been assigned to those ports which are associated with low priority attachments such as memories. Accordingly, when the highest priority level of a requesting process is decoded in decoder 317 that signal will be applied to the multiplexor indicating that level of decoded priority. The multiplexor which may typically be a 1 of 8 or 1 of 13 or whatever is needed to cover the number of ports on the SIU 100, will identify all those ports which have the highest level priority request during the currently executing clock cycle.
I~e signals from all those ports having the current highest priority request are then applied to a priority tree 326. Also the output signals from decoder 317a and the series of multi-plexors 322-323 representing priority of prior interrupted ~LV7(~75~5 ~
processes are applied to priority tree 326. Priority tree 326 therefore considers all ports with the highest lev01 of priority that are currently requesting an interrupt or that have been interrupted at a prior clock cycle cmd have not completed their tasks. Priority trea 326 from this input information then seleots that port having the highest priority which also has the highest level priority request on it. An output signal from priority tree 32~ representing that port is then applied to encode unit 328; the encoded result is then temporarily stored in flip-flops 329 or 330 and applied to the appropriate V switch or W switch of processor P0 or Pl. Flip-flop 327 is used to hold the fact that the hîghest level request from the highest priority port is either a new request or an old request which is ~o be resumed. This informat;on is supplied to the processor when the processor is ready for the next process.
A release instruction Cnot shown herein) ~REL) is used to exit processes entered as the result of an interrupt. After a REL the SIU selects for execution the highest priority process waiting for the processor.
This process may be one that was previously interrupted, or a new process to be initiated as the result of an interrupt request. At the same priority level, previously interrupted pro-cesses have priority over new interrupt requests. Through hardware ~see reference B supra) and software loading of the PCR, ~shown in refarence C supra), a processor may present ~o the SIU an inter-rupt at any level, 0-7. Howaver, in order to provide a well-defined response to a REL executed at any level, the PCR bit request-ing a level 7 interrupt is always set.
~)7075~S
If a new process is to be entered as a result of a REL, the processor response is similar to that triggered by a normal interrupt, including acceptance of an interrupt word from the SIU
and access to an ICB (see reference C supra). If a prevlously interrupted process is to be re-entered, the SIU supplies only the level number and the fact ~hat an old process is to be re-entered. Since the process state at the time of its interruption is intact in the register scratchpad, this is the only information required to restart the process.
Referring now to Figure 4 there is shown the dispatcher mechanism which dispatches the data from the appropriate port to the processor requesting such data. The priority interrupt mechanism of Figuro 3 having identified that there is either a level 0 request or a request that has a higher level of priority than the currently executing process has provided a signal apprising the appropriate processor of this condition~ The appropriate processor then requests the data which must be dispatched to the correct processor via a V data switch 218 or a W data switch 217 through the passi~e input cross bar PIP 219.
Accordingly, a control mechanism 400 is provided to develop the control signals for selecting the W data output unit 400a or tho V data output unit 400b. Note by referring to Figure 1 and Figure
4 that processor pair P0 comprising of processors 103, lO~
respectively communicate with other port units via ports H and G in the SIU lO0 respectively. Si~ilarly, processor pair Pl comprising processors 105, 106 communicate with other ports via ports ~, E respectively in SIU 100. Accordingly, therefore, when processor P0 makes a request for data it makes this request through ports H and G and it also receives data through ports H-G
respectively via ~ data output unit 400a or via V data output ~07~79S
unit 400b. The same rationale holds when a request is made by processor pair Pl via ports E, F. The data of the highest level priority process from the highest level priority port to be dispatched to the processor is available to either the W
data output unit 400a or the V data output unit 400b. The W or V control unit 400 develops the control signal ~o selec~
the appropriate one of the W or V data output units. (On Fi~lre 4 the details of only the W data output unit are shown with the V data output unit having similar details~. Once having been notified that there is a higher priority level request awaiting the uppropriate processor requires the following data in order to ef~0ct a proper transfer o control to the requesting process:
(a) the system interfact unit SIU port number available on terminal 450; the interrupt multiport identifier IMID available on terminal 460; th~ interrupt control block number ICBN available on terminal 470; and the error enable signal EE available on terminal 480. The SIU port number identifies the port on SIU to which information is to be sent; the ICBN identifies the control block which has addressing information ~see reference B supra);
and the error enable signal on terminal ~80 and also on terminal ~`
1001 available through software that instructs each module via the SIU to ignore certain classes o~ error i.e. ignore parity, etc.
Part A is utilized to provide the 1'0R" of all ICBN parity checks~ because a part of the înterrupt requesting ports are checked in the W switch unit, whereas others are in the V switch unit, and only one signal must be generated to indicate a specific `
class of errors. Accordingly the logic "ORing" of two like fields ;~ are performed in OR gate 424 from the inputs of Part A and AND
gate 423.
l~V7'3~i When the interrupt of the processor is finally effected, the information in registers 130-133 of the interrupted processors need not be removed since there are 16 registers ~or each priority level as previously discussed.
Referring now to Figure 4 in greater detail -the W or V
control unit is conditioned by applying the inhibit PIP requests (from 437,434) IPR to an input terminal of yates 401-404. This is the signal that has been developed via the error detection hardware 347,434 of Figure 4 and indicates that no interrupt data should be moved from the port with bad data. Also a logically operational signal is applied to another input terminal of gates 401-404 to indicate that the processor attached to that port which is requesting the data is operational i.e. power is turned on, the system is on and physically connected to the appropriate port and is not in an initialized state etc. With the dispatcher unit thus conditioned when an interrupt data request on any of ports G through F is applied to the appropriate gate 401-404, that gate or gates will be enabled. Continuing the instant example where processor pair P0 comprising processors 103-104 coupled to ports H, G is making the request, gates 401-402 would be enabled. If both processor pairs P0 on ports G and H and processor pa:ir Pl on ports E and F ask for data at the same time by providing an interrupt data request IDR to all gates 401-404 at the same time, processor pair P0, ports G and H would take preference oyer processor pair Pl, ports E and F.
This is e~fected ~y an inhibit function which is presented to AND gates 40~, 410, 411 ~07(~7~5 :-and 412 via AND ga~e 402a. Note that when gates 401 and 402 are enabled a high signal is presented as one input to gates 406 and 408 via input terminals 453 and 457 rlespectively; how-ever, an inverse or a low signal is presented to OR gate 402a.
Sinc0 neither of the input signals applied to OR gate 402a are high when gates 401 ai~d 402 are high, then thlere will not be a high output signal from OR gate 402a and accordingly a low signal will be provided as one of the input signals to ANU gates 409-412 via input terminals 459, 465, 466 and 472 respectively; thus AND
gates 409-412 cannot be enabled when this set of conditions apply and processor P0 coupled to ports G, ~I will be enabled and will take preference over processor Pl coupled to ports ~, F. When processor P0 asks for the interrupt data from the interrupt requestor, it does it through the predetermined ports G, ~I which may be either in the ~ or the V data output unit. Accordingly, the W signal for processor P0 on terminals 451 and 455 respective- ;
ly is high; also the input signal on input terminals 452 and 456 respectively on gates 405 and 407 is high, since it is derived from the high output signal of gates 401 and 402 respectively which are high because processor P0 is making the data request.
Therefore, gates 405 and 407 re~spectively are enablecl providing a high signal for G, H port to the passive input cross bar PIP
21~ which indicates to the PIP 219 that data will be forthcoming ~-to it ~ia the W data lines in the W data output unit. By similar reasoning since no high signal is applied to gates 406 and 408 respectively on their input terminals 454 and 458 respectively these gates are not enabled and accordingl~ the V data lines 487 and 491 respectively for the G and H ports are low. Having thus far alerted the PIP cross bar 219 to expect interrupt data 1C~7079 5i ~
from the GJ 11 ports on the W data output unit it must also notify the W data output unit for processor PO to supply this data. It does this through OR gates 406a and 406b respectively.
It will be noted that when output terminals 481 and 486 of gates 405 and 407 respective~ly are high, the converse is true on out-put terminals 482 and 483 of gates 405 and 407 respectively.
Therefore, terminals 482 and 483 apply a low signal to QR gate 406a when gates 405 and 407 respectively are enabled. With a low signaI on OR gate 406a it is enabled and provides a high signal to the multiplexor unit comprising multiplexor elements 413, 414 and 415. (Multiplexor units are describ0d in greater detail infra).
The W control signal developed is applied to W data output unit 400a to indicate that this unit will be supplying data to the passive input PIP cross bar 219. Note by referring to Figure 2 that the W data output unit 217 on Figure 2 which is similar to the W data output unit 400a of Figure 4 selects one port from ports L, B, D, G, ~l, K and RMl to supply the data to the PIP cross bar 219. With the W control signal selecting the appropriate W data output unit the port through which data is to be applied to the PIP cross bar is selected by the 1 o 8 multiplexor units 431-432. The interrupt data such as SIU port number, DMID, ICBN are selected by multiplexor unit 431-432 and eventually transmitted to the PIP cross bar 219. However, it will be noted that prior to the application of this data to the PIP
various error checks are performed. For example there is a parity check performed on the ICBN number in parity check unit 422. If no error is discovered, then the data is applied during the next ~07~7~35 clock cycle to the appropriate port via flip-flop 420 or ~25. If an error is discovered by parity check 422, a high signal is applied to AND gate 423 which goes lo~ when error signal on ter~inal 480 is high. This low output s;gnal from AND gate 423 is applied as one input to OR gate 424 which then provides a high si~lal since at least one of its input terminals is lo~.
As previously described parity check unit PC 422, AND
gate 423 and OR gats 424 are utilized to report parity errors on ICBN's per port. Similarly, CMP 426, AND gate 427 and AND
gate 428 are utilized to report compare errors per processor port pairs. ~RR unit 249 is a wide "OR" structure for develop;ng one line of error status for indicating when enabled that thcre ls some error as seen by the interrupt checking devices.
Referring now to Pigure 5 there is shown the detailed - logic block diagram of the priority tree 315 or 326. Basically, the priority tree is comprised of as many AND gates as there are levels (315) or ports ~325); in this instance ~315) there being 8 levels there would be 8 AND gates 501-505. The AND gates are enabled when all inputs have a high signal. However, a com-plementary signal is obtained by providing an inverter 511-517n.
Therefore, when any AND gate 501-505 is enabled, there will be a high output signal and a low output inverted signal also. Note in the construction of the priority tree that the complementary output signal is applied as an input signal to every AND gate below it. Accordingly~ the complementary output signal 511 from AND gate 501 is applied to all AND gates 502-505. Similarly, the complementary output signal 513 of AND gate 502 is applied as one input signal of all AND gates below it 503-505. Hence, when ; - 2~ -~)7(~795 any one AND gate in the prîority tree is enabled all AND gates above it and below it cannot be enabled and cannot provide a high output signal~ For example, assuming that there is a level 2 r~quest and therefo~e there is a level 2 signal present which is applied as one inpu~ to AND gate 503. Now since there is no level O or level 1 signal present, AND gates 501 and 502 cannot be enabled. Therefore~ the output signal OD terminals 510 and 512 is low and the output signal on complementary terminals 511, 513 is high. Note that the signal from output terminal 511 is applied to input terminal 519 of AND gate 503 whereas the output signal from terminal S13 is applied to input terminal 520 of AND gate 503. Hence all the input terminals of AND gate 503 are high and the AND gate is enabled and the high si~lal is provided on terminal 514. Also, a complementary low signal is generated on output terminal 515 which is then applied to all AND gates below AND gate 503 and accordingly none of the AND
gates 504-505 can be enabled. Hence it is shown that with a given set of level signals present only one AND gate can be enabled allowing a signal to be generated which indicates the highest priority level of all the requestors.
Referring to Figure 6 there is shown a typical 1 of 2 multiplexor. It is comprised of AND gates 601-fil6 having input data signals DOOa to D41a on AND gates 602-611. Enabled signals G2Aa-G2Ba are applied to AND gate 601 and control signal Sla is applied to amplifier/inverter 617. Data out signals ZOa-Z4a are abstracted from AND gates 612-616. Two completely in-dependent 5-bit 1 of 2 ~ated data selection is determined by the S input, whereas the outputs are enabled by the AND gate of the G inputs.
~7q~S
The sOOlean expressions for Figure 6 are as follows wnere there is a 1 to 1 correspondence between inputs and outputs of Figure 6 and the Boolean expressions:
For a = A, B
ZOa = (G2Aa.G2Ba).((DOOa.~l)+(DOla.Sl)) Zla = (G2Aa.G2Ba).((DlOa.Sl)~(Dlla.Sl)) Z2a = (G2Aa.G2Ba).((D20a.Sl)~(G21a.Sl)) Z3a = (G2Aa.G2Ba).((D30a.Sl)+(D31a.Sl)) Z4a = (G2Aa.G2Ba).((D40a.Sl)~(D41a.Sl)) Relating the above elements of Figures 6 to the pertinent elements of Figure 4, there is a relationship as follows:
617 and 413; 602 and 414; 603 and 415; inputs 492 and noOa;
input 493 and DOla. Similarly the remainder of the gates and inputs may be paired of~ as above with units 414 and 415. I~hen }5 control input Sla is O it can readily be seen that data on input 493 is switched, whereas then the control input is 1, data on input 493 is switched. (See set o~ equations above).
Referring now to Figure 7 there is shown a typical 1 of 4 multiplexor. As in Figure 6 input data signals are applied to AiID gates 702-705, enable signals are applied to A~D gate 701 and control signals are applied to amplifier/inverters 707-708 with Data Out signals being abstracted on AiID gate 706.
The Boolean expressions for Figure 7 are as follows:
For a = A, B, C, D, E
Za - (G4A.G4B).((DOa.S2.~l) + (Dla.S2.Sl)+(D2a.S2.Sl)-~(D3a.S2.Sl)) , ~(~7~7335 Referring now to Figure 8 there is shown a typical 1 of 8 data multiplexor. Data In signals DOa-D7a are applied to AND gates 802-809; enable signals G8A-G8B are applied to ~ND
gate 801; and control signals Sl-S4 are applied to amplifier/
inverters 811-813; while 1 of 8 data is abstracted from AND
gate 810.
The Boolean expression for Figure 8 is as follows:
For a - A, B, C
2a = (G8A.G8B).((DOa.S4.S2.Sl) +(Dla.S4.S2.Sl)+(D2a.S4.S2.Sl)+
(D3a.S4.S2.Sl) ~(D4a.S4.S2.Sl)+
~D5a.S4.S2.Sl)+(D6a.S4.S2.Sl)+
(D7a.S4.S2.Sl)) Having shown and described a preferred embocliment of the invention, those skilled in the art wlll realize that man~
variations and modifications may be made to affect the described invention and still be within the scope of the claimed invention.
Thus, many of the elements indicated above may be altered or replaced by different elements which will provide the same result ~ and fall within the spirit of the claimed invention. It is the intention, therefore, to limit the invention only as indicated by tlle scope of the claims.
What is claimed is:
,~
!
respectively communicate with other port units via ports H and G in the SIU lO0 respectively. Si~ilarly, processor pair Pl comprising processors 105, 106 communicate with other ports via ports ~, E respectively in SIU 100. Accordingly, therefore, when processor P0 makes a request for data it makes this request through ports H and G and it also receives data through ports H-G
respectively via ~ data output unit 400a or via V data output ~07~79S
unit 400b. The same rationale holds when a request is made by processor pair Pl via ports E, F. The data of the highest level priority process from the highest level priority port to be dispatched to the processor is available to either the W
data output unit 400a or the V data output unit 400b. The W or V control unit 400 develops the control signal ~o selec~
the appropriate one of the W or V data output units. (On Fi~lre 4 the details of only the W data output unit are shown with the V data output unit having similar details~. Once having been notified that there is a higher priority level request awaiting the uppropriate processor requires the following data in order to ef~0ct a proper transfer o control to the requesting process:
(a) the system interfact unit SIU port number available on terminal 450; the interrupt multiport identifier IMID available on terminal 460; th~ interrupt control block number ICBN available on terminal 470; and the error enable signal EE available on terminal 480. The SIU port number identifies the port on SIU to which information is to be sent; the ICBN identifies the control block which has addressing information ~see reference B supra);
and the error enable signal on terminal ~80 and also on terminal ~`
1001 available through software that instructs each module via the SIU to ignore certain classes o~ error i.e. ignore parity, etc.
Part A is utilized to provide the 1'0R" of all ICBN parity checks~ because a part of the înterrupt requesting ports are checked in the W switch unit, whereas others are in the V switch unit, and only one signal must be generated to indicate a specific `
class of errors. Accordingly the logic "ORing" of two like fields ;~ are performed in OR gate 424 from the inputs of Part A and AND
gate 423.
l~V7'3~i When the interrupt of the processor is finally effected, the information in registers 130-133 of the interrupted processors need not be removed since there are 16 registers ~or each priority level as previously discussed.
Referring now to Figure 4 in greater detail -the W or V
control unit is conditioned by applying the inhibit PIP requests (from 437,434) IPR to an input terminal of yates 401-404. This is the signal that has been developed via the error detection hardware 347,434 of Figure 4 and indicates that no interrupt data should be moved from the port with bad data. Also a logically operational signal is applied to another input terminal of gates 401-404 to indicate that the processor attached to that port which is requesting the data is operational i.e. power is turned on, the system is on and physically connected to the appropriate port and is not in an initialized state etc. With the dispatcher unit thus conditioned when an interrupt data request on any of ports G through F is applied to the appropriate gate 401-404, that gate or gates will be enabled. Continuing the instant example where processor pair P0 comprising processors 103-104 coupled to ports H, G is making the request, gates 401-402 would be enabled. If both processor pairs P0 on ports G and H and processor pa:ir Pl on ports E and F ask for data at the same time by providing an interrupt data request IDR to all gates 401-404 at the same time, processor pair P0, ports G and H would take preference oyer processor pair Pl, ports E and F.
This is e~fected ~y an inhibit function which is presented to AND gates 40~, 410, 411 ~07(~7~5 :-and 412 via AND ga~e 402a. Note that when gates 401 and 402 are enabled a high signal is presented as one input to gates 406 and 408 via input terminals 453 and 457 rlespectively; how-ever, an inverse or a low signal is presented to OR gate 402a.
Sinc0 neither of the input signals applied to OR gate 402a are high when gates 401 ai~d 402 are high, then thlere will not be a high output signal from OR gate 402a and accordingly a low signal will be provided as one of the input signals to ANU gates 409-412 via input terminals 459, 465, 466 and 472 respectively; thus AND
gates 409-412 cannot be enabled when this set of conditions apply and processor P0 coupled to ports G, ~I will be enabled and will take preference over processor Pl coupled to ports ~, F. When processor P0 asks for the interrupt data from the interrupt requestor, it does it through the predetermined ports G, ~I which may be either in the ~ or the V data output unit. Accordingly, the W signal for processor P0 on terminals 451 and 455 respective- ;
ly is high; also the input signal on input terminals 452 and 456 respectively on gates 405 and 407 is high, since it is derived from the high output signal of gates 401 and 402 respectively which are high because processor P0 is making the data request.
Therefore, gates 405 and 407 re~spectively are enablecl providing a high signal for G, H port to the passive input cross bar PIP
21~ which indicates to the PIP 219 that data will be forthcoming ~-to it ~ia the W data lines in the W data output unit. By similar reasoning since no high signal is applied to gates 406 and 408 respectively on their input terminals 454 and 458 respectively these gates are not enabled and accordingl~ the V data lines 487 and 491 respectively for the G and H ports are low. Having thus far alerted the PIP cross bar 219 to expect interrupt data 1C~7079 5i ~
from the GJ 11 ports on the W data output unit it must also notify the W data output unit for processor PO to supply this data. It does this through OR gates 406a and 406b respectively.
It will be noted that when output terminals 481 and 486 of gates 405 and 407 respective~ly are high, the converse is true on out-put terminals 482 and 483 of gates 405 and 407 respectively.
Therefore, terminals 482 and 483 apply a low signal to QR gate 406a when gates 405 and 407 respectively are enabled. With a low signaI on OR gate 406a it is enabled and provides a high signal to the multiplexor unit comprising multiplexor elements 413, 414 and 415. (Multiplexor units are describ0d in greater detail infra).
The W control signal developed is applied to W data output unit 400a to indicate that this unit will be supplying data to the passive input PIP cross bar 219. Note by referring to Figure 2 that the W data output unit 217 on Figure 2 which is similar to the W data output unit 400a of Figure 4 selects one port from ports L, B, D, G, ~l, K and RMl to supply the data to the PIP cross bar 219. With the W control signal selecting the appropriate W data output unit the port through which data is to be applied to the PIP cross bar is selected by the 1 o 8 multiplexor units 431-432. The interrupt data such as SIU port number, DMID, ICBN are selected by multiplexor unit 431-432 and eventually transmitted to the PIP cross bar 219. However, it will be noted that prior to the application of this data to the PIP
various error checks are performed. For example there is a parity check performed on the ICBN number in parity check unit 422. If no error is discovered, then the data is applied during the next ~07~7~35 clock cycle to the appropriate port via flip-flop 420 or ~25. If an error is discovered by parity check 422, a high signal is applied to AND gate 423 which goes lo~ when error signal on ter~inal 480 is high. This low output s;gnal from AND gate 423 is applied as one input to OR gate 424 which then provides a high si~lal since at least one of its input terminals is lo~.
As previously described parity check unit PC 422, AND
gate 423 and OR gats 424 are utilized to report parity errors on ICBN's per port. Similarly, CMP 426, AND gate 427 and AND
gate 428 are utilized to report compare errors per processor port pairs. ~RR unit 249 is a wide "OR" structure for develop;ng one line of error status for indicating when enabled that thcre ls some error as seen by the interrupt checking devices.
Referring now to Pigure 5 there is shown the detailed - logic block diagram of the priority tree 315 or 326. Basically, the priority tree is comprised of as many AND gates as there are levels (315) or ports ~325); in this instance ~315) there being 8 levels there would be 8 AND gates 501-505. The AND gates are enabled when all inputs have a high signal. However, a com-plementary signal is obtained by providing an inverter 511-517n.
Therefore, when any AND gate 501-505 is enabled, there will be a high output signal and a low output inverted signal also. Note in the construction of the priority tree that the complementary output signal is applied as an input signal to every AND gate below it. Accordingly~ the complementary output signal 511 from AND gate 501 is applied to all AND gates 502-505. Similarly, the complementary output signal 513 of AND gate 502 is applied as one input signal of all AND gates below it 503-505. Hence, when ; - 2~ -~)7(~795 any one AND gate in the prîority tree is enabled all AND gates above it and below it cannot be enabled and cannot provide a high output signal~ For example, assuming that there is a level 2 r~quest and therefo~e there is a level 2 signal present which is applied as one inpu~ to AND gate 503. Now since there is no level O or level 1 signal present, AND gates 501 and 502 cannot be enabled. Therefore~ the output signal OD terminals 510 and 512 is low and the output signal on complementary terminals 511, 513 is high. Note that the signal from output terminal 511 is applied to input terminal 519 of AND gate 503 whereas the output signal from terminal S13 is applied to input terminal 520 of AND gate 503. Hence all the input terminals of AND gate 503 are high and the AND gate is enabled and the high si~lal is provided on terminal 514. Also, a complementary low signal is generated on output terminal 515 which is then applied to all AND gates below AND gate 503 and accordingly none of the AND
gates 504-505 can be enabled. Hence it is shown that with a given set of level signals present only one AND gate can be enabled allowing a signal to be generated which indicates the highest priority level of all the requestors.
Referring to Figure 6 there is shown a typical 1 of 2 multiplexor. It is comprised of AND gates 601-fil6 having input data signals DOOa to D41a on AND gates 602-611. Enabled signals G2Aa-G2Ba are applied to AND gate 601 and control signal Sla is applied to amplifier/inverter 617. Data out signals ZOa-Z4a are abstracted from AND gates 612-616. Two completely in-dependent 5-bit 1 of 2 ~ated data selection is determined by the S input, whereas the outputs are enabled by the AND gate of the G inputs.
~7q~S
The sOOlean expressions for Figure 6 are as follows wnere there is a 1 to 1 correspondence between inputs and outputs of Figure 6 and the Boolean expressions:
For a = A, B
ZOa = (G2Aa.G2Ba).((DOOa.~l)+(DOla.Sl)) Zla = (G2Aa.G2Ba).((DlOa.Sl)~(Dlla.Sl)) Z2a = (G2Aa.G2Ba).((D20a.Sl)~(G21a.Sl)) Z3a = (G2Aa.G2Ba).((D30a.Sl)+(D31a.Sl)) Z4a = (G2Aa.G2Ba).((D40a.Sl)~(D41a.Sl)) Relating the above elements of Figures 6 to the pertinent elements of Figure 4, there is a relationship as follows:
617 and 413; 602 and 414; 603 and 415; inputs 492 and noOa;
input 493 and DOla. Similarly the remainder of the gates and inputs may be paired of~ as above with units 414 and 415. I~hen }5 control input Sla is O it can readily be seen that data on input 493 is switched, whereas then the control input is 1, data on input 493 is switched. (See set o~ equations above).
Referring now to Figure 7 there is shown a typical 1 of 4 multiplexor. As in Figure 6 input data signals are applied to AiID gates 702-705, enable signals are applied to A~D gate 701 and control signals are applied to amplifier/inverters 707-708 with Data Out signals being abstracted on AiID gate 706.
The Boolean expressions for Figure 7 are as follows:
For a = A, B, C, D, E
Za - (G4A.G4B).((DOa.S2.~l) + (Dla.S2.Sl)+(D2a.S2.Sl)-~(D3a.S2.Sl)) , ~(~7~7335 Referring now to Figure 8 there is shown a typical 1 of 8 data multiplexor. Data In signals DOa-D7a are applied to AND gates 802-809; enable signals G8A-G8B are applied to ~ND
gate 801; and control signals Sl-S4 are applied to amplifier/
inverters 811-813; while 1 of 8 data is abstracted from AND
gate 810.
The Boolean expression for Figure 8 is as follows:
For a - A, B, C
2a = (G8A.G8B).((DOa.S4.S2.Sl) +(Dla.S4.S2.Sl)+(D2a.S4.S2.Sl)+
(D3a.S4.S2.Sl) ~(D4a.S4.S2.Sl)+
~D5a.S4.S2.Sl)+(D6a.S4.S2.Sl)+
(D7a.S4.S2.Sl)) Having shown and described a preferred embocliment of the invention, those skilled in the art wlll realize that man~
variations and modifications may be made to affect the described invention and still be within the scope of the claimed invention.
Thus, many of the elements indicated above may be altered or replaced by different elements which will provide the same result ~ and fall within the spirit of the claimed invention. It is the intention, therefore, to limit the invention only as indicated by tlle scope of the claims.
What is claimed is:
,~
!
Claims (11)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a data processing system having a plurality of processors coupled to an interface unit via predetermined processor communication channels each processor being selectively controlled by selected ones of a first group of processes, said data processing system also having a plurality of peripheral devices also coupled to said interface unit via predetermined peripheral channels for communicating with each other and with said processors, said data processing system further having monitoring means for monitoring request signals from a plurality of a second group of processes requesting control and vying with each other for control of one of said processors via one of said processor communication channels, each process and each peripheral channel being associated with a predetermined level of priority, a priority interrupt mechanism included in said interface unit for determining, before interrupting one of said selected first processes, the highest priority peripheral channel of a highest priority second process of said second group of processes requesting control of one of said processor communication channels, and for further determining whether or not said one of said first processes on said one of said processors has a higher priority than said highest priority peripheral channel of the highest priority second process requesting control of said one of said processors, said priority mechanism comprising:
a. first means responsive to said monitoring means for directing said request signals from said second group of processes to one of said processor communication channels requested by said second group of processes;
b. second means, coupled to said first means, for determining the highest priority of said request signals from said second group of Processes;
c. third means for storing the priority level of said currently executing first process on said selectively controlled one of said processors;
d. fourth means coupled to said second means for determining the highest priority level of each peripheral channel of said second group of processes requesting assignment to one of said selected processors; and e. fifth means, coupled to said second, third and fourth means, for determining the higher priority level between said currently executing first process and the highest priority peripheral channel of said second process having said highest priority request.
a. first means responsive to said monitoring means for directing said request signals from said second group of processes to one of said processor communication channels requested by said second group of processes;
b. second means, coupled to said first means, for determining the highest priority of said request signals from said second group of Processes;
c. third means for storing the priority level of said currently executing first process on said selectively controlled one of said processors;
d. fourth means coupled to said second means for determining the highest priority level of each peripheral channel of said second group of processes requesting assignment to one of said selected processors; and e. fifth means, coupled to said second, third and fourth means, for determining the higher priority level between said currently executing first process and the highest priority peripheral channel of said second process having said highest priority request.
2. The apparatus as recited in claim 1 wherein there are eight levels of priority 0-7 with level 0 being the highest level of priority and level 7 being the lowest level of priority and wherein said second means include zero level determining means and further including eighth means for providing an interrupt signal to said selected one of said processors upon the detection of a level 0 level priority.
3. The apparatus as recited in claim 1 including a plural-ity of sets of registers each of said sets of registers associated with a predetermined priority level and with a first of said sets of registers which. has a level of priority equal to said first level of priority of said first one of said plurality of processes, storing signals representing instructions of said currently executing first one of said processes, said apparatus further including interrupting means for interrupting said currently executing first one of said processes by said second process having a higher priority level than said currently executing first process, whereby the signals representing instructions of said currently executing first one of said processes remain stored in said first set of registers during execution of the interrupting said second process.
4. The apparatus as recited in claim 3 including level storing means coupled to said fifth means for storing the priority level of the highest priority second process of the highest priority peripheral device.
5. The apparatus as recited in claim 4 including sixth means coupled to said third and said level storing means for comparing the contents of said third means with the contents of said level storing means.
6. The apparatus as recited in claim 5 including seventh means coupled to said sixth means for indicating to said selected one of said processors which of said third or fifth means is storing the smaller value i.e. greater level of priority.
7. The apparatus as recited in claim 5 wherein the requests are in binary code and identify the processor being requested and the priority level number of the process making such request and further including ninth means coupled to said first and second means for decoding the binary code identifying the priority level of the process requesting said selected one of said processors.
8. The apparatus as recited in claim 7 including tenth means coupled to said first and ninth means for checking the coded requests for error.
9. In a data processing system having a plurality of peripheral units and one processor for sequentially executing instructions of a first one of a plurality of processes having a first level of priority, each of said processes having a priority level based on the relative importance of said plurality of processes, and with any of said processes generat-ing signals for requesting control of said one processor, said one processor having a plurality of sets of registers each of said sets of registers associated with a predetermined priority level and with a first of said sets of registers which has a level of priority equal to said first level of priority of said first one of said plurality of processes, storing signals representing instructions of said first one of said processes, said data processing system further including at least one peripheral channel for each one of said peripheral units for communication between said peripheral units and said processor, each peripheral channel having a priority level based on the relative importance of the peripheral unit associated with the peripheral channel, and with any of said peripheral channels also generating signals for requesting assignment to said one processor, a priority apparatus for determining priority among said requesting processes and among said peripheral channels before said processor is interrupted, said priority apparatus comprising:
a. first means for determining the highest priority level of said peripheral channels requesting assignment to said one processor;
b. second means coupled to said first means for determining the highest priority level among said requesting processes;
c. third means, coupled to said first and second means and to said first of said sets of registers, for comparing the priority level of said requesting processes requesting peripheral channels and said first one of said plurality of processes; and, d, fourth means, coupled to said third means for notifying said processor that a process having a priority level among the requesting processes higher than the priority level of said first one of said plurality of processes desires to interrupt said first one of said plurality of processes.
a. first means for determining the highest priority level of said peripheral channels requesting assignment to said one processor;
b. second means coupled to said first means for determining the highest priority level among said requesting processes;
c. third means, coupled to said first and second means and to said first of said sets of registers, for comparing the priority level of said requesting processes requesting peripheral channels and said first one of said plurality of processes; and, d, fourth means, coupled to said third means for notifying said processor that a process having a priority level among the requesting processes higher than the priority level of said first one of said plurality of processes desires to interrupt said first one of said plurality of processes.
10. The priority apparatus as recited in claim 9 wherein said first one of the plurality of processes has a predeter-mined first priority level for a predetermined portion of said first process for executing at one priority level and a second priority level of another predetermined portion of said first process for executing at a second priority level and is associ-ated with fifth means for interrupting itself after said pre-determined portion of said first one of said processes has been executed, whereby said another portion of said first one of said processes then competes with the other requesting processes for control of said processor.
11. The apparatus as recited in claim 9 including sixth means coupled to said third means, for determining that at least two of said requesting processes have a priority rank higher than said first one of said plurality of processes and further including seventh means for determining which of said at least two of said requesting processes is utilizing the higher priority peripheral channel to communicate between said processor and one of said peripheral units.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/562,315 US4001783A (en) | 1975-03-26 | 1975-03-26 | Priority interrupt mechanism |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1070795A true CA1070795A (en) | 1980-01-29 |
Family
ID=24245781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA244,791A Expired CA1070795A (en) | 1975-03-26 | 1976-02-02 | Priority interrupt mechanism |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4001783A (en) |
| JP (1) | JPS6022372B2 (en) |
| BE (1) | BE840016A (en) |
| CA (1) | CA1070795A (en) |
| DE (1) | DE2611907A1 (en) |
| FR (1) | FR2305789A1 (en) |
Families Citing this family (59)
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| US4381540A (en) * | 1978-10-23 | 1983-04-26 | International Business Machines Corporation | Asynchronous channel error mechanism |
| US4271467A (en) * | 1979-01-02 | 1981-06-02 | Honeywell Information Systems Inc. | I/O Priority resolver |
| FR2445989B1 (en) * | 1979-01-02 | 1987-06-26 | Honeywell Inf Systems | PRIORITY DETERMINATION AND INTERRUPTION DEVICE OF A DATA PROCESSING SYSTEM |
| US4309753A (en) * | 1979-01-03 | 1982-01-05 | Honeywell Information System Inc. | Apparatus and method for next address generation in a data processing system |
| JPS55134721A (en) * | 1979-04-06 | 1980-10-20 | Hitachi Ltd | Electronic engine controlling method |
| DE3072043D1 (en) * | 1979-04-06 | 1987-11-19 | Hitachi Ltd | Electronic type engine control method and apparatus |
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| FR2500659B1 (en) * | 1981-02-25 | 1986-02-28 | Philips Ind Commerciale | DEVICE FOR THE DYNAMIC ALLOCATION OF THE TASKS OF A MULTIPROCESSOR COMPUTER |
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| JPH0326591U (en) * | 1989-07-25 | 1991-03-18 | ||
| DE3931924A1 (en) * | 1989-09-25 | 1991-04-04 | Standard Elektrik Lorenz Ag | CONTROL OF THE TIME ASSIGNMENT OF DATA PROCESSING PERFORMANCE OF A COMPUTER |
| DE58908886D1 (en) * | 1989-09-29 | 1995-02-23 | Siemens Nixdorf Inf Syst | Method and interrupt control for handling interrupt requests during input / output operations in a virtual machine system. |
| US5371872A (en) * | 1991-10-28 | 1994-12-06 | International Business Machines Corporation | Method and apparatus for controlling operation of a cache memory during an interrupt |
| JP2854474B2 (en) * | 1992-09-29 | 1999-02-03 | 三菱電機株式会社 | Bus use request arbitration device |
| JP3676882B2 (en) | 1996-06-12 | 2005-07-27 | 株式会社リコー | Microprocessor and its peripheral devices |
| JP4151198B2 (en) * | 1999-06-23 | 2008-09-17 | 株式会社デンソー | Interrupt controller and microcomputer |
| US6971043B2 (en) * | 2001-04-11 | 2005-11-29 | Stratus Technologies Bermuda Ltd | Apparatus and method for accessing a mass storage device in a fault-tolerant server |
| WO2004114132A1 (en) * | 2003-06-20 | 2004-12-29 | Fujitsu Limited | Interrupt control method, interrupt control device, and interrupt control program |
| US20050021894A1 (en) * | 2003-07-24 | 2005-01-27 | Renesas Technology America, Inc. | Method and system for interrupt mapping |
| JP4241462B2 (en) * | 2004-03-26 | 2009-03-18 | 株式会社デンソー | Control unit and microcomputer |
| US8533716B2 (en) * | 2004-03-31 | 2013-09-10 | Synopsys, Inc. | Resource management in a multicore architecture |
| US9038070B2 (en) | 2004-09-14 | 2015-05-19 | Synopsys, Inc. | Debug in a multicore architecture |
| JP2009251802A (en) * | 2008-04-03 | 2009-10-29 | Panasonic Corp | Multiprocessor system and multiprocessor system interrupt control method |
| KR101443291B1 (en) * | 2008-09-02 | 2014-09-25 | 삼성전자주식회사 | Image forming apparatus associated with network and the method for setting network related information thereof |
| US8850450B2 (en) * | 2012-01-18 | 2014-09-30 | International Business Machines Corporation | Warning track interruption facility |
| US9104508B2 (en) | 2012-01-18 | 2015-08-11 | International Business Machines Corporation | Providing by one program to another program access to a warning track facility |
| US9110878B2 (en) * | 2012-01-18 | 2015-08-18 | International Business Machines Corporation | Use of a warning track interruption facility by a program |
| US9678564B2 (en) * | 2012-12-21 | 2017-06-13 | Nxp B.V. | Multiprocessor system with interrupt distributor |
| CN113162606B (en) * | 2021-03-30 | 2023-04-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-priority control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3421150A (en) * | 1966-08-26 | 1969-01-07 | Sperry Rand Corp | Multiprocessor interrupt directory |
| US3702462A (en) * | 1967-10-26 | 1972-11-07 | Delaware Sds Inc | Computer input-output system |
| US3648252A (en) * | 1969-11-03 | 1972-03-07 | Honeywell Inc | Multiprogrammable, multiprocessor computer system |
| GB1240978A (en) * | 1970-03-25 | 1971-07-28 | Ibm | Data processing systems |
| US3676861A (en) * | 1970-12-30 | 1972-07-11 | Honeywell Inf Systems | Multiple mask registers for servicing interrupts in a multiprocessor system |
| GB1397438A (en) * | 1971-10-27 | 1975-06-11 | Ibm | Data processing system |
| US3812463A (en) * | 1972-07-17 | 1974-05-21 | Sperry Rand Corp | Processor interrupt pointer |
| US3812473A (en) * | 1972-11-24 | 1974-05-21 | Ibm | Storage system with conflict-free multiple simultaneous access |
-
1975
- 1975-03-26 US US05/562,315 patent/US4001783A/en not_active Expired - Lifetime
-
1976
- 1976-02-02 CA CA244,791A patent/CA1070795A/en not_active Expired
- 1976-03-20 DE DE19762611907 patent/DE2611907A1/en not_active Withdrawn
- 1976-03-25 BE BE165546A patent/BE840016A/en not_active IP Right Cessation
- 1976-03-25 FR FR7608759A patent/FR2305789A1/en active Granted
- 1976-03-26 JP JP51032696A patent/JPS6022372B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6022372B2 (en) | 1985-06-01 |
| US4001783A (en) | 1977-01-04 |
| JPS51120643A (en) | 1976-10-22 |
| FR2305789A1 (en) | 1976-10-22 |
| FR2305789B1 (en) | 1979-07-20 |
| BE840016A (en) | 1976-07-16 |
| DE2611907A1 (en) | 1976-10-07 |
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